Design and Construction of a GSM Based Controlled System for a Power Sub-Station

7/28/2019 Design and Construction of a GSM Based Controlled System for a Power Sub-Station

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MARK WILSON B. Eng (Hons) REGENT GHANA Page 1

CHAPTER ONE

1.0 INTRODUCTION

Automation is the key to modernization and has now been conceptually understood as a

way to increase efficiency and productivity. [1] To improve the power quality efficient

operation and monitoring of high voltage and a low voltage substations is very important.

There is a need to ensure power supply at the proper voltage and frequency with the least

number of duration of interruptions and with minimum financial and return on

investment. [2]

The use of cellular phone to control electrical power distribution of a substation is now

taken off. Not only does GSM based controlling lead to much power efficiency and better

decision systems, it also brings intangibles like safety to the system. [3]

A power substation transforms voltage from high to low or reverse. A power substation

generally consists of switching equipment, protection equipment, transformers, control

equipment, circuit breakers, shunt reactors and capacitor banks. Power substation

ensures that the supply to the end users is reliable, efficient, stable and safe. [4]

The supply to the substation is connected from the national grid through a step down

power transformer and the circuit breakers. A relay is connected to each phase of the

incomer and outgoing feeder via the circuit breakers. Whenever there is faulty condition

e.g. earth fault, over current fault, short circuit fault and surges, the relay will sense it and

depending on its setting will initiate action on circuit breaker to trip the circuit. [5]


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A relay is an electromechanical switch that opens and closes with electromagnetic coil.

As current flows through the coil, it generates a magnetic field that attract the plunger,

pulling it down. [6] The function of a circuit breaker in electrical circuit is to

automatically operate to safeguard the circuit and other associated equipment whenever

there is power surge, faulty current, short circuit and earth fault in the circuit. Once the

fault is detected, contact within the circuit breaker must be open to interrupt the supply.

[7]

In the past, substations were operated manually and as complexity of distribution

networks grew, it became economically necessary to automate supervision and control of

substations from centrally attended point, to allow overall coordination in case of

emergencies and to reduce operational cost. [8]

The automation of a substation monitoring and controlling using microcontroller

AT89C51 will be studied. A message would be sent to GSM modem through RS232

cable connected to the microcontroller. The microcontroller AT89C51 is interfaced to the

relays which switch (on/off) of the circuit breaker coil. A PC is connected to the

microcontroller using MAX 232 IC. GSM modem receives the data from control circuit

and sends an input to microcontroller. The microcontroller verifies with reference

specifications, if the logged data is abnormal, relay control will take place. [9]

1.1 Microcontroller

Microcontroller, as the name suggests, are small controllers. These are like single chip

computers that are often embedded into systems to function as processing /controllers unit. For

example, microcontroller is used to measure and control temperature of a furnace and oven,


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speed of electric motor, deflection, pressure of boiler etc. It is used in automatic control of car

to control air and fuel mixture to test the condition of the engine, brakes etc. Microcontrollers

are used to in military equipment, radars, and tanks etc. where automation is needed. [10]

1.2Types of MicrocontrollersThe various types of microcontrollers used in industries today are 8 bits, 16 bits and 32

bits. These are classified below:

The 8-Bit Microcontroller

When the ALU performs arithmetic and logical operations on a byte (8-bits) at an

instruction, the microcontroller is an 8-bit microcontroller. The internal bus width of 8-bit

microcontroller is of 8-bit. Examples of 8-bit microcontrollers are Intel 8051 family and

Motorola MC68HC11 family. [11]


When the ALU performs arithmetic and logical operations on a word (16-bits) at an

instruction, the microcontroller is a 16-bit microcontroller. The internal bus width of 16-

bit microcontroller is of 16-bit. Examples of 16-bit microcontrollers are Intel 8096 family

and Motorola MC68HC12 and MC68332 families. The performance and computing

capability of 16 bit microcontrollers are enhanced with greater precision as compared to

the 8-bit microcontrollers. [12]


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When the ALU performs arithmetic and logical operations on a double word (32- bits) at

an instruction, the microcontroller is a 32-bit microcontroller. The internal bus width of

32-bit microcontroller is of 32-bit. Examples of 32-bit microcontrollers are Intel 80960

family and Motorola M683xx and Intel/Atmel 251 family. The performance and

computing capability of 32 bit microcontrollers are enhanced with greater precision as

compared to the 16-bit microcontrollers. [13]


computers that are often embedded into systems to function as processing /controllers unit.

For example, microcontroller is used to measure and control temperature of a furnace and

oven, speed of electric motor, deflection, pressure of boiler etc. It is used in automatic control

of car to control air and fuel mixture to test the condition of the engine, brakes etc.

Microcontrollers are used to in military equipment, radars, and tanks etc. where automation is

needed. [14]

1.3 Microcontroller AT89C51

1.3.1 Introduction to AT89C51

The Intel 8051contains two separate buses for the program and data. It is based on an 8

bit central processing unit with an 8 bit accumulator and another 8 bit register as main

processing blocks.AT89C51 is supported with on-chip peripheral functions like I/O ports,

Timers/Counters, serial communication port. The AT89C51 is a low-power, high-

performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and

erasable read only memory (PEROM). [15]


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1.4 Problem Statement

Electric power transmission and distribution companies in developing countries

continuously encounter challenges of providing efficient and reliable power supply to the

end users at competitive price. In the event of power failure which could be due to

equipment failure, partial short circuit, lighting strikes, accidents, natural catastrophes

and power disturbances. Outages occur in long service hours.

The delay in long service period could be attributed to the reasons emulated below

In event of maintenance work, personnel have to move from sub-station to sub-

station to carry out switching operations.

If the network is faulty, personnels has to drive from sub-station to sub-station to

isolate the lines.

If the sub-station is sited at the middle of the city, traffic conjunction may delay

the operations.

If the substation is sited on top of a hill driving to and fro may delay the operation

Delay in solving simple problem may result in huge revenue lost.

Energy loss as a result of these problems stated above will also affect productivity

The safety of personnel switching the circuit breaker manually could be in danger.

In view of these it is advisable to control the substation remotely to avoid time wasting

and save human lives during switching operations.


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1.5 Objectives

The aim of this study is to design and construct a GSM based controlled system for a

power sub-station.

To achieve this, a general pocket radio services (GPRS) or GSM modem was connected

to a personal computer to receive a short message service (SMS) from a cell phone.

The short message services (SMS) then passes through an RS 232 cable through Max

232Ic to the microcontroller 89C51.

The microcontroller 89C51 send signal to the relay which operate the circuit breaker

ON/OFF.

.


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CHAPTER TWO

2.0 LITERATURE REVIEW

The utilization of GSM mobile phone and it associate benefit cannot be over emphasis.

This technology has emerged as a useful facility to make life easy and safe. It is

enhancing development worldwide. Several research works has been done on automation

of power substation. [16]. Some of the research works on design and construction of

automatic unit to control power sub-station by other authors are as follows:

On January 23, 2009, Moxa, one of manufacturer of world leading network realize a

white paper on embedded computers for substation automation. Power substations play a

critical role in transporting electricity from power plants to homes, businesses, and

factories. However, a typical power grid can be comprised of hundreds of substations that

need to monitored and controlled. Thanks to the rapid growth of computer and

communication technology, power substations are becoming more automated and

increasingly deploy intelligent devices to monitor and control unmanned facilities. The

company mentioned that the key factors to establishing successful substation automation

systems include faster and more reliable networking solutions such as embedded

computers.

There are three physical layers in substation automation: the bay layer, the

communication layer, and the substation layer. The bay layer consists of protection units

and control units, and is based on the RS-485 bus. The communication layer serves as the

core of the whole remote monitoring system. It not only collects data from the protection

units and sends it to the back-end control center, but transmits commands from the


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control center to the control units, such as switching on and off the various system

devices, capacitors, and converter transformer taps. The substation layer provides

100Mbps. Compared to the traditional IPC (industrial PC), the embedded computer is a

revolutionary technology that considerably changes the structure of control systems. By

replacing the PCs hard drive with flash or DOM (disk on module) memory, the RISC-

based structure of embedded computers provides users with fanless operation and low

power consumption. Structurally speaking, embedded technology reduces many unstable

factors associated with traditional IPCs that usually require add-on boards or cards for

system expansion. Add-on expansion boards/cards seldom meet strict anti-vibration and

anti-shock demands of harsh industrial conditions. To solve this problem, embedded

systems use a highly integrated layout design for all interfaces including serial ports,

Ethernet ports, and DI/DO. This significantly enhances system reliability and operation

stability. Moreover, embedded computers usually come pre-installed with either Linux or

Windows operating systems for a ready-to-run platform that satisfies real-time industrial

application demands, and ensures system maintenance costs and effort. [17]

In 2010 Cisco a network company reported on substation automation for smart grid.

The smart grid promises a more efficient way of supplying and consuming energy. In

essence, the smart grid is a data communications network integrated with the power grid

that enables power grid operators to collect and analyze data about power generation,

transmission, distribution, and consumptionall in near real time. Smart grid

communication technology provides predictive information and recommendations to

utilities, their suppliers, and their customers on how best to manage power. To achieve


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this vision of ubiquitous nearreal time information, a transformation of the power grid

communications infrastructure is needed, particularly in transmission and distribution

substations. While modern data communication has evolved from telephony modems to

IP networks, many power utilities are still deploying modem access and serial bus

technology to communicate with their substations. The existing supervisory control and

data acquisition (SCADA) remote terminal unit (RTU) systems located inside the

substation cannot scale and evolve to support next generation intelligence. Since flexible

IEC 61850compliant intelligent electronic devices (IEDs) and utility-grade rugged IP

routers and Ethernet switches have become more widely available, many utilities are now

ready to transform their communications networks from serial to IP-based

communications. [18]. Figure 1 shows the transition from a legacy substation to a next

generation substation.


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Figure 2.1 Substation Migrations in Process [18]

The migration toward this future transmission and distribution substation is taking place

because of the desire to bring more automation and intelligence to the power grid

network to address a myriad of utility concerns such as how to reduce operational

expenses to ways to meet new regulatory requirements. This paper describes Ciscos

vision and activities in the area of substation automation to help ensure a secure smart

grid and a reliable, sustainable energy supply. The transition from a legacy to future

substation is taking place because of various substation automation factors: The future

substation reduces operational expenses by converging multiple controls and monitoring

systems onto a single IP network while helping ensure higher priority for grid operational

and management traffic. This network convergence enables utility companies to reduce

power outages and service interruptions as well as decrease response times by quickly

identifying, isolating, diagnosing, and repairing faults. These improvements are achieved


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through automation and flexible access to operational control systems and, in the future,

through better data correlation across multiple monitoring systems.

In addition, many utilities are facing an aging workforce, which will be retiring in the

next 5 to 10 years. Utilities need to fill their pipeline of talent with a younger workforce

that is capable of operating todays electric grid, but who can also help build the smart

grid of the future. Utilities can benefit from substation automation by more efficiently

using their existing workforce and reducing the amount of service calls through programs

such as condition-based maintenance. Further, substation automation allows utilities to

extract further value from their corporate networks by providing a remote workforce

secure access to applications and data that are located in the operations center.

As demand for energy continues to grow, utilities must find ways to generate power to

meet peak loads. As a regulated industry, utilities must provide power regardless of the

amount of power consumed. The cost of providing spinning reserves for peak load hours

of the year is extremely high for society. Utilities are challenged to find new ways to

shave peak load to help reduce costs and manage supply and demand of energy more

efficiently. Substation automation can be the enabling technology for mass-scale peak

load shaving and demand response, which will reduce the need to build as many power

plants to meet peak demand.

Additionally, substation automation can reduce the expense and complexity of dedicated

control wiring between devices found in many transmission and distribution substations

today by converging to an Ethernet based network. Logical network segmentation and

reconfiguration of IED connectivity are much SIMpler to achieve. Point-to-point wiring

not only is expensive, but also increases the difficulty of fault isolation detection.


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As network intelligence expands beyond the control center out into the substations, new

applications can be developed that enable distributed protection, control, and automation

functions. A distributed intelligent network also introduces opportunities for new service

creation, such as business and home energy management. [18]

DT Brown and AL Gelink reported on utility experience in the implementation of

Substation Automation Project. Their system uses low technology solution for substation

automation. Their systems were heavily dependent on on-site hard wires secondary

cabling with associated advantages. The reduction in secondary cabling and the

rationalization for functionality in relays made possible by substation automation has

enabled significant cost saving to be achieved. [19]

Isaac Osei and Julius Anani Akpalu designed and constructed automobile anti hijack

system (A remote control unit to prevent car theft and other intruders from entering the

car when you are far away. It is a wireless communication system and uses transistors

for switching. [20]

David Dolezilk; Worked on case study of large transmission and distribution substation

automation project. In his findings, he said, The challenge is after choosing the most

beneficial and cost effective substation design. He concluded that motor motivators of

qualifying reliability issues include deriving the best solution on how to improve the

system, how to manage dependability versus security tradeoffs, as well as how to get the

best results for the least money when selecting a design. A quantitative understanding is

essential in a competitive utility industry. Reliability can be further quantified by

comparing unavailability. [21]


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In 2001, Tom Wilson reported on multi-vendor local and remote substation SCADA

system. The system logs production data for display on a trend screen or for transfer to

a separate software package for analysis and display. The SCADA system maintains

alarm and activity log data for sixty days. Operators can view any of these files from the

SCADA terminals. The Substation supplier had to balance certain device and SCADA

features in design, specifically the power meters were primarily selected for their

metering functionality, while relays were selected for their protection characteristics.

Integrating the meters and relays with the SCADA systems was important but secondary.

These devices were purchased from two different vendors who use different protocols for

open communications. Therefore, the SCADA master needed to properly handle

intelligent electronic device (IED) to server to distributed OIT communications. The

SCADA system does not any automatic control. Therefore, the SCADA master

functionality relates to handling communications, logging data, logging alarms, operator

displays and manual operator control. This functionality lends itself to PC based SCADA

master specification in the design. The (OIT) software will run under either the

workstation or server version of Microsoft windows on remote location. Although man

software packages provide local operator interface features, very few integrate support

for remote monitoring and control. One diagnostic feature is the protective relays ability

to store characteristic data at the time of a fault. The event data can be viewed on a PC

report by a protective relays. The one-line diagrams on the SCADA system give the

operator an overview of how the power is being used. These screens are divided between

the main transformer screen and a screen for each bus. Where data is available from

multiple sources, the meter data is normally used. If the SCADA master defects a meter


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communication failure, the display automatically switches to relay data. One important

SCADA function is recording the operator activity and system alarms for future review.

This system is configured to record operator activity such as SCADA system security,

manual breaker trip and close and tag-out status for a breaker or switch. The log also

records the name of the operator who took the action. [22]


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CHAPTER THREE

3.0 METHODOLOGY

This chapter looks at the various methods that are used to achieve the objectives of a gsm

based controlled system for a power sub-station.

3.1 Materials

3.1.1 Microcontroller

The microcontroller used was AT89C51 and was obtained from Interlogicx Embedded

Systems, in India. Some of the properties of the microcontroller are listed in table 3.1.

Table 3.1: Some Properties of Microcontroller

Property Value

Nature Tin (1.0mm) plotic Gull wing Quad flat package

Shape Rectangular

Pin 4

Supply voltage 4.0-5.5volts

RAM 256Bytes

ROM 4KB

Timer Available 2

Serial Port 1

Code memory 64K bytes

Flash memory 4Kbytes


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Current 25Ma

Timer/counter Two stand 16 bits

Table 3.1: Properties of microcontroller AT89C51

The Max 232IC was also obtained form interlogicx and embedded systems in India. A

few properties of the max 232 IC are listed in table 3.2 below.

Table 3.1.2: Some Properties of Max 232IC

Property Value

Operating voltage 5V

Nature Rectangular

Level 120bits

Driver 2

Receivers 2

Frequency 50Hz

Pins 16

Rs 232 cable which was obtain from Still searching electronic enterprise, Takoradi. A

few of the properties of the Rs 232 is listed in the table 3.3.

Table 3.1.3: Some Properties of RS232 Cable

Baud Rate Max cable length (ft)

19200 50

9600 500


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4800 1000

2400 3000

The GPRS or GSM was also obtained from interlogicx embedded system in India. A few

of the GPRS properties is listed in table 3.4 below.

Table 3.1.4: Some Properties of GPRS or GSM Modem

Property Value

Frequency 1900MHs

Slot class 10/8

Temperature -20co

to 55oc

D.C voltage 12V

D.C current 1A

Band per seconds 9600

Interface Rs-232 through D-Type 9 pin connector

Properties of General Pocket Radios Service (GPRS)

3.2 Designing

3.2.1 Designing of the Circuit

The circuit was designed using electronic workbench software. This software was used

to design a sample for the power supply which was incorporated on the receiver system.

The receiver sections were designed by this computer aid. In designing the power

supply, the software has menus that contains the various components of the circuit. One


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has to identify which menu contains the component for the power supplies were selected.

The components that were selected are: diodes (1n4001) capacitor (220F and 10F) and

regulator 7805. A step down transformer of 240/12V AC was also selected was also

selected. These components were laid out and their pins were joined appropriately with

lines. These lines are similar to the conductors on the printed circuit board (PCB). The

same procedure was followed in the design of the receiver circuit. The resulting circuit

diagrams is shown is in fig below.

240 V AC

FIGURE 3.1 240 V AC TO 12 V AC

+220F 12V

7805IN OUT

180

120

22010F

+

+

_

GND


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Fig 3.2 Circuit diagram of the receiver


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3.3 Construction

3.31 Construction of the Receiver

The receiver was constructed on printed circuit board (PCB) of 30mm x 14mm x 1.5mm

dimensions. The PCB was etched in accordance with the receiver circuit shown below

with various integrated circuit (IC) pin hole drilled. The microcontroller chip 89C51,

max 232 Ic, ULN2803AG (Ic),circuit breakers and the relays were all inserted on the

board to form a complete receiver unit. A picture of the receiver is shown below.

Fig 3.3: A snap shot of the receiver

RECEIVER SECTION


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Nokia 1280 was used to transmit Short Message Service (SMS) from a location to the

receiver. The SMS message could be sent to the receiver wherever there is a network

connectivity.

Fig 3.4: Picture of the transmitter


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CHAPTER FOUR

4.0 SYSTEM DESIGN, DEVELOPMENT AND IMPLEMENTATION

4.1 System Design

The designed circuit diagram for the receiver section is as shown below.

Fig 4.1: Circuit diagram of the receiver


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4.2 System Operation

The cell phone is used to send on SMS message to the GSM modem which is connected

to the PC. The GSM modem reads the data and process it through the software installed

on the PC. The output passes through RS232 cable which is also connected to the PC.

The RS 232 cable is connected to microcontroller AT 89C51 through an interface MAX

232 Ic. The microcontroller AT89C51 verify the data send with reference specification

and send control action to switch ON/OFF the circuit breaker. This circuit uses regulated

5V, 750 mA power supplies.

The 7805 three terminal voltage regulator is used for voltage regulation. Full wave

bridge rectifier is used to rectify the ac output of secondary 240/12 V step down

transformer.

4.3 Cross Compilers

Here is a brief introduction about cross compilers in embedded programming and their

applications. It is know that the execution of code in a microcontroller takes place as a

hexadecimal code. So we can program any microcontroller using an assembly language.

Also though the use of cross compilers we can program the microcontrollers in any

language like C or C++.

The cross compilers acts as a bridge between the programming software and

microcontrollers. Suppose we are programming the microcontroller using C the code

written in C language cannot be directly executed by microcontroller. So this code

written in C is fed to a cross compiler which converts into hexadecimal code which is

understood and executed by microcontroller. The advantages of using cross compilers is


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that in case of some applications programming the microcontroller using assembly

language will become bulk and tedious. So when we use cross compilers we can program

the microcontroller in any other language which is easy to program and debug also. The

commonly used cross compilers are SDCC (Small devices C compiler), Keil etc.

In this steady, the use of Keil cross compiler is to program the microcontroller. The

discussion on the introduction to programming in Keil features of Keil and finally

advantages of using Keil when compared to other cross compilers will be looked . When

we are writing program for any microcontroller using cross compiler we cannot directly

write the converted code on to the microcontroller. This means we need to use a special

technique to load the program into the microcontroller. One of the methods is to use a

microcontroller with a flash memory. Flash memory is similar to erasable programmable

read only memory. So once program is written and debugged using cross compiler, we

need to flash the program on to the flash memory of the memory. Once program is

flashed the microcontroller is loaded with the hex code and it will be ready for execution.

4.3.1 Introduction to Keil

Keil software provides the premier 8051 development tools to industry .The Keil

software comprises of different tool kits. A tool kit consist of several application program

that we can use to create our 8051 application .When the Keil software is used for the

study, the development cycle is somewhat similar to a software development project .It

consist of creating source file in C or assembly language compiling or assembling the

source files debugging error in the source file, linking file from complier and assembler

and finally building a project linking all the files and testing the linked application.


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4.3.2 Functioning of Keil

All the files are created through the micro vision integrated development environment are

then passed to the C51 compiler or A51 assembler. The compiler and assembler process

source files and create relocatable object files. Object files created by the compiler or

assembler may be used by the library manager to create a library. A library is a specially

formatted, ordered program collection of object modules that linker can process. When

the linker processes a library, only the object modules in the library necessary for

program creation are used. Object files created by the compiler and assembler and library

files created by the library manager are processed by the linker to create an absolute

object module. An absolute object file or module is an object file with no relocatable

code. All the code in an absolute object file resides at fixed locations.

The absolute object file created by the linker may be used to program EPROM or other

memory devices. The absolute object module may also be used with the dScope-51

debugger / simulator or with an in-circuit emulator. The dScope-51 source level

debugger/simulator is ideally suited for fast, reliable high-level-language program

debugging. The debugger contains a high-speed simulator and a target debugger that let

you simulate an entire 8051 system including on-chip peripherals. By loading specific

I/O drivers, we can simulate the attributes and peripherals of a variety of 8051 family.

The RTX-51 real time operating system is a multitasking kernel for the 8051 family. The

RTX-51 real time kernel simplifies the system design, programming, and debugging of

complex applications where reaction to time critical events fast is essential. The kernel is

fully integrated into the C51compiler and is easy to use. Task description tables and


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operating system consistency are automatically controlled by the BL51 code banking

linker/locater.

4.3.3 Development Tools in Keil

The tools listed below comprise the professional developers kit. In addition to the

professional kit, Keil Software provides a number of other tool kits for the 8051

developer. The most capable kit is the professional developers kit is described as

follows:

The professional developers kit includes everything the professional 8051 developer

needs to create sophisticated embedded applications. This tool kit includes the following

components:

C51 Optimizing C compiler,

A51 Macro Assembler,

BL51 Code Banking Linker/Locator,

OC51 Banked Object file converter,

OH51 Object-Hex converter,

LIB51 Library Manager,

dScope-1 SIMulator/debugger,

tScope-51 Target Debugger,

Monitor-51 ROM Monitor and Terminal Program,

Integrated Development Environment,

RTX-51 Tiny Real-Time Operating System.


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In addition, the professional developers kit includes the following tools for Windows

users:

dScope-51 simulator/Debugger for windows,

Micro Vision/51 Integrated Development Environment for windows.

The professional developers kit can be configured for all 8051 derivatives. The tools

included in this kit can run any compatible computer.

4.3.4 C51 Optimizing C Cross Compiler

The C programming language is a general-purpose programming language that provides

code efficiency, elements of structured programming, and a rich set of operators. Its

generality, combined with its absence of restrictions, make C a convenient and effective

programming solution for a wide variety of software tasks. Many applications can be

solved more easily and effectively with C than with other more specialized languages.

The Keil software C51 optimizing cross compiler for the MS-DOS operating system is a

complete implementation of the ANSI (American National Standards Institute) standard

for the C language. The C51 compiler generates code for the 8051 microprocessor but is

not a universal C compiler adapted for the 8051 target. It is a ground-up implementation

dedicated to generating extremely fast and compact code for the 8051 microprocessor.

For most 8051 applications, the C51 compiler gives software developers the flexibility of

programming in /c while matching the code efficiency and speed of assembly language.

Using a high-level language like C has many advantages over assembly language

programming. For example:


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Knowledge of the processor instruction set is not required. A rudimentary

knowledge of the 8051s memory architecture is desirable but not necessary.

Register allocation and addressing mode details are managed by the compiler.

The ability to combine variable selection with specific operations improves

program readability.

Keywords and operational functions that more nearly resemble the human thought

process can be used.

Program development and debugging times are dramatically reduced when

compared to assembly language programming.

The library files that are supplied provide many standard routines (such as

formatted output, data conversions, and floating-point arithmetic) that may be

incorporated into our application.

Existing routine can be reused in new programs by utilizing modular

programming techniques available with C.

The C language is very portable and very popular. C compilers are available for

almost all target systems. Existing software investments can be quickly and easily

converted from or adapted to other processors or environments.

4.3.5 A51 Micro Assembler

The A51 assembler is a macro assembler for the 8051 microcontroller family. It translates

symbolic assembly language mnemonics into relocatable object code where the utmost

speed, small code size, and hardware control are critical. The macro facility speeds

development and conserves maintenance time since common sequences need only be

developed once. The A51 assembler supports symbolic access to all features of the 8051


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architecture and is configurable for the numerous 8051 derivatives. The A51 assembler

translates an assembler source file into a relocatable object module. If the DEBUG

control is used, the object file contains full symbolic information for debugging with

dScope or an in-circuit emulator. In addition to the object file, the A51 assembler

generates a list file which may optionally include symbol table and cross reference

information. The A51 assembler is fully compatible with Intel ASM-51 source modules.

The A51 assembler supports all members of the 8051 family. The special function

register (SFR) set of the 8051 is predefined. However, the NOMOD51 control lets you

override these definitions with processor-specific include files.

The A51 assembler is shipped with include files for the 8051, 8051fx, 8051GB, 8052,

80152, 80451, 80452, 80515, 80C517, 80C517A, 8x552, 8xC592, 8xCL782, 8xCL410

and 80C320 microcontrollers. You can easily create include files for other 8051 family

members.

4.3.6 BL51 Code Banking Linker/Locator

The 51 code banking linker/locator combines one or more object modules into a single

executable 8051 program. The linker also resolves external and public references, and

assigns absolute addresses to relocatable programs segments. The BL51 code banking

linker/locator processes object modules created by the keil C51 compiler and A51

assembler and the Intel PL/M-51 compiler and ASM-51 assembler. The linker

automatically selects the appropriate run-time library and links only the library modules

that are required. Normally, you invoke the BL51 code banking linker/locator from the

command line specifying the names of the object modules to combine. The default


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controls for the BL51 code banking linker/locator have been carefully chosen to

accommodate most applications without the need to specify additional directives.

However, it is easy for us to specify custom settings for your applications.

4.3.7 OC51 Banked Object File Converter

The OC51 banked object file converter creates absolute object modules for each code

bank in a banked object module. Banked object modules are created by the BL51 code

banking linker/locator when you create a bank switching application. Symbolic

debugging information is copied to the absolute object files and can be used by dScope or

an in-circuit emulator. We may use the OC51 banked object file converter to create

absolute object modules for the command area and for each code bank in your banked

object module. You may then generate Intel HEX files for each of the absolute object

modules using the OH51 object-hex converter.

4.3.8 OH51 Object-HEX Conveter

The OH51 object-hex converter creates Intel hex files from absolute object modules.

Absolute object modules can be created by the BL51 code baking linker or by the OC51

banked object file converter. Intel hex files are ASCII files that contain a hexadecimal

representation of your application. They can be easily loaded into a device programmer

for writing on Erasable programmable read only memory.

4:3.9 LIB51 Library Manager

The LIB51 library manager lets you create and maintain library files. A library file is a

formatted collection of one or more object files. Library files provide a convenient


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method of combining and referencing a large number of object files. Libraries can be

effectively used by the BL51 code banking linker/locator. The LIB51 library manager

lets you create a library file, add object modules to a library file, remove object modules

from may be controlled interactively or from the command line.

4.3.10 Dscope-51 for Windows

DScope-51 is a source level debugger and simulator for programs created with the keil

C51 compiler and A51 assembler and the Intel PL/M-51 compiler and ASM-51

assembler. DScope-51 is a software-only product that lets us simulate the features of an

8051 without actually having target hardware. We may have used Scope-51 to test and

debug our embedded applications before actual 8051 hardware is ready. DScope-51

simulates a wide variety of 8051 peripherals including the internal serial port, external

I/O, and timers.

4.3.11 vision/51 for Windows

Microvision/51 is an integrated software development platform that includes a full

function editor, project manager, make facility, and environment control for the keil 8051

tools. When we use Vision/51 speeds our embedded applications development by

providing the following:

Standard Windows user interface,

Dialog boxes for all environment and development tool settings,

Multiple file editing capability,

Full function editor with user-definable key sequences,


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Application manager for adding external programs into the pull-down

menu,

Project manager for creating and maintaining projects,

Integrated make facility for building target programs from your projects,

On-line help system.

4.4 System Development

4.4 Description to Embedded Controllers


computers that are often embedded into systems to function as processing /controllers unit. For

example, the remote control you are using probably has microcontrollers inside that do

decoding and other controlling functions. They are also used in automobiles, washing

machines, microwave ovens, toysetc, where automation is needed. The key features of

microcontrollers include:

High integration ofFunctionality

Microcontrollers sometimes are called single chip computers because they have on-chip

memory and I/O circuitry and other circuitries that enable them to function as small standalone

computers without other supporting circuitry.

Field Programmability, Flexibility

Microcontrollers often use EEPROM or EPROM as their storage device to

allow field programmability so they are flexible to use. Once the program


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tested to be correct then large quantities of microcontrollers can be programmed

to be used in embedded systems.

Easy to Use

Assembly language is often used in microcontroller and since they usually follow RISC

architecture, the instruction set is small. The development package of microcontrollers

often includes an assembler ,a simulator ,a programmer to burn the chip and a

demonstration board .Some packages include a high level language compiler such as a

C compiler and more sophisticated libraries.

4.5 Microcontroller AT89C51

4.5.1 Introduction to AT89C51

The Intel 8051contains two separate buses for the program and data. It is based on an 8

bit central processing unit with an 8 bit accumulator and another 8 bit register as main

processing blocks.AT89C51 is supported with on-chip peripheral functions like I/O ports,

Timers/Counters, serial communication port.

The key features of AT89C51 are

4K Bytes of In-System Reprogrammable Flash Memory

Endurance: 1,000 Write/Erase Cycles

Fully Static Operation: 0 Hz to 24 MHz

Three-level Program Memory Lock

128 x 8-bit Internal RAM

32 Programmable I/O Lines


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Two 16-bit Timer/Counters

Six Interrupt Sources

Programmable Serial Channel

Low-power Idle and Power-down Modes

4.5.2 Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K

bytes of Flash programmable and erasable read only memory (PEROM). The device is

manufactured using Atmels high-density nonvolatile memory technology and is

compatible with the industry-standard MCS-51 instruction set and pin out. The on-chip

Flash allows the program memory to be reprogrammed in-system or by a conventional

nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a

monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a

highly-flexible and cost-effective solution to many embedded control applications.

The AT89C51 provides the following standard features:

4K bytes of flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five

vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and

clock circuitry. In addition, the AT89C51 is designed with static logic for operation down

to zero frequency and supports two software selectable power saving modes. The Idle

Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt

system to continue functioning. The Power-down Mode saves the RAM contents but

freezes the oscillator disabling all other chip functions until the next hardware reset.


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Fig 4.2: System Block Diagram


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4.6 Architecture of AT89C51

The Accumulator

The Accumulator is used as a general register to accumulate the results of a large number

of instructions. It can hold an 8-bit (1-byte) value and is the most versatile register the

8051 has due to the sheer number of instructions that make use of the accumulator.

Accumulator performs arithmetic and logic functions. Accumulator is also responsible

for conditional branching and provides a temporary place in a data transfer operations

within the device. More than half of the 8051s 255 instructions manipulate or use the

accumulator in some way.

The "R" registers

The "R" registers are a set of eight registers that are named R0, R1, up to and including

R7.

These registers are used as auxiliary registers in many operations.

The Accumulator alone would not be very useful if it were not for these "R" registers.

The "R" registers are also used to temporarily store values.

The "B" Register

The "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit

(1-byte) value.

The "B" register is only used by two 8051 instructions: MUL AB and DIV AB. It enables

quick and easier way of multiplying or dividing a number by another number, and stores

the other number in "B" and makes use of these two instructions.


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Aside from the MUL and DIV an instruction, the B register is often used as yet another

temporary storage register much like a ninth "R" register.

The Data Pointer (DPTR)

The Data Pointer (DPTR) is the 8051s only user-accessible 16-bit (2-byte) register.

DPTR is used to point to data. It is used by a number of commands which allow the 8051

to access external memory. When the 8051 accesses external memory it will access

external memory at the address indicated by DPTR.

While DPTR is most often used to point to data in external memory, many programmers

often take advantage of the fact that its the only true 16-bit register available. It is often

used to store 2-byte values which have nothing to do with memory locations.

The Program Counter (PC)

The Program Counter (PC) is a 2-byte address which tells the 8051 where the next

instruction to execute is found in memory. When the 8051 is initialized PC always starts

at 0000h and is incremented each time an instruction is executed. It is important to note

that PC isnt always incremented by one. Since some instructions require 2 or 3 bytes the

PC will be incremented by 2 or 3 in these cases. The Program Counter is special in that

there is no way to directly modify its value.

The Stack Pointer (SP)

The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte)

value. The Stack Pointer is used to indicate where the next value to be removed from the

stack should be taken from.


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When you push a value onto the stack, the 8051 first increments the value of SP and then

stores the value at the resulting memory location.

When you pop a value off the stack, the 8051 returns the value from the memory location

indicated by SP, and then decrements the value of SP.

When the 8051 is initialized SP will be initialized to 07h. If you immediately push a

value onto the stack, the value will be stored in Internal RAM address 08h. This makes

sense taking into account what was mentioned two paragraphs above: First the 8051 will

increment the value of SP (from 07h to 08h) and then will store the pushed value at that

memory address (08h).

SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL,

RET, and RETI.

PSW Program Status Word

PSW, the Program Status Word is at address D0h and is a bit-addressable register. The

status bits are listed in table 4.1

Table.4.1 Program Status Word

Symbol Bit Address Description

C (or CY) PSW.7 D7h Carry flag

AC PSW.6 D6h Auxiliary carry flag

F0 PSW.5 D5h Flag 0


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RS1 PSW.4 D4h Register bank select 1

RS0 PSW.3 D3h Register bank select 0

0V PSW.2 D2h Overflow flag

PSW.1 D1h Reserved

P PSW.0 D0h Even Parity flag

Carry flag(C)

This is a conventional carry, or borrows, flag used in arithmetic operations. The carry

flag is also used as the Boolean accumulator for Boolean instruction operating at the bit

level. This flag is sometimes referenced as the CY flag.

Auxiliary carry flag (AC)

This is a conventional auxiliary carry (half carry) for use in BCD arithmetic.

Flag 0(F0)

This is a general-purpose flag for user programming.

Register bank select 0 and register bank select 1. RS0 and RS1

These bits define the active register bank (bank 0 is the default register bank).

Overflow flag. OV

This is a conventional overflow bit for signed arithmetic to determine if the result of a

signed arithmetic operation is out of range.

Even Parity flag (P)

The parity flag is the accumulator parity flag, set to a value, 1 or 0, such that the number

of 1 bits in the accumulator plus the parity bit add up to an even number.


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SFR Registers for the Internal Timer

TCON, the Timer Control register is an SFR at address 88h, which is bit-addressable.

TCON is used to configure and monitor the 8051 timers. TMOD, the Timer Mode

register is an SFR at address 89h and is used to define the operational modes for the

timers. TL0 (Timer 0 Low) and TH0 (Timer 0 High) are two SFR registers addressed at

8Ah and 8Bh respectively. The two registers are associated with Timer 0.

TL1 (Timer 1 Low) and TH1 (Timer 1 High) are two SFR registers addressed at 8Ch and

8Dh respectively. These two registers are associated with Timer 1.

Power Control Register

PCON (Power Control) register is an SFR at address 87h. It contains various control bits

including a control bit, which allows the 8051 to go to sleep so as to save power when

not in immediate use.

Serial Port Registers

The SCON (Serial Control) is an SFR register located at addresses 98h, and it is bit-

addressable. SCON configures the behavior of the on-chip serial port, setting up

parameters such as the baud rate of the serial port, activating send and/or receive data,

and setting up some specific control flags.

The SBUF (Serial Buffer) is an SFR register located at address 99h. SBUF is just a single

byte deep buffer used for sending and receiving data via the on-chip serial port.


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Interrupt Registers

IE (Interrupt Enable) is an SFR register at addresses A8h and is used to enable and

disable specific interrupts. The MSB bit (bit 7) is used to disable all interrupts.

IP (Interrupt Priority) is an SFR register at addresses B8h and it is bit addressable. The IP

register specifies the relative priority (high or low priority) of each interrupt. On the

8051, an interrupt may either be of low (0) priority or high (1) priority.

4.6.1 Pin Description

Figure.4.3 Pin Description


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VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink

eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high

impedance inputs.

Port 0 may also be configured to be the multiplexed low order address/data bus during

accesses to external program and data memory.

In this mode P0 has internal Pull-ups. Port 0 also receives the code bytes during Flash

programming, and outputs the code bytes during program verification. External pullups

are required during program verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers

can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high

by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally

being pulled low will source current (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes during Flash programming and

verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers



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being pulled low will source Current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory

and during accesses to external data memory that uses 16-bit addresses (MOVX @

DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During

accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits

the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash

programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers



being pulled low will source current (IIL) because of the pullups. Port 3 also serves the

functions of various special features of the AT89C51 as listed below:


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Table.4.1 Port 3 Functions

Port 3 also receives some control signals for Flash programming and verification.

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running

resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during

accesses to external memory. This pin is also the program pulse input (PROG) during

Flash programming.

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and

may be used for external timing or clocking purposes. Note, however, that one ALE pulse

is skipped during each access to external Data Memory.


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If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the

bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in

external execution mode.

PSEN

Program Store Enable is the read strobe to external program Memory. When the

AT89C51 is executing code from external program memory, PSEN is activated twice

each machine cycle, except that two PSEN activations are skipped during each access to

external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to

fetch code from external program memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program Executions. This pin also receives

the 12-volt programming enable voltage (VPP) during Flash programming, for parts that

require 12-volt VPP.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier is XTAL2 pin.


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4.6.1 Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier

which can be configured for use as an on-chip oscillator, as shown in Figure 4.4. Either a

quartz crystal or ceramic resonator may be used. To drive the device from an external

clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in

Figure 4.5. There are no requirements on the duty cycle of the external clock signal, since

the input to the internal clocking circuitry is through a divide-by-two flip-flop, but

minimum and maximum voltage high and low time specifications must be observed.

Figure 4.4 Osciliator Connections


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Figure.4.5 Oscillator Characteristics

4.6.2 Idle Mode

In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active.

The mode is invoked by software. The content of the on-chip RAM and all the special

functions registers remain unchanged during this mode. The idle mode can be terminated

by any enabled interrupt or by a hardware reset. It should be noted that when idle is

terminated by a hard ware reset, the device normally resumes program execution, from

where it left off, up to two machine cycles before the internal reset algorithm takes

control. On-chip hardware inhibits access to internal RAM in this event, but access to the

port pins is not inhibited.

To eliminate the possibility of an unexpected write to a port pin when Idle is terminated

by reset, the instruction following the one that invokes Idle should not be one that writes

to a port pin or to external memory.


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4.6.3 Power down Mode

In the power-down mode, the oscillator is stopped, and the instruction that invokes

power-down is the last instruction executed. The on-chip RAM and Special Function

Registers retain their values until the power-down mode is terminated. The only exit from

power-down is a hardware reset. Reset redefines the SFRs but does not change the on -

chip RAM. The reset should not be activated before VCC is restored to its normal

operating level and must be held active long enough to allow the oscillator to restart and

stabilize

4.6.4 AT89C51 Reset

Figure.4.6.Reset


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RESET is an active high input.

When RESET is set to high, AT89C51 goes to the power on state.

Power-On Reset.

Push PB and active high on RST.

Release PB, Capacitor discharges and RST goes low.

RST must stay high for a min of 2 machine cycles

4.7Timer/CountersThe 8051 has two internal sixteen bit hardware Timer/Counters. Each Timer/Counter can

be configured in various modes, typically based on 8-bit or 16-bit operation. The 8051

product has an additional (third) Timer/Counter

4.7.1 8-Bit Counter Operation

First let us consider a simple 8-bit counter. Since this is a modulo-8 set up we are

concerned with 256 numbers in the range 0 to 255 (28

=256). The counter will count in a

continuous sequence as follows:

Hex Binary Decimal

00h 00000000 0

01h 00000001 1

02h 00000010 2

. . .


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FEh 11111110 254

FFh 11111111 255

00h 00000000 0 here the counter overflows to zero1

01h 00000001 1

Figure.4.7. Timer/Counter 1

Supposing we were to initialize this Timer/Counter with a number, say 252, then the

counter would overflow after just four event pulses, i.e.:

FCh 11111100 252 counter is initialised at 252

FDh 11111101 253

FEh 11111110 254

FFh 11111111 255

00h 00000000 0 here the counteroverflows

An 8-bit counter can count 255 events before overflow, and overflows on the 256th

event.

When initialized with a predefined value of say 252 it overflows after counting just four

Timer/Counter 8-bit

Event

TF1

Overflows after

255 events, i.e.TL1


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events. Thus the number of events to be counted can be programmed by pre-loading the

counter with a given number value.

4.7.2 8-bit Timer Operation

The 8051 internally divides the processor clock by 12. If a 12 MHz. processor clock is

used then a 1 MHz instruction rate clock, or a pulse once every microsecond, is realized

internally within the chip. If this 1 microsecond pulse is connected to a Timer/Counter

input, in place of an event input, then the Timer/Counter becomes a timer which can

delay by up to 255 microseconds. There is a clear difference between a timer and a

counter. The counter will count events, up to 255 events before overflow, and the timer

will count time pulses, thus creating delays up to 255 microseconds..

Figure. 4.8.Reset

If the timer is initialized to zero it will count 256 microseconds before overflow. If the

timer is initialized to a value of 252, for example, it will count just 4 microseconds before

overflow. Thus this timer is programmable between 1 microsecond and 256

microseconds.

Working Operation

Configure the Timer/Counter as a TIMER or as a COUNTER

Timer/Counter 8-bit

1 MHz. i.e. pulseTF1

Overflows at

256 micro sec.

12MH

z.

Clock

12 TL1


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Program the Timer/Counter with a value between 0 and 255

Enable and disable the Timer/Counter

How to know when the timer has overflowedinterrupt vs. polling.

TMOD register (Timer Mode Control): It is an SFR register at location 89h in internal

RAM and is used to define the Timer/Counter mode of operation.

TMOD register

Gate

msb

C/T M1 M0 Gate C/T M1 M0

lsb

------------- Timer 1 ------------|----------- Timer 0 ---------------

Consider Timer/Counter 1 only. The Gate bit will be ignored for now and will be set to 0

in the examples. The C/T bit is set to 1 for COUNTER operation and it is set to 0 for

TIMER operation. MI and M2 bits define different modes, where mode 2 is the 8 bit

mode, i.e.:

M1 M0

0 0 mode 0: 13 bit mode (seldom used).

0 1 mode 1: 16-bit mode

1 0 mode 2: 8-bit mode (with auto reload feature)

1 1 mode 3: ignore for now


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To run in TIMER mode using 8-bit operation, the TMOD register is initialized as

follows:

MOV TMOD, #00100000b ; assume timer 0 is not considered

Program the Timer/Counter value

The 8-bit Timer/Counter is pre-programmed with a value in the range 0...255. This is

achieved by writing this value into the TH1 register for the Timer/Counter. TH1 is an

SFR register (located at 8Dh in Internal RAM). An example is as follows:

MOV TH1, #129d ; Timer/Counter 1 is programmed for 129 counts

Timer Overflow

TCON register (Timer Control) has some bits which represent Timer/Counter status flags

as well as some bits which can be set or cleared to control the Timer/Counter operation.

The relevant bits for Timer/Counter 1 are bolded in the diagram. TR1 is set to 1 to enable

Timer/Counter 1. Clearing TR1 turns the Timer/Counter off. TF1 is the Timer/Counter

overflow flag. When the Timer/Counter overflows TF1 goes to logic 1. Under interrupt

operation TF1 is automatically cleared by hardware when the processor vectors to the

associated ISR routine.

TCON register:

TF1

Msb

TR1 TF0 TR0 IE1 IT1 IE0 IT0

lsb


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Auto reloading of the 8-bit Timer/Counter

The TL1 SFR register (located at 8Bh in Internal RAM) represents the current value in

the 8-bit Timer/Counter. The Timer/Counter can be programmed by initializing this

register with a number between 0 and 255. However, there is an interesting automatic

reload feature in mode 2, where, when TL1 overflows (its value reaches 0), the

Timer/Counter is automatically reloaded with the 8-bit value stored in SFR register TH1.

4.7.3 The 16 Bit Timer/Counter

When the Timer/Counter is configured for mode 1 operation it operates in 16 bit mode.

Since this is a modulo-16 set up we are concerned with 65,536 numbers in the range 0 to

65,535 (216

= 65,536). Consider a 16 bit Timer/Counter as shown below, which will

count in the sequence as follows

Hex Binary Decimal

0000h 0000000000000000 0

0001h 0000000000000001 1

0010h 0000000000000010 2

. . .

FFFEh 1111111111111110 65,534

FFFFh 1111111111111111 65,535

00000h 0000000000000000 0 here it overflows to zero.


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Figure.4.9. 16 bit Timer Overflow

Now we have a 16-bit Timer/Counter and we can preload it with a sixteen bit number so

as to cause a delay from bewteen 1 to 65,535 microseconds (65.535 millisecs.), or in

counter mode it can count between 1 and 65,535 events. To preload the Timer/Counter

value SIMply write the most significant byte into the TH1 register and the least

significant byte into the TL1 register. The 16-bit counter is not automatically reloaded

following an overflow and such reloading must be explicitly programmed.

4.8 Interrupts

An interrupt causes a temporary diversion of program execution in a similar sense to a

program subroutine call, but an interrupt is triggered by some event, external to the

currently operating program. We say the interrupt event occurs asynchronously to the

currently operating program as it is not necessary to know in advance when the interrupt

event is going to occur.

There are five interrupt sources for the AT89C51. Since the main RESET input can also

be considered as an interrupt, six interrupts can be listed as follows:

Timer/Counter 16-bit

Event or time pulse

depending on

TL1TH1

TF1

Overflows after


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Interrupt Flag Vector address

System RESET RST 0000h

External interrupt 0 IE0 0003h

Timer/counter 0 TF0 000B

External interrupt 1 IE1 0013h

Timer/counter 1 TF1 001Bh

Serial port RI or TI 0023h

The Interrupt Enable, IE, register is an SFR register at location A8h in Internal RAM.

The EA bit will enable all interrupts (when set to 1) and the individual interrupts must

also be enabled.

4.8.1 Interrupt Enable Register

EA

Enable interrupt bits.

Set to 1 to permit individual interrupts to be enabled by their enable bits. Cleared to 0 by

program to disable all interrupts.

ES

Enable serial interrupt. Set to 1 to enable by program. Cleared to 0 to disable it.

EA

msb

ES ET1 EX1 ET0 EX0

lsb


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ET 1

Enable/disable the timer 1 overflow interrupt.

EX1

Enable external interrupt 1.Set to 1by program to enable external interrupt 1.

Cleared to 0 to disable it.

ET 0

Enable/disable the timer 1 overflow interrupt.

EX0

Enable external interrupt 1.Set to 1by program to enable external interrupt 1.

Cleared to 0 to disable it.

4.8.2 Sources of Interrupts

The external interrupt INT0, for example, we see that this external interrupt connects to

the processor at the P3.2 pin. Note Port 3 can be used as a standard input/output port as

shown earlier but various Port 3 pins have alternative functionality. When INT0 is

activated (negative edge usually), internally within the 8051 the EX0 request is raised.

This flags an interrupt request but the relevant interrupt bit within the IE register must be

set, along with the EA bit if this interrupt request is to raise an interrupt flag. The

interrupt flag IE0 is then raised and causes the program counter (PC) to vector to vector

location 0003h, as discussed earlier. The Timer/Counter interrupt flags can be software

polled even if the ETx bits are not enabled. Interrupts can also be software generated by

setting the interrupt flags in software. The interrupt flags are accessible as flags on the

TCON and SCON registers as follows:


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TCON register

TF1

msb

TF0 IE1 IT1 IE0 IT0

Lsb

SCON register

M0

msb

M1 M2 REN TB8 RB8 TI RI

Lsb

T1

INT1

External int. 1

T0

Timer/counter 0

INT External int. 0

Figure.4.10.Interrupt sources

Timer 1

UART

Timer 0

EA

ES

ET1

RI

or TI

TF1

0023h

001Bh

0013h

000Bh

0003h

P3.3

P3.5

P3.2

P3.4

Vector

Table

Interrupt

FLAGS

in TCON

Interrupt

Requests

Enables

Tx

Rx

P3.3


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4.8.3 Interrupt Priority Level Structure

An individual interrupt source can be assigned one of two priority levels. The Interrupt

Priority, IP, register is an SFR register used to program the priority level for each

interrupt source. A logic 1 specifies the high priority level while a logic 0 specifies the

low priority level.

IP REGISTER

x

msb

X PT2 PS PT1 PX1 PT1 PX0

lsb

IP.7 x reserved

IP.6 x reserved

IP.5 PT2 Timer/counter-2 interrupt priority (8052 only, not 8051)

IP.4 PS Serial ports interrupt priority

IP.3 PT1 Timer/Counter-1 interrupt priority

IP.2 PX1 External interrupt-1 priority

IP.1 PT0 Timer/Counter-0 interrupt priority

IP.0 PX0 External interrupt-0 priority


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An ISR routine for a high priority interrupt cannot be interrupted. An ISR routine for a

low priority interrupt can be interrupted by a high priority interrupt, but not by a low

priority interrupt.

If two interrupt requests, at different priority levels, arrive at the same time then the high

priority interrupt is serviced first. If two, or more, interrupt requests at the same priority

level arrive at the same time then the interrupt to be serviced is selected based on the

order shown below.

Note, this order is used only to resolve SIMultaneous requests. Once an interrupt service

begins it cannot be interrupted by another interrupt at the same priority level.

The interrupts and the its priorities are given as below,

Interrupt Priority within

IE0 highest

TF0

IE1

TF1

RI, TI

TF2 lowest


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4.9 Serial Communication

Serial communication is basically the transmission or reception of data one bit at a time.

Todays computers generally address data in bytes or some multiple thereof. A byte

contains 8 bits. A bit is basically either a logical 1 or zero. Every character on this page is

actually expressed internally as one byte. The serial port is used to convert each byte to a

stream of ones and zeroes as well as to convert a stream of ones and zeroes to bytes. The

serial port contains a electronic chip called a universal asynchronous receiver/transmitter

UART that actually does the conversion.

The serial port has many pins. Electrically speaking, whenever the serial port sends a

logical one a negative voltage is effected on the transmit pin. Whenever the serial port

sends a logical zero a positive voltage is affected. When no data is being sent, the serial

ports transmit pins voltage is negative and is said to be in a mark state. Note that the

serial port can also be forced to keep the transmit pin at a positive voltage and is said to

be the SPACE or BREAK state.

The terms MARK and SPACE are also used to SIMply denote a negative voltage 1 or a

positive voltage 0 at the transmit pin respectively.

Figure.4.11.Serial Communication.


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When transmitting a byte, the UART first sends a START BIT which is a positive

voltage 0, followed by the data generally 8 bits, but could be 5,6,7,8 bits, followed by one

or two STOP BITS which is a negative voltage. The sequence is repeated for each byte

sent. The figure explains what a byte transmission would look like. The duration of the

bit is dependent on the baud rate. The baud rate is the number of times the signal can

switch states 9600 times per second.

The first characteristic is the length of the byte that will be transmitted. This length in

general can be anywhere from 5 to 8 bits.

The second characteristic is parity. The parity characteristic can be even, odd, mark,

space, or none. If even parity, then the last data bit transmitted will be a logical 1 if the

data transmitted had an even amount of 0 bits. If odd parity, then the last data bit

transmitted will be a logical 1 if the transmitted had an odd amount of 0 bits. If MARK

parity, then the last transmitted data will always be a logical 0. If no parity then there is

no parity bit transmitted.

The third characteristic is the amount of stop bits. This value in general is 1 or 2.

If the letter A is sent then the binary representation of it is 000001.Remembering that

bits are transmitted from least significant bit to most significant bit, the bit stream

transmitted would be as follows for the line characteristics bits, 1 stop bit,9600 baud.

LSB 0100000101 MSB

The above represents Start bit Data bits Stop bits

4.9.1 The 8051 UARTThe 8051 includes a hardware UART to support serial asynchronous communications so

that, typically, the product can support RS-232 standard communication. The UART


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(Universal Asynchronous Receiver and Transmitter) block diagram is shown in figure

4.12 . In this examples, BAUD clocks are, in fact, a single clock source provided by

Timer/Counter 1.

8 data

SBUF

8

BAUD Clk.

e.g. 9600

TI

Stop bit

Start bit

Send

8-bitdata

Transmitter

Buf fer isempty

10 bit

parallelto serial

conversion

Serial data transmit

TRANSMITTER HALF

8 data bits

start

bit

stop

bit

8 data

SBUF

8

RI

Start bit

Stop bit

Receive

8-bitdata

Receiv edata is

av ailable

10 bit

serial toparallel

conversion

Serial data receive

RECEIVER HALF

8 data bits

stop

bit

start

bit

Tx

Rx

Figure.4.12.8051 UART


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SBUF is an SFR register which can be written to, so as to hold the next data byte to be

transmitted. Also it can be read from to get the latest data byte received by the serial port.

SBUF is thus effectively two registers: one for transmitting and one for receiving.

The SCON (Serial Control) register is an SFR register, used for configuring and

monitoring the serial port status.

SCON register

SM0

Msb

SM1 SM2 REN TB8 RB8 TI RI

Lsb

SM0, SM1 bits define the mode of operation, such as the number of data bits (8 or 9), the

clock source etc. Our examples will use mode 3, which specifies 9 data bits (8 data plus a

parity bit) with the clock source being Timer/Counter 1.

SM2 is set to 0 for normal operation

REN is set to 1 to enable reception, 0 to disable reception

TB8 is the ninth bit (parity bit) to be transmitted

RB8 is the ninth bit received (parity bit)

TI Transmit Interrupt flag. A logic 1 indicates that transmit buffer (SBUF) is empty. This

flag must be cleared by software.


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RI Receive Interrupt flag. A logic 1 indicates that data has been received in the receive

buffer (SBUF). This flag must be cleared by software.

4.9.2 SETTING THE BAUD RATE

Timer/Counter 1 (in SCON mode 3) provides the serial port baud rate clock. Usually the

8-bit auto reload operation (Timer/Counter mode 2) is used. The table shows some values

defined for the TH1 register to achieve some of the more common baud rates. The values

shown assume a processor clock rate of 11.059MHz. This is a common crystal value for

8051 based designs as it divides down to provide accurate baud rates.

Table.4.3. Setting the BAUD Rate

Baud rate Timer/Counter1

TH1 value

PCON.7

SMOD

8051clock

Frequency

300 A0h 0 11.059MHz.

1,200 D0h 0 11.059MHz.

2,400 FAh 0 11.059MHz.

9,600 FDh 0 11.059MHz.

4.10 Microcontroller Interfacing

4.11 GSM/GPRS Modem


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This GSM modem is a highly flexible plug and play quad band GSM modem for direct

and easy integration to RS232. Supports features like Voice, Data/Fax, SMS, GPRS and

integrated TCP/IP

The GPRS Modem

4.12 Relay

A relay is an electrically operated switch. Many relays use an electromagnet to operate a

switching mechanism mechanically, but other operating principles are also used. Relays

are used where it is necessary to control a circuit by a low-power signal (with complete

electrical isolation between control and controlled circuits), or where several circuits

must be controlled by one signal. The first relays were used in long distance telegraph

circuits, repeating the signal coming in from one circuit and re-transmitting it to another.

Relays were used extensively in telephone exchanges and early computers to perform

logical operations.


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A type of relay that can handle the high power required to directly drive an electric motor

is called a contactor. Solid-state relays control power circuits with no moving parts,

instead using a semiconductor device to perform switching. Relays with calibrated

operating characteristics and sometimes multiple operating coils are used to protect

electrical circuits from overload or faults; in modern electric power systems these

functions are performed by digital instruments still called "protective relays".

4.12.1 Basic Design and Operation

A SIMple electromagnetic relay consists of a coil of wire surrounding a soft iron core, an

iron yoke which provides a low reluctanc

Documents

Design and Construction of a GSM Based Controlled System for a Power Sub-Station