DESIGN AND ANALYSIS OF THREE-PHASE SYMMETRICAL … · DESIGN AND ANALYSIS OF THREE-PHASE SYMMETRICAL MULTILEVEL VOLTAGE SOURCE INVERTER USING FUZZY CONTROLLER RAJASEKHAR REDDY.DESAM1,

INTERNATIONAL JOURNAL OF PROFESSIONAL ENGINEERING STUDIES Volume 10 /Issue 1 / MAY 2018

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DESIGN AND ANALYSIS OF THREE-PHASE SYMMETRICAL

MULTILEVEL VOLTAGE SOURCE INVERTER USING FUZZY

CONTROLLER RAJASEKHAR REDDY.DESAM1, T. SUMAN PAUL REDDY2

1M.Tech student Department of Electrical and Electronics Engineering, Universal College Of Engg & Tech, Dokiparru, Medikonduru, Guntur-522438, Andhra Pradesh, INDIA

2Assistant Professor,Head of the Department of Electrical and Electronics Engineering,Universal College Of Engg & Tech, Dokiparru, Medikonduru, Guntur-522438, Andhra Pradesh, INDIA

[email protected], [email protected]

Abstract- Multi-level inverters have obtained great attention as a single stage inverter. Although, they need high number of components, but due to their advantages such as generating output voltage with extremely low distortion factor , low dv/dt, small output filter size, low electromagnetic interface , and low total harmonic distortion, still have great attention be extended , for extra number of output voltage levels ,it is a modular type and it can by adding additional modular stages. To maximize the number of voltage levels the impact of the proposed topology is its proficiency using a reduced number of isolated dc voltage sources and electronic switches. Here we are using the fuzzy controller compared to other controllers i.e. The fuzzy controller is the most suitable for the human decision-making mechanism. In addition, using the fuzzy controller for a nonlinear system allows for a reduction of uncertain effects in the system control and improve the efficiency. A new design and implementation of a three-phase multilevel inverter for distributed power generation system using low frequency modulation and sinusoidal pulse width modulation for various modulation is presented in this paper. To verify the control technique and performance of the topology by using simulation results .

INTRODUCTION Many multilevel converter topologies and

wide variety of control methods have been developed, due to their advantages such as generating output voltage with extremely low distortion factor , low dv/dt, small output filter size, low electromagnetic interface , and low total harmonic distortion , still have great attention. Multi-level inverters great attention as a single stage inverter. Practically, all of these advantages appear strongly as the number of dc-power sources increased as in the case of renewable energy systems Although this topology uses only one single dc-source, but it has many limitations due to capacitors, existence of three-phase transformer, and high voltage stress on

the H-bridge switches as the number of levels is increased.

To produce ac voltage waveforms with higher amplitude and near sinusoidal waveform general concept of is to utilize isolated dc sources or a bank of series capacitors. There are three conventional types of named as neutral point diode clamped [7], flying capacitor [8], and cascaded H-Bridge [9]. Almost all of them are suffering from increased components number per level, and complex control architecture [9].

Among the different topologies for, they can be classified into two main categories: 1) single dc-source inverter such as, and inverters; 2) multi-dc sources inverters such as inverter. While, multi-dc sources inverter is divided into symmetrical and nonsymmetrical topologies. principally, compared to symmetrical topologies nonsymmetrical topologies produce more voltage levels. For more voltage levels almost all of these topologies can be extended by increasing the number of the primary configuration (basic cell).

A new hybrid cascaded inverter was presented. Its operation depends on constructing unidirectional staircases waveforms generated from a series connected cells. Each cell consists of one capacitor and four switching devices. Many topologies were presented in the last decade focusing on minimizing the basic multilevel topologies drawbacks. A new topology presented named multilevel dc link. It consists of a group of basic cells connected in series configuration. However, compared to the conventional topologies, this topology requires increased number of components and high voltage stresses.

The authors presented a topology named transistor-clamped H-bridge . The primary cell can produce five-levels per pole in the output voltage. However, it suffers also from the increased

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components counts, requirements of electrolytic capacitors, complex control methodology. While, the a new single dc-link power supply topology presented, the presented topology generates seventeen voltage levels (0,E/16 ,E/8 ,3E/16 ,E/4 ,5E/16 ,3E/8 ,7E/16 ,E/2 ,9E/16 ,5E/8 ,11E/16 ,3E/4 ,13E/16 ,7E/8 ,15E/16 and E) on the output voltage by using three level flying capacitor inverter and cascades H-bridge. However, this topology utilizes a single dc-power supply. It uses increased number of electrolytic capacitors as floating dc-power supplies. A new double sub-module circuit presented. The presented cell generates a three output voltage levels across its terminals using eight switches and two capacitors. It improved the voltage balancing over capacitors at low switching frequencies; however extra components compared with the equivalent half bridge modules required.

A modified flying capacitors topology presented; to produce five levels for pole voltages it requires three dc-power supplies, nine capacitors, and 36 switching devices. It suffers from the same limitation founded and capacitor's voltage balancing problems. For large scale application some topologies were presented. They basically use a dc-ac inverter stage to convert the dc output voltage from the PV modules to the required ac-voltages.This configuration suffers from many limitations like increasing components counts, high cost, noise, low efficiency, and big installation size.

Based on a nested arrangement, a new sub-family of was presented in [18]. The nested actually lay in multi dc-power sources topologies category. They have two configurations; one produces an odd number of output voltage levels and the other is belonging to even number of output voltage levels. In order to generate a four voltage levels, it requires three dc-power supplies, four capacitors, and 18 switches. However, it has no diodes compared to the inverters but it requires two extra dc-power supplies. Besides, it uses electrolytic capacitor that has increased the system cost and size.

In order to generate three voltage levels, it requires five switches, two capacitors and two diodes. Different basic cells were presented named as clamp-double cell. It generates five output voltage levels. However, it requires six switching devices and two capacitors for its operation. Modified cells were created by combining common known basic cells such as half bridge, full bridge, that can be connected in series, in parallel, in cascaded, or in cross configurations. The resulting cells aim to overcome the basic cells drawbacks. The resulting cells are classified as mixed commutation cells, asymmetrical commutation cells, cross-connected commutation cells, clamped double commutation

cells, and T-connected. However, all of them suffer from electrolytic capacitor limitations.

Based on components per level factor a comparison strategy has been proposed in this paper. To produce one voltage level across the output pole this factor is used to define the required components. Therefore, it acts as a comparison tool that is describing how the different topologies of fully utilize their components. If this factor has a high value, to produce one pole voltage level and vice versa this indicates that a large number of components counts is required. Therefore, the research target is to decrease this factor

F = N + N + N + N + N + N

N (1)

it is clear that the topology presented records the lowest value for this factor and to produce the same voltage level number so, it requires the smallest count of the components. Table I shows the computed factor for the conventional types of the multilevel inverters and the introduced topologies

TABLE I MLI TOPOLOGIES COMPARISON

PROPOSED MODULAR MLI

In this paper a new modular three-phase with reduced components count is proposed. As shown in Fig. 1(a) the suggested three phase symmetrical inverter. Each arm consists of series connection of basic cells with a series connected switch, for example arm A is consists of one cell connected in series with switch. Adding the common dc voltage source in to each arm forms the pole, creating the pole voltages. Fig. 1(b) shows the primary basic cell, where each cell consists of two switches and single dc voltage source In order to obtain the zero state pole voltage another switch is added to the pole. The two switches operate in a complementary fashion. Therefore, each cell can produce two voltage levels: when in ON-STATE, zero voltage is produced across the cell terminals, and when in ON-STATE, volt is applied across the cell terminals. Using only one cell per each pole and applying suitable control signals to the, and, three voltage levels per pole (i.e.) are produced. The output



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pole voltage for cells connected in series configuration is shown in Fig. 1(c).

Fig. 1. (a) Generalized power circuit of the suggested three-phase symmetrical MLI. (b) Basic cell. (c) Pole

voltage waveform for –cell Table II summarizes the different switching states and the corresponding output voltages for both the basic cell and the pole voltage of the proposed topology. The proposed topology is a modular type therefore it can be extended to any levels. Equations (2)–(5) provide the relations of the proposed topology as

N = N + 2 (2) M = 2N + 3 (3) N = 3(2N + 2) (4) N = 3N + 1 (5)

MODULATION TECHNIQUES FOR THE PROPOSED MLI

According to the switching frequency the modulation techniques are classified into two main groups used to drive inverter switches: 1) low frequency modulation technique, 2) pulse-width modulation (PWM) techniques that cover conventional PWM techniques, sinusoidal pulse-width modulation (SPWM), space vector pulse-width modulation (SVPWM), sub-harmonic pulse-width modulation (SHPWM), and switching frequency optimal pulse-width modulation (SFO-PWM). To achieve sinusoidal output voltages waveforms two modulation techniques are investigated in this paper, as described in the following.

TABLE II DIFFERENT SWITCHING STATES AND THE

CORRESPONDING OUTPUT VOLTAGES

A. Low Frequency Modulation Technique In order to investigate the performance of the proposed, a three levels per pole by using single basic cell in each pole is used as shown in Fig. 2.The low frequency modulation is considered as the basic modulation technique due to its lower switching frequency than the other modulation methods. In order to generate the required switching signals for

the proposed , a rectified sine waveform has a frequency equals to the output voltage frequency ( 50 Hz) is compared with a dc voltage signal has an amplitude equal to half of the sine wave amplitude as shown in Fig. 3. The intersection points between them identify six periods (to).

Fig.2. Proposed three-phase MLI topology Four switching signals are constructed from these periods combination in order to generate a sinusoidal output voltage. The control equations for the ( S , S ,S andS ) are given. The same scenario is applied to inverter poles and after shifting the basic sinusoidal voltage with -1200, 1200, respectively. Therefore, the required switching signals for the overall three poles can be generated

S = P + P (6) S = P + P (7) Q = P + P + P + P (8) Q = P + P (9)

Where (+) stands to logic OR. The suggested MLI has 12 modes of operation per one cycle. It is essentially to note that: when switches Q1, Q3andQ5 are in OFF-STATE, switches S1to S6 have two possibilities for operation. Switches S1 to S6 may be in ON-STATE or at OFF-STATE. However, keeping switches S1 to S6 in the OFF-STATE will reduce the overall voltage stresses on Q1, Q3and Q5.

Fig. 3. Switching patterns for low frequency

modulation technique. Balancing three phase output voltage can be achieved byoperating the MLI according to switching states shown inTable III.

TABLE III



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SWITCHING STATES OF THE PROPOSED TOPOLOGY (SWITCH ON: 1, S WITCH OFF: 0)

B. Sinusoidal Pulse-Width Modulation Technique (SPWM): Compare a sinusoidal waveform signal with a triangular waveform to generate the SPWM signals. To synthesize the switches control pulses the comparison operation will produce the Boolean signals that are required. The SPWM technique is successfully applied for the proposed topology. Two different approaches have been proposed as follows. 1) Scheme I: SPWM Using Single Carrier Signal: This scheme uses one carrier signal centered with the sinusoidal modulation signal (sine waveform), and it has an amplitude equal to peak-to-peak value of the modulation signals. It worth mentioning that the modulation signal is shifted by dc level equals to (CR/2), where CR is the carrier signal amplitude. The resulted Boolean output from the comparison between the carrier and the modulating signal produces the main pulse signal G1. Also the pulse signal GP1 is generated by comparing the modulating signal with zero value. After logical processing on G1and GP1, the switching pulses S1, S2,Q1, and Q2 can be generated as specified in (10)–(13).

S = (G X GP ) + (G X GP ) (10) S = (G X GP ) (11) Q = GP + {(G X GP ) + (G X GP )} (12)

Q = GP X (G X GP ) (13) In order to avoid dc-power sources short circuit operate in a complementary mode with dead time. Where stands for logic AND, stands for logic OR stands for invert, and are the signals which will be applied to the gates drive belongs to switches respectively 2) Scheme II: SPWM Using Two Carrier Signals: This scheme compares single modulating signal with two identical and shifted in level carrier signals. Both of them have amplitude equal the modulating signal peak.

Fig. 4. Switching patterns of the proposed MLI for scheme I.

Due to using two carrier signals, there are two Boolean signals named and resulted from the comparison. By Carrying out several logical operations on these two signals as given .The required control pulses for can be obtained.

S = (G X G ) (14) S = G (15)

Q = G X (G X G ) (16) Q = G X (G X G ) (17)

Fig. 5. Switching patterns of the proposed MLI for scheme II.

FUZZY LOGIC CONTROLLER In FLC, basic control action is determined

by a set of linguistic rules. These rules are determined by the system. Since the numerical variables are converted into linguistic variables, mathematical modeling of the system is not required in FC.

Fig.6.Fuzzy logic controller



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The FLC comprises of three parts: fuzzification, interference engine and defuzzification. The FC is characterized as i. seven fuzzy sets for each input and output. ii. Triangular membership functions for simplicity. iii. Fuzzification using continuous universe of discourse. iv. Implication using Mamdani’s, ‘min’ operator. v. Defuzzification using the height method.

TABLE IV: Fuzzy Rules

Fuzzification: Membership function values are assigned to the linguistic variables, using seven fuzzy subsets: NB (Negative Big), NM (Negative Medium), NS (Negative Small), ZE (Zero), PS (Positive Small), PM (Positive Medium), and PB (Positive Big). The Partition of fuzzy subsets and the shape of membership CE(k) E(k) function adapt the shape up to appropriate system. The value of input error and change in error are normalized by an input scaling factor.

In this system the input scaling factor has been designed such that input values are between -1 and +1. The triangular shape of the membership function of this arrangement presumes that for any particular E(k) input there is only one dominant fuzzy subset. The input error for the FLC is given as

E(k) = ( ) ( )( ) ( )

(18)

CE(k) = E(k) – E(k-1) (19) Inference Method: Several composition methods such as Max–Min and Max-Dot have been proposed in the literature. In this paper Min method is used. The output membership function of each rule is given by the minimum operator and maximum operator. Table 1 shows rule base of the FLC. Defuzzification: As a plant usually requires a non-fuzzy value of control, a defuzzification stage is needed. To compute the output of the FLC, „height‟ method is used and the FLC output modifies the control output. Further, the output of FLC controls the switch in the inverter. In UPQC, the active power, reactive power, terminal voltage of the line and capacitor voltage are required to be maintained. In order to control these parameters, they are sensed and compared with the reference values. To achieve this, the membership functions of FC are: error, change in error and output

The set of FC rules are derived from u=-[α E + (1-α)*C] (20)

Where α is self-adjustable factor which can regulate the whole operation. E is the error of the system, C is the change in error and u is the control variable. A large value of error E indicates that given system isnot in the balanced state. If the system is unbalanced, the controller should enlarge its control variables to balance the system as early as possible. One the other hand, small value of the error E indicates that the system is near to balanced state.

Fig 7 input error membership functions

Fig 8 change as error membership functions

Fig 9 Output variable membership functions

SIMULATION RESULTS A single cell has been chosen to produce

five levels per line-to-line load voltages. However, the proposed topology can be extended to cells. The proposed topology has been simulated using MATLAB.



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Fig. 10. Pole voltages and line-to-line voltage (VAB)

with low frequency modulation technique.

Fig. 11. Output phase voltages ( , , and ) with low frequency modulation technique. (a) Simulation.

Fig.12. Inverter outputs with load with low frequency modulation technique. (a) Simulation.

Fig.13. Pole voltages for scheme I, mi =0.95 and fs =2.5 kHz. (a) Simulation.

Fig.14. Line-to-line voltages for scheme I, mi =0.95 and fs =2.5 kHz.(a) Simulation.

Fig.15. Phase voltages for scheme I, mi =0.95 and fs =2.5 kHz. (a) Simulation.

Fig. 16. Pole voltages for scheme II, mi =0.95 and fs =2.5 kHz. (a) Simulation.

Fig. 17. Line-to-line voltages for scheme II, mi =0.95 and fs =2.5 kHz. (a) Simulation.

Fig.18. Phase voltages for scheme II, mi =0.95 and fs =2.5 kHz. (a) Simulation.

Fig. 19. Line-to-line voltage and phase voltage at for scheme I, mi =0.95 and fs =2.5 kHz. (a) Simulation.


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Fig. 20. Line-to-line voltage and phase voltage for

scheme II, mi =0.95 and fs =2.5 kHz. (a) Simulation.

Fig.21. Inverter output voltages: (a) three phase line-to-line voltages (b) line-to-line voltage, phase voltage

and the phase current under R-L load.

Fig.22. Voltage total harmonic distortions with different modulation strategies.

TABLE V: MLI PROPOSED TOPOLOGY

Fig.23. Comparison between the proposed and the

addressed topologies.

The proposed topology compared to the presented topologies provides a good solution from both system topology and control algorithm point of view. The problematic issues related to electrolytes capacitors and their voltages balancing have been eliminated. Therefore, the proposed inverter has better efficiency than the others.

CONCLUSION This paper presents a new design and

implementation of a three-phase multilevel inverter for distributed power generation system using low frequency modulation and sinusoidal pulse width modulation as well. A new modular multilevel inverter topology using two modulation control techniques is presented. Compared with existing topologies the proposed has several advantages i.e. lower number of components count such as isolated dc-power supplies, switching devices, electrolyte capacitors, and power diodes are required. So it exhibits the merits of high efficiency, lower cost, simplified control algorithm, smaller inverter's foot print and increased the overall system reliability. It can be extended to higher stages number leads to a good performance issues such as low, low, and low and eliminating the output filter will be obtained, due to the modularity of the presented topology. Beside the low frequency modulation, two schemes are successfully applied to control the suggested. This paper also suggests a significant factor, which defines the required components to generate one voltage level across the output pole terminals.To maximize the number of voltage levels the impact of the proposed topology is its proficiency using a reduced number of isolated dc voltage sources and electronic switches. Moreover, this paper proposes a significant factor, which is developed to define the number of the required components per pole voltage level. In the literature based on comparison is provided in order to categorize the different topologies of the s addressed.. To verify the control technique and performance of the topology by using simulation results

REFERENCES [1] S. J. Park, F. S. Kang, M. H. Lee, and C. U. Kim, “A new single-phasefive-level PWM inverter employing a deadbeat control scheme,” IEEETrans. Power Electron., vol. 18, no. 3, pp. 831–843, May 2003. [2] V. G. Agelidis, D. M. Baker, W. B. Lawrance, and C. V. Nayar, “Amultilevel PWM inverter topology for photovoltaic applications,” inProc. Int. Symp. Ind. Electron., Jul. 1997, vol. 2, pp. 589–594. [3] G. J. Su, “Multilevel DC-link inverter,” IEEE Trans. Ind. Appl., vol.41, no. 3, pp. 848–854, May–Jun. 2005. [4] M. Calais, L. J. Borle, and V. G. Agelidis, “Analysis of multicarrierPWM methods for a single-



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phase five level inverter,” in Proc. PowerElectron. Specialists Conf., 2001, vol. 3, pp. 1351–1356. [5] C. T. Pan, C. M. Lai, and Y. L. Juan, “Output current ripple-free PWMinverters,” IEEE Trans. Circuits Syst. II, Exp. Briefs., vol. 57, no. 10,pp. 823–827, Oct. 2010. [6] T. C. Neugebauer, D. J. Perreault, J. H. Lang, and C. Livermore, “Asix-phase multilevel inverter for MEMS electrostatic induction micromotors,”IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, no. 2, pp.49–56, Feb. 2004. [7] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clampedPWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523,Sep. 1981. [8] M. F. Escalante, J. C. Vannier, and A. Arzandé, “Flying capacitor multilevelinverters and DTC motor drive applications,” IEEE Trans. Ind.Electron., vol. 49, no. 4, pp. 809–815, Aug. 2002. [9] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Pérez, “Asurvey on cascaded multilevel inverters,” IEEE Trans. Ind. Electron.,vol. 57, no. 7, pp. 2197–2206, Jul. 2010. [10] M. A. Pérez, S. Bernet, J. Rodriguez, S. Kouro, and R. Lizana, “Circuittopologies, modeling, control schemes, and applications of modularmultilevel converters,” IEEE Trans. Power Electron., vol. 30, no. 1,pp. 4–17, Jan. Student Details:

Rajasekhar Reddy.D received his Bachelor of Technology degree in Electrical & Electronics Engineering and Master of Technology in Power Electronics from JNTU kakinada, A.P. in 2012 and 2018respectively.Areas of interests are in, Power Electronics and Drives, FACTS and Electrical Machines.

Guide Details:

SUMAN PAUL REDDY T received his Bachelor of Technology degree in Electrical & Electronics Engineering and Master of Technology in Power Electronics from JNTU Hyderabad, A.P. in 2006 and 2011respectively. Currently, working as an Assistant Professor & Head, Dept. of EEE in Universal College of Engineering and Technology, Guntur, A.P. His areas of interests are in, Power Electronics and Drives, FACTS and Electrical Machines.


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DESIGN AND ANALYSIS OF THREE-PHASE SYMMETRICAL … · DESIGN AND ANALYSIS OF THREE-PHASE SYMMETRICAL MULTILEVEL VOLTAGE SOURCE INVERTER USING FUZZY CONTROLLER RAJASEKHAR REDDY.DESAM1,