DEPARTMENT OF INFORMATION SCIENCE AND ENGINEERING

Study Material for Academic Year 2020-21 (Odd Semester)

COURSE NAME : DIGITAL LOGIC DESIGN

COURSE CODE : 19ISE33

SEMESTER : III

DepartmentofISE NHCE

(Draw this diagram using the previous page expressions)

Show how final carry is generated for a parallel adder when two numbers added are A: 1111and B: 000 l.

Solution : First it calculates, G; and P; parallely.

Gi=Ai.Bi

Pi=Ai+Bi

Go = 1.1 = l, G1 = 1.0 = 0, G2 = 1.0 = 0, G3 = 1.0=0.

AndPo =l+l=l,P1=l+O=l, P2=l+O=l,P3=l+O=l,

C-1 =O.

Then substituting thesein equation of C3 we get final carry as

C3 = G3 + P3G2 + P3P2.G1+ P3 P2P1.Go + P3P2P1Po.C1

[refer the formula Ci=AiBi+(Ai+Bi)Ci-1 = Gi+PiCi-1]

= 0 +LO+ 1.1.0 + Ll.1.1 + 1.1.Ll.O

=O+O+O+l+O

=1

ARITHMETIC LOGIC UNIT:

Arithmetic Logic Unit, popularly called ALU is multifunctional device that can perform both arithmetic

and logic function. ALU is an integral part of central processing unit or CPU of a computer. It comes in

variousforms with wide range of functionality. Other than normal addition, subtraction it can also

perform increment,decrement operations.

As logic unit it performs usual AND, OR, NOT, EX-OR and many other complex logic functions. It also

comes with PRESET and CLEAR options, invoking which all the function outputs are made 1 and O

respectively.

Normally, a mode selector input (M) decides whether ALU performs a logic operation or an arithmetic

operation. In each mode different functions are chosen by appropriately activating a set of selection

inputs.

Very popular discrete ALU device from TTL family is IC 74181.It is a 4-bit ALU that can generate 16

different kinds of outputs in each mode selected by four selection inputs S3, S2, S1 and So.

The functional diagram of this IC with pin numbers and corresponding truth table is shown in above Fig.

this truth table considers data inputs A and Bare active high. A similar but different truth table is

obtained if data is considered as active low.

The Cout is activated ( active low) by addition as well as subtraction because subtraction is carried out

by 2 's complement addition. Note that, if the result of an arithmetic operation is negative it will be

available in 2 's complement form.

The A= B output is activated when an the function outputs are 1, i.e. F3 ... F0 = 1111. Output A= B,

together with Cout can give functions like A>Band A <B.

Note that A = B is an open collector output; thus when more than 4-bits are to be compared this output of

different ALU devices are wire-ANDed, simply by knotting outputs together to get the final result.

The outputs Cout, G3_0 and P3_o are useful when addition and subtraction of more than 4-bits are

performed using more than one IC 74181.

Logic operations are done bit-wise by making M = l and choosing appropriate select inputs.

Let us see how AND operation between two 4-bit numbers 1101 and O 111 is to beperformed. Enter

input A3 .. Ao = 1101 and B3 .. Bo = 0111. Make S3 .. S0 = 1011 and M = I to choose logic function.

For arithmetic operations M = 0 to be chosen and we have to appropriately place Cin ( active low), if

any. For example, ifwe want to add decimal numbers 6 with 4 we have to place 0110 for 6 at A and 0100

for 4 at B. Then with S3 .. S0 = 1001 (from truth table) and Cin = 1 (active low) the output generated is

F3 .. F0 = 1010 which is decimal equivalent of 10.

MODULE 4 :Sequential Circuit Elements

Latches, types of Flip-flops, Flip-flop excitation tables, Registers, type of Shift Registers, Universal shift Registers, Applications of Shift Registers –Ring Counter, Johnson Counter, Sequence generator, Verilog implementation of Flip-flops and Registers.

REGISTERS

• A register is a group of flip-flops used to momentarily store binary-information (e.g. 1101).

• Each flip-flop can store either 0 or 1. The flip-flops used to construct registers are usually edge-triggered JK, SR or D types.

• Applications:The register can also be used

→ to accept input-data from an alphanumeric keyboard and then present this data at the i/p of a microprocessor chip.

→ to momentarily store binary-data at the output of a decoder.

→ to perform various arithmetic operations. For ex: multiplication & division.

→ to count number of pulses entering into a system as up-counter, down-counter,ring-counter or johnson-counter.

→ as serial-adder , sequence-generator and sequence-detector.

• UART(Universal Asynchronous Receiver Transmitter) is a chip used to exchange data in a microprocessorsystem.

TYPES OF REGISTERS

• Shift-register is a group of flip-flops connected in such a way that a binary-number can be shifted into or out ofthe flip-flops.

• The bits in a binary-number can be moved from one place to another in following 2 ways:

→ Serial shifting: Data-bits are shifted one after the other in a serial fashion with one bitshifted at each clock transition

→ Parallel shifting: Data-bits are shifted simultaneously with a single clock transition.

• Shift-register types are

→ Serial in-Serial out (e.g. 7491, 8 bits)

→ Serial in-Parallel out (e.g. 74164, 8 bits)

→ Parallel in-Serial out (e.g. 74165, 8 bits)

→ Parallel in-Parallel out (e.g. 74198, 8 bits)

Serial in-Serial out Serial in-Parallel out Parallel in-Serial out Parallel in-Parallel out

SERIAL IN-SERIAL OUT (SISO):

SHIFTING BINARY-DATA INTO THE REGISTER

• A common clock provides trigger at its negative edge to all the flip-flops (Figure).

• The output of one D flip-flop is connected to input of the next.

• At every clock trigger, data stored in one flip-flop is transferred to the next flip-flop.

• Data-transfer takes place like this Q->R, R->S; S->T and serial data-input(D) is transferred to Q.

• Suppose that 4-bit number 0100 has to be loaded into the register. When clock signals are applied, followingtable shows the shifting

of bits.

Fig: Data transfer through serial input in a shift register

Now,consider the example of shifting the data 1010,the following events happen at each clock edge.

At clock edge A,

→ flip-flop Q has serial data-input 0

→ flip-flop R has input 0 from output of Q

→ flip-flop S has input 0 from output of R and

→ flip-flop T has input 0 from output of S.

When clock triggers, these inputs get transferred to corresponding flip-flop outputssimultaneously so that QRST=0000.Thus,

at clock trigger, values at DQRS is transferred to QRST.

(note: before entering binary number, by default all flip-flops are cleared, that's why initialvalue of QRST=0000).

So,at clock edge A: DQRS=0000. As the clock trigger at A, the values at DQRS is transferred to QRST and QRST=0000.

At clock edge B: DQRS=1000. As the clock trigger at B, the values at DQRS is transferred to QRST and QRST=1000.

At clock edge C: DQRS=0100. As the clock trigger at C, the values at DQRS is transferred to QRST and QRST=0100.

At clock edge D: DQRS=1010. As the clock trigger at B, the values at DQRS is transferred to QRST and QRST=1010.

D Q

Q

D R

R

D S

S

D T

T

Serial Data

Input

Clock

TimeA B C D

Clock1

0

1

0

1

0

1

0

1

0

1

0

Q

R

S

T

D

1

0

1

0

Figure : 4-bit serial input shift register Fig. timing diagram

SHIFTING BINARY-DATA OUT OF THE REGISTER

• Suppose that the register has the 4-bit number QRST=1010 stored in it.

• When clock signals are applied, following events happen:

Before Time A: The register holds the bits QRST=1010.The LSB 0 appears at T.

At Time A: The bits are all shifted one flip-flop to the right. A 0 is shifted into Q and the LSB is shifted out the right-end and lost. The

second LSB 1 appears at T. The register holds the bits QRST=0101.

At Time B: The bits are all shifted one flip-flop to the right. A 0 is shifted into Q. The third LSB 0 appearsat T. The register holds

QRST=0010.

At Time C: The bits are all shifted one flip-flop to the right. A 0 is shifted into Q. The MSB 1 appears at T.The register holds

QRST=0001.

At Time D: The MSB is shifted out the right end and lost. A 0 is shifted into Q. The registers holdsQRST=0000. Thus, the binary-data

stored is shifted out of the right-end of the register in a serial fashionand lost after 4 clock cycles.

Figure : Waveform for shifting 1010 out of register

7491 8-BIT SHIFT REGISTER

• As shown in logic diagram, 7491 register has eight RS flip-flops connected to provide a serial input as well as aserial output.

• The clock input at each flip-flop is negative-edge-trigger-sensitive. However, since the applied clock signal ispassed through an

inverter, data will be shifted on the positive-edges of the input clock pulses.

• The inverter connected between R and S on the first flip-flop means that this circuit functions as a D-type flipflop.

• The data input is applied at either A or B.• A data level (0 or 1) at A is complemented by the NAND gate and then applied to the R

input of the first flip-flop.

• On a positive clock transition, a 1 at input will set the flip-flop i.e. this 1 is shifted into the first flip-flop.

• The NAND gate with inputs A and B simply provides a gating function for the input data stream if desired. Ifgating is not desired,

simply short A & C together and apply the input data stream to this connection.

Figure :74191 8-bit shift register

SERIAL IN-PARALLEL OUT (SIPO)

• Binary-data is shifted into register serially, but shifted out in parallel.

• The 74164 is an 8-bit SIPO shift-register. It is constructed by using RS flip-flops having clock inputs that aresensitive to NTs.

• 74164 register is similar to 7491 with two exceptions:

i) All 8 bits of any number stored in the register are available simultaneously as an output.

ii) Each flip-flop has an asynchronous clear-input. A low level at the clear-input will immediately reset allflip-flops low(0000 0000).

The clear-input is asynchronous i.e. it can be done at any time.

• Suppose that the serial-data is connected to A, then B can be used as a control-line. Here's how it works:

B is held high: The NAND gate is enabled and the serial input-data passes through the NAND gateinverted. The input-data is shifted

serially into the register.

B is held low: The NAND gate output is forced high, the input-data stream is inhibited, and the nextpositive clock transition will shift a

0 into the first flip-flop. Each succeeding positive clock transition willshift another 0 into the register. After 8 clock pulses, the register

will be full of zeros (QAQBQCQDQEQFQGQH=0000 0000).

• As shown in waveform, the serial-data is input at A while the control-signal is applied at B.

• The first CLEAR pulse occurs at time A and resets all flip-flops to 0.

• The clock begins at time B, but the first PT does nothing since the control-line is low. At time C, the control-linegoes high, and the

first data bit(a 0) is shifted into the register at time D.

• The next 7 data bits are shifted in, in order, at times E,F,G,H,I,J & K. The clock remains high after time K, andthe 8-bit number 0010

1100 now resides in the register and is available on the eight output line.

Figure :74164 8-bit shift registerFigure:Waveform for entering data 00110100 into register

PARALLEL IN-SERIAL OUT (PISO)

•54/74166 is a 8bit register &the same circuit is repeated 8 times.it is capable of either serial or parellel data entry and serial data

o/p.•There are 8 RS flip flops and a logic circuitry is attached to it.As all the 8 logic circuitry is same,analysis of one circuit is enough

to understand the working .The working is as follows:Fig a IC pin diagram is for reference,•There is one control input in the circuit (fig

c)which decides whether X1 or X2 has to be shifted into flipflop.And two AND gates and one NOR gate is connected.TheClocked SR

FF & inverter forms D FF.The datais clocked into FF during clock transisitions•The inputs X1 & X2 is for serial data entry &parellel

data entry.(X1 & X2 represents serial i/p &parellel data entry,Control input is labeled as shift/load in fig b.For analysis considered as

X1 & X2,Control input )•CONTROL I/P is HIGH:Consider X1 =X2=1,with control i/p is high upper AND gate o/p =1 & lower AND

gate o/p =0.So the NOR o/p= 1.After inverter the S input to the FF=1.So now upper AND gate is selected which means data X1 is

shifted ie.seriali/p is shifted.•CONTROL I/P is LOW:Consider X1 =X2=1,with control i/p is low upper AND gate o/p =0 & lower

AND gate o/p =1.So the NOR o/p= 1.After inverter the S input to the FF=1.So now lowerr AND gate is selected which means data X2

is shifted ie.parellel loading..•Now refer fig b,8 circuits are connected.The same analysis which is discussed above for one circuit can

be applied for all.Basically this circuit allows 2 different operations 1.serial data entry from first FF QA to QH.2.Parellel data entry

labelled as A to H.Now the control i/p is labeled as SHIFT/LOAD.•If SHIFT/LOAD is LOW-single clock transistion loads 8 bits of

data(A to H)into the register in parellel.•If SHIFT/LOAD is HIGH- clock transistion will shift data serially through registers,with

entering data at serial i/p.•When clock inhibit pin is high ,NOR o/p=0,so clock is not reaching thr FF & this wallows the register to stop

and hold its contents.

Fig C.Control Logic circuit

PARALLEL IN-PARALLEL OUT (PIPO)

• Here, data can be shifted either into or out of the register in parallel (Figure).

• Each flip-flop is negative-edge-triggered, and thus a PT will shift data into the register.

• The 6 data bits, D1 through D6 are all loaded into the register in parallel. The loaded-data is immediately available in

parallel, at the outputs, Q1 through Q6.Since this type of register is used to store data, it is also called a data-latch.

• It is not possible to shift stored data either to the right or left. A low level at the clear input will immediately reset all flip-flops low.

• The clear input is asynchronous ie it can be done at any time.Note: Take one example data & explain how it get shifted and draw

timing diagram

UNIVERSAL SHIFT REGISTER(74195)

• Four basic types of shift register are: i)serial in serial out, ii)serial in parallel out, iii)parallel in serial out andiv)parallel in parallel out.

Serial in or serial out can be made possible by shifting data in any of the two directions,left shift and right shift. A universal shift

register can perform all the 4 operations and is also bidirectional innature (Figure).

• In 74194 register, there are 2 separate inputs for serial data for left and right shift.

• There are two mode control inputs which select the mode of operation for the universal shift registeraccording to below table

•Referring the diagram,there are four 4:1 multiplexer blocks in the circuit.Two selection inputs are S1S0.•For S1S0=00,the 2nd

AND

gate o/p is tranferred to o/p.ie previous stage o/p.so this mode is ‘HOLD’ mode.•For S1S0=01,the 4th

AND gate o/p is transferred which

corresponds to ‘shift right’. •For S1S0=10,the 1st AND gate o/p is transferred which

corresponds to ‘shift left’. •For S1S0=11,the 3rd

AND gate o/p is transferred which

corresponds to ‘parellelload’.Thei/p ’Clear' is active low and resets all FF.•‘Clock’ is +ve edge triggred due to two inversions in the

circuit.

APPLICATIONS OF SHIFT REGISTER:

1.Ring counter 2.Switched tail counter or jhonson counter 3.Sequence generator and sequence detector 4.Serial adder

NOTE:Ring counter &jhonson counter –lab circuit can also be referred

SEQUENCE GENERATOR AND SEQUENCE DETECTOR

Sequence Generator

• This is used to generate a prescribed-sequence repetitively .

• Shift register can be represented as pipe full of data and each flip-flop represents one compartment of it.

• The leftmost flip-flop is connected to serial data-in and rightmost provides serial data-out.

• When clock trigger occurs, data-transfer takes place.

• The shift-register is connected like a ring-counter and with triggering of clock; the binary-word stored in theregister comes out

sequentially from serial out but does not get lost as it is fed back as serial-in to fill the register.•The shift register is connected like a

ring counter & with triggering of clock the binary word stored comes out sequentially from serial out and fed back as serial in to fill the

register again.Sequence generated 1011 is shown in figure.

Sequence Detector

• This is used to check binary-data stream and generate a signal when a particular sequence is detected.

• This has one register to store the binary-word, we want to detect from the data stream.

• Input-data stream enters a shift-register as serial data-in and leaves as serial-out.

• At every clocking instant, bit-wise comparisons of these 2 registers are done through Ex-NOR gate.

• 2-input Ex-NOR gives logic HIGH when both inputs are low or both of them are high.

• The final output is taken from a 4-input AND gate, which becomes 1 only when all its inputs are 1 i.e. all the bitsare matched.•The

circuit is shown for the data received so far is 0111 and the word to be matched is 1011.The first 2 bits are mismatched and Ex-NOR

o/p a are low,and Y=0.when the serial data in 1 comes,the content of FF got shifted & the sequence is 1011 and matches with

sequence.o/p Y=1.

• This is also programmable i.e. if we want to change the binary-word to be detected, we simply load that in thebottom register.

Figure : (a)4-bit sequence generator (b)4 bit sequence detector

RING COUNTER

• It is a basic shift register with direct feedback such thatthe contents of the register simply circulate around the register when the clock

is running.

• Suppose that QA is high and all other flip-flops are low.On very first clock PT, the 1 in A will shift into B and A will be reset, since

the 0 in H will shift into A. All other flip-flops will still contain 0s. The second clock pulse will shift the 1 from B to C, while B resets.

• The third clock PT will shift the 1 from C to D, and so on. Thus this single 1 will shift down the register, travelingfrom one flip-flop

to the next flip-flop each time the clock goes high. When it reaches flip-flop H, the next clock PTwill shift it into flip-flop A by means

of the feedback connections.

• The 1 simply circulate around the register in a clockwise direction, moving ahead one flip-flop witheach clock PT. This configuration

is frequently referred to as a circulating register or a ring counter.

Figure : Ring Counter (a)74164 8-bit shift register with feedback line from QH to A-B

(b)Waveform when register has a single 1 and seven 0s

JOHNSON COUNTER (SWITCHED TAIL COUNTER) • It is a shift register with inverting output of last flip-flop fed to first

flip-flop input (Figure ).

• Consider 4-bit counter. Initially, all the flip-flops are cleared. i.e. QRST=0000.

• When first clock trigger occurs, flip-flop stores QRST=1000. The output of last stage T is 0. Therefore,complement output of last

stage is 1.This is connected back to the D input of first stage. So, D=1.

• When second clock trigger occurs, flip-flop stores QRST=1100.When third clock trigger occurs, flip-flop stores QRST=1110.

• For any N-bit shift register, johnson counter can count up to 2N number of clock pulse and gives modulo-2Ncounter.

• The output Y, derived by AND operation of first and last flip-flop inverting outputs gives a logic high at every 2Nth clock cycle. This

two-input AND gate which decodes states repeating in the memory units to generate outputthat signals counting of a given number of

clock pulses is called decoding gate.

Figure : (a) 4 bit Johnson Counter b)it’s state table

Verilog program for PIPO(this program is for IC 74174

Modulepipo(D,clock,clear,Q)

input Clock,clear;

input [5:0] D

output [5:0] Q

reg[5:0] Q;

always@ (negedgeClockor negedgeClear)

if (~Clear)

Q=6'b0;

else

Q=D;

endmodule

SISO

module siso (D,clock,T)

input clock,D;

output T; // Clear as in

reg T; // LHS to

reg Q,R,S;

always @ (negedgeClock)

begin Q <= D;

R <= Q;

s <= R;

T <= S;

end

endmodule

SIPO

module sipo(D,Clock,Q);

input clock,D;

output [3:0] Q;

reg [3:0] Q

always @ (negedgeClock)

begin Q [0]<= D.;

Q [1]<=Q [0].;

Q [2]<= Q [1];

Q[3]<= Q [2];

end

endmodule

Differences between Combinational & sequential circuits:

Sl.No Combinational circuits Sequential circuits

1 The output variables are at all times dependant on the input variables

Output depends on present and past input variables

2 Memory unit is not required Memory unit is required to store the history of the past variable

3 Faster in speed as the delay is due to only propagation delay of gates.

Slower in speed as the delay is due to propagation delay of gates and clock signal.

4 Easy to design Comparitively harder

5 Example:Adder,Mux Flip flop,counters

Differences between Latch & Flip flop

Sl.No Latch Flip flop

1 Latch changes state as soon as input is given and does not depend on control input or clock input i.e. there is no clock present in latch.

Flip flop changes state only during the clock signal.

2 Transparent devices Non- Transparent devices

3 Does not depend on clock Flip-Flops are edge sensitive i.e. flip flop will store the input only when there is a Rising(positive) or falling edge(negative) of the clock.

4 Latches are faster. Flip flops are slower

5 Examples of flip flops are D flip flop, T flip flop, SR flip flop, JK flip flop

Examples of latches are SR latch(NAND & NOR)