DEMP LAB MANUAL

EXPERIMENT NO.1

STUDY OF LOGIC GATES

Department of PPT, SIES GST

EXPERIMENT NO.1

STUDY OF LOGIC GATES

AIM: To study logic gates.

APPARATUS REQUIRED:

Logic circuit, trainer kit, wires, IC7408, IC7432, IC7404, IC7486, IC7400, IC7402

THEORY:

The three logic gates AND, OR and NOT are used to produce any digital system. These are called basic gates. The gates NAND and NOR are called universal gates because they are sufficient for realization of any logical expression.

AND gate

This gate has HIGH output only when all the inputs are high, its truth table is shown below:

A B C0 00 11 01 1

The symbol for AND gate is as shown below


OR gate

This gate has LOW output only when all the inputs are low, its truth table is shown below:

A B C0 00 11 01 1

The symbol for OR gate is as shown below


NOT gate

In this when input is low, output is high and vice versa. It is also referred as complementary gate or inverter. Its truth table is as shown below

A Y01

The symbol for NOT gate is as shown below


NAND gate

The combination NOT and AND operator is known as NAND operator. The truth table is given as below

A B C0 00 11 01 1

The symbol for NAND gate is as shown below


NOR gate

The combination NOT and OR operator is known as NOR operator. Its truth table is as shown below

A B C

0 00 11 01 1

The symbol for NOR gate is as shown below


EXCLUSIVE OR gate

It is widely used in digital circuits. This finds application where two digital signals are to be compared .Its truth table is as shown below

A B C0 00 11 01 1

The symbol for EX-OR gate is as shown below


PROCEDURE:

1. Mount IC on trainer kit.2. Connect Vcc and GND connections to IC.3. Apply logic 0 or 1 inputs to IC gate with logic switches provided in the kit.4. Connect the cable from output of gate to LED indicator to observe output.5. Switch on the trainer kit and verify output from truth table.

CONCLUSION:


EXPERIMENT NO: 2

VERIFICATION OF BOOLEAN LAWS AND THEOREMS USING LOGIC GATES


EXPERIMENT NO: 2

VERIFICATION OF BOOLEAN LAWS AND THEOREMS USING LOGIC GATES

AIM: Verification of Boolean laws and theorem using Logic Gates.

(De-Morgan’s theory).

APPARATUS REQUIRED:

Digital trainer kit, IC7408, IC 7404, IC7432, single stranded wires.

THEORY:

De-Morgan’s first theorem states that complement of the sum of variables is equal to product of complements of individual variables. Corresponding expression is as given below.

De-Morgan’s second theorem states that complement of the product of variables is equal to sum of complements of individual variables. Corresponding expression is as given below.

BABA


A+B=A⋅B

Truth table for 1st theorem:

A B

Last column of these two tables is same. This proves the theorem.

Truth table for 2nd theorem:

A B BA BA

A B A B BA


A B A+B A+B

A B A⋅B

Last column of these two tables is same. This proves the theorem.

PROCEDURE:

1. Mount IC on trainer kit.2. Connect Vcc and GND connection to IC.3. Apply logic 0 or 1 inputs to IC gate with logic switches provided in the kit.4. Connect the cable from output of gate to LED indicator to observe output.5. Switch on the trainer kit and verify output from truth table for different input

combination

CONCLUSION:


EXPERIMENT NO:3

STUDY OF HALF ADDER AND HALF SUBTRACTOR USING GATES

EXPERIMENT NO:3

STUDY OF HALF ADDER AND HALF SUBTRACTOR USING GATES


AIM: To study half adder and half subtractor using XOR and AND gate.

APPRATUS REQUIRED: Digital trainer kit, IC7408, IC7432, single stranded wires.

THEORY:

In electronics, an adder or summer is a digital circuit that performs addition of

numbers. In many computers and other kinds of processors, adders are used not only

in the arithmetic logic unit, but also in other parts of the processor, where they are

used to calculate addresses, table indices etc.

Half Adder

The half adder adds two one-bit binary numbers A and B. It has two outputs, S and

C(Sum and Carry) The simplest half-adder design, incorporates an XOR gate for S

and an AND gate for C. With the addition of an OR gate to combine their carry

outputs, two half adders can be combined to make a full adder.

LOGIC CIRCUIT


TRUTH TABLE

A B SUM CARRY0 00 11 01 1

The logical expression for sum and carry can be obtained from truth table and using

K-Map is

E = A B

C = AB

Half Subtractor

In electronics, a subtractor can be designed using the same approach as that of an

adder. The half-subtractor is a combinational circuit which is used to perform

subtraction of two bits. It has two inputs, A (minuend) and B (subtrahend) and two

outputs D (difference) and B (borrow).


LOGIC CIRCUIT

TRUTH TABLE

A B DIFFERENCE BORROW0 00 11 01 1

PROCEDURE:

1. Mount IC on trainer kit.2. Connect Vcc and GND connection to IC.3. Apply logic 0 or 1 inputs to IC gate with logic switches provided in the kit.4. Connect the cable from output of gate to LED indicator to observe output.5. Switch on the trainer kit and verify output from truth table.


CONCLUSION:


EXPERIMENT NO: 4

STUDY OF FULL ADDER AND HALF ADDER USING LOGIC GATES

EXPERIMENT NO: 4

STUDY OF FULL ADDER AND HALF ADDER USING LOGIC GATES

AIM: To study full adder and full subtractor.


EQUIPMENTS REQUIRED:

Digital trainer kit, IC7482, IC7432, single stranded wires.

THEORY:

Full adder

A full adder is to add carry from lower adder bit when multibit addition is performed.

For this purpose a third input terminal is included in this kit. It adds An, B n, & Cn-1

inputs where An, B n, & Cn-1 are nth order bits of numbers A & B respectively & (n-1)

inputs generated from addition of (n-1)th order bits. The full-adder is usually a

component in a cascade of adders, which add 8, 16, 32, etc. binary numbers

Let A, B, C be the 3 inputs where A & B are numbers & C is carry generated in

previous addition.

For sum S = A B C

For carry C = AB+BC+AC

LOGIC CIRCUIT


Truth Table: Full Adder

Full subtractor

It is used to borrow multiple times from lower subtractor when multibit subtraction is

performed. For this purpose third input terminal is used. This circuit is used for

subtraction of An, B n, & Cn-1inputs where An, B n, & Cn-1are nth order bits of numbers

An, B n, & Cn-1 is borrowed bit used to make subtraction possible.

Difference=A B C

Borrow = B+ C+BC


INPUT OUTPUT

A B C SUM CARRY

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

LOGIC CIRCUIT

Truth Table: Full

Subtractor


INPUT OUTPUT

A B Bin DIFFERENCE BORROW

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

PROCEDURE:

1. Mount IC on trainer kit.2. Connect Vcc and GND connection to IC.3. Apply logic 0 or 1 inputs to IC gate with logic switches provided in the kit.4. Connevt the cable from output of gate to LED indicator to observe output.5. Switch on the trainer kit and verify output from truth table.

CONCLUSION:


EXPERIMENT NO: 5

STUDY OF FLIP-FLOPS

EXPERIMENT NO: 5

STUDY OF FLIP-FLOPS

AIM: To study flip flop.


APPARATUS:

IC 7400, IC7474, single stranded wires, power supply, trainer kit.

THEORY:

Electronic circuits are combination of memory element and combinational logic circuits. The combinational part accepts logic signals from external input and from the present output of memory elements. The combinational circuit operates on these inputs to produce various new output. Some of the new outputs are stored in the memory element referred to as next state.

In sequential logic circuit, most important part seems to be memory element. The memory element is called as flip-flop. Flip flop is also called as latch because it holds or latches content of previous level of signal.

Clock:

The main key control in synchronous sequential circuit is clock signal. Clock has a regular waveform that repeat once every T seconds, where T is the clock period or cycle. Normally clock has 50% duty cycle. During each clock period, clock exhibits a positive edge and a negative edge. Either of the edge changes state of the circuit. It is convenient to design a clock such that it begins at one triggering edge and ending at the next.

Preset:

Preset is used to accomplish required initial condition.

Clear:

Clear is used to directly reset the required initial condition.

Different types of flip-flop are

1) SR F/F (Set Reset)2) D F/F (Delay)3) JK F/F4) T F/F (Toggle)

SR F/F (Set Reset)

Truth Table


Diagram

D F/F (Delay)

Truth Table


Diagram

JK F/F

Truth Table


Diagram

T F/F

Truth Table


Diagram

PROCEDURE:

1. Place the IC 7408 and IC 7432 on the breadboard and IC 7474 in slot of IC embedded in the kit.

2. Make the connections with the help of circuit diagram.3. Apply all the combinations of 0 and 1 at the input.4. Check the output of the preset state.


5. To get the output of the next state press pulse button.

CONCLUSION:


EXPERIMENT NO: 6

STUDY OF FLIP-FLOP CONVERSION

EXPERIMENT NO: 6

STUDY OF FLIP-FLOP CONVERSION

AIM: To study D to JK Flip-Flop conversion.


APPARATUS REQUIRED:

IC 7432, 7408, 7474, single stranded wires, power supply, trainer kit.

THEORY:

D Flip-Flop:

It has only input referred as D input or delta input. Hence the delta appears as output in equivalent to applied input at the end of the CLK pulse. Thus, the transfer of data from input to output is delay. Hence the name is delay or D-type flip-flop.

JK Flip-Flop:

The uncertainty in state of SR Flip-flop can be eliminated by converting it into JK Flip-flop.

Race-Around Condition: The difficulty of both high inputs been not allowed in SR Flip-flop is eliminated in JK-Flip-flop. By using feedback connections from output to input but in that duration tp of both pulses the output oscillates back and forth between 0 and 1. At the end of Clock pulse, the value of Q is uncertain.

PROCEDURE OF FLIP-FLOP CONVERSION USING K-MAP:


PROCEDURE:

1) Place the IC 7408 and IC 7432 on the breadboard and IC 7474 in slot of IC embedded in the kit.

2) Make the connections with the help of circuit diagram.3) Apply all the combinations of 0 and 1 at the input.4) Check the output of the preset state.5) To get the output of the next state press pulse button.

CONCLUSION:


EXPERIMENT NO: 7(A)

ADDITION OF TWO 8-BIT NUMBERS

EXPERIMENT NO: 7(A)

ADDITION OF TWO 8-BIT NUMBERS

AIM: To perform addition of two 8-bit numbers.

APPARATUS REQUIRED: Dyna 85 Kit


ALGORITHM:

1. Start the program by loading the first number to the accumulator from some memory.

2. Move the data to another register B.

3. Get the second data and load it to the accumulator.

4. Add the two register contents

5. Check for Carry.

6. Store the value of sum and carry in different memory locations

7. Terminate the program.

4. PROGRAM:


OBSERVATIONS:

CONCLUSION:


EXPERIMENT NO: 7(B)

SUBTRACTION OF TWO 8-BIT NUMBERS

EXPERIMENT NO: 7(B)

SUBTRACTION OF TWO 8-BIT NUMBERS

AIM: To perform subtraction of two 8-bit numbers

EQUIPMENTS REQUIRED: Dyna-85 kit


ALGORITHM:

1. Start the program by loading the first number to the accumulator from some memory.

2. Move the data to another register B.

3. 3) Get the second data and load it to the accumulator.

4. Subtract the two register contents

5. Check for Carry.

6. If CARRY is present, take 2’s complement of the accumulator contents.

7. Store the value of borrow and difference in different memory locations

8. Terminate the program.

PROGRAM:


OBSERVATIONS:

CONCLUSION:


EXPERIMENT NO: 8(A)

MULTIPLICATION OF TWO 8-BIT NUMBERS

EXPERIMENT NO: 8(A)

MULTIPLICATION OF TWO 8-BIT NUMBERS

AIM: To perform multiplication of two 8-bit numbers


APPARATUS: Dyna-85 kit

ALGORITHM:

1)Start the program by loading the first number to the accumulator from some memory.

2)Move the data to another register B.

3)Get the second data and load it to the accumulator.

4)Add the two register contents

5)Check for Carry.

6) Increment the value of carry

7) Check whether repetitive addition is over, and, store the value of product and carry in

different memory locations

7)Terminate the program.

PROGRAM :


OBSERVATIONS:

CONCLUSION:


EXPERIMENT NO: 8(B)

DIVISION OF TWO 8-BIT NUMBERS

EXPERIMENT NO: 8(B)

DIVISION OF TWO 8-BIT NUMBERS

AIM: To perform division of two 8-bit numbers

APPARATUS: Dyna – 85 kit


ALGORITHM:

1)Start the program by loading the HL pair with the address of the memory location. 2)Move

the data to another register B.

3)Get the second data and load it to the accumulator.

4)Compare the the two register contents to check for carry.

5)Subtract the two numbers.

6) Increment the value of carry

7) Check whether repetitive subtraction is over, and, store the value of quotient and

remainder in different memory locations

8)Terminate the program.

PROGRAM:


OBSERVATIONS:

CONCLUSION:


EXPERIMENT NO: 9

PROGRAM TO READ AND WRITE DATA TO 8255

EXPERIMENT NO: 9

PROGRAM TO READ AND WRITE DATA TO 8255

AIM: To write a program to read and write data to 8255.


APPARATUS: Dyna 85 Kit, 8255 Study kit

THEORY:

8255 is a programmable peripheral interfacing IC which contains 3 I/O ports which can be programmed in different modes. To program the function to all three I/O ports, it contains a register called control register. The control register gives the signal which is used to define the function of each I/O port and in which mode they should operate. Port A and Port B are 8-bit ports and Port C is a 6-bit port. 8255 has direct bit select/reset compatibility which is available for Port C[BSR mode]. The ports can be operated in 3 modes.

Mode 0- Simple I/O

Mode 1- Strobbed I/O

Mode 2-Strobbed bidirectional I/O.

I/O mode Control Word Format

PROGRAM:

For reading data from 8255


For writing data to 8255


CONCLUSION:


EXPERIMENT NO: 10

EXECUTION OF PROGRAM OF DOWN COUNTER

EXPERIMENT NO: 10

EXECUTION OF PROGRAM OF DOWN COUNTER

AIM: Write and execute a program for down counter.

APPARATUS: Dyna – 85 kit

ALGORITHM


1)Start the program by loading the HL pair with the address of the memory location.

2) Initialize register B with value 00.

3) Decrement the contents of register B.

4)Transfer the data from register B to accumulator.

5) Transfer data from accumulator to memory location indicated by HL pair.

6) Increment contents of register pair HL

7) go to step 3 again

PROGRAM

CONCLUSION:


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DEMP LAB MANUAL