Deliverable D3.1 Front-end design - 5g-champion.eu · 5GCHAMPION project task 3 ... to provide Antenna Module functionality for EU side 5G Radio ... a baseline for developing the

5G Communication with a Heterogeneous, Agile Mobile network in the Pyeongchang Winter Olympic Competition

Grant agreement n. 723247

Deliverable D3.1 Front-end design

Date of Delivery: 29 November 2016

Editor: Saila Tammelin (Univ. Oulu)

Associate Editors: Aki Korvala (NOKIA)

Authors:

Aarno Pärssinen (Univ. Oulu), Olli Kursu (Univ. Oulu), Saila Tammelin (Univ. Oulu), Jari Haukipuro (Univ. Oulu), Giuseppe Destino (Univ. Oulu), Antonio Clemente (CEA), Emilio Clvanese Strinati (CEA), Aki Korvala (NOKIA), Jari Huttunen (NOKIA)

Dissemination Level: PU

Security: Public

Status: Final

Version: V1.0

File Name: 5GChampion_D3_1_Final

Work Package: WP3

Title: Deliverable D3.1: Front-end design

Date: 29-11-2016 Status: Final

Security: Public Version: V1.0

The information contained in this document is the property of the contractors. It cannot be reproduced or transmitted to thirds without the authorization of the contractors.

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Abstract

This report provides the architecture description and key specifications for the RF front-end developed in 5GCHAMPION project task 3.1. The objective of the report is i) to give description of the selected architecture for the RF-front-end for mmW backhauling based on phase shifters and linear phase array, ii) to identify the technologies for the design and implementation of the RF-FE iii) to provide system calculations for verifying the assumptions used in link budget analyses. In addition auxiliary antenna architecture based on electronically reconfigurable transmit array antennas or discrete flat-lenses is presented. The front-end architectures described in the report will further developed and implemented in tasks 3.1 and 3.3.

Index terms

5G, RF transceiver, millimeter wave backhaul, RF architecture, phased array, beamforming, automatic gain control, power amplifier.





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Contents

1 Introduction ......................................................................................... 6

2 RF front-end architecture description ............................................... 8

2.1 RF architecture assumptions 8

2.2 Block diagram and functionality 9

2.2.1 Main functionality 9

2.2.2 Antennas and antenna filters 10

2.2.3 AGC 11

2.2.4 Calibration 12

2.2.5 Control interface 12

3 Selected technologies and implementation .................................... 14

3.1 Power amplifier 14

3.2 Other components (LNA, mixers, phase shifters) 15

3.3 PCB 15

4 Specifications .................................................................................... 17

4.1 RF system partition 17

4.2 Key RF specification 17

5 Auxiliary architecture solution ......................................................... 19

5.1 Preliminary analysis on phase quantization effects 19

5.2 Integration of the transmit array and RF transceiver 20

5.3 Unit-cell and steering logic architecture 21

6 Conclusion ......................................................................................... 24

References ................................................................................................... 25





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List of Acronyms 3GPP 5G

3rd Generation Partnership Project 5th Generation

5GTN 5G Test network AGC automatic gain control BB Baseband BRU Backhaul Radio Unit CA Carrier aggregation dBi decibel isotropic EIRP Effective isotropic radiated power EU European union GaN Gallium nitridi HW hardware IF intermediate frequency KPI Key performance indicator KR Korea LNA low noise amplifier LO local oscillator LoS line-of-sight MIMO MME

Multiple-input-multiple-output Mobility Management Entity

MMIC monolithic microwave integrated circuit mmW MUX

millimetre wave Multiplexer

OIP output intercept point PA Power amplifier PCB Printed circuit board PoC Proof of Concept QAM QPSK

Quadrature amplitude modulation Quadrature Phase Shift Keying

RF-DFE Radio Frequency Digital Frontend RSSI Received signal strength indicator SDN SNR

Software defined networking Signal-to-Noise Ratio

TDD Time Division Duplex WP Work package





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Table of Figures

Figure 1: System overview and the BRU components. ............................................................ 6

Figure 2: a) RF beamformer with phase-shifters where the number of antenna elements are dimensioned based on the range-rate trade-off, b) RF beamformer with p-i-n diodes and c) RF hybrid-beamformer with phased-array and p-i-n diodes. .......................................................... 7

Figure 3: a)-b) Power amplifier dimension compared to 2×2 array at 28 GHz. c) Radiation pattern for 2×2 antenna element. .............................................................................................. 8

Figure 4: Block diagram of one transceiver channel. ............................................................... 9

Figure 5: Linear phased array and radiation pattern at 26.5 GHz frequency. ......................... 10

Figure 6: AGC loop of the receiver. ......................................................................................... 11

Figure 7: AGC functionality diagram. ...................................................................................... 12

Figure 8: Antenna module control interfaces in RF hybrid-beamformer implementation with phased-array and PIN diodes.................................................................................................. 13

Figure 9: PA technologies state of art. .................................................................................... 14

Figure 10: Study of PA package effects PCB area. ................................................................ 15

Figure 11: An example of PCB layout design around power amplifier................................... 16

Figure 12: An example of thermal simulation result. ............................................................... 16

Figure 13: Cascaded TX gain and OIP3. ............................................................................... 18

Figure 14: Cascaded RX gain and noise figure with minimum and maximum attenuation. ... 18

Figure 15: Analysis of the 20×20-unit-cell ideal transmitarray performance as a function of the phase quantization. (a) Aperture efficiency as a function of the ratio F/D. (b) Radiation patterns on the E-plan and (c) gain as a function of the steering direction. .......................................... 20

Figure 16: Schematic view of the transceiver with electronically reconfigurable transmit array. ................................................................................................................................................. 21

Figure 17: Schematic view of the 1-bit electronically reconfigurable unit-cell and an examples of unit-cell with 1 or 10 bias lines. ........................................................................................... 22

Figure 18: Schematic view of the bias line architecture. ........................................................ 23





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1 Introduction

The objective task 3.1 is to develop mmWave RF front-end and antenna solutions for a backhaul/fronthaul transceiver operating in the frequency range of 24 – 28 GHz. This objective is approached by defining the mmWave RF front-end platform architecture, investigating, developing and testing advanced antenna solutions for wireless backhaul transmission in dynamic environment and, finally, integrating selected antenna solutions with RF front-end for the wireless backhaul/fronthaul transceiver platform. Based on implementation constraints and practical performance, the proposed backhaul solution could be demonstrated in the lab/Oulu 5GTN and in demo cases defined by WP6.

The developed solution targets to provide Antenna Module functionality for EU side 5G Radio Backhaul Units (5G BRU). The backhaul radio unit (BRU) consists of base-band unit (BB), RF-digital front end (RF-DFE) and antenna module, as show in Figure 1 and explained in report IR2.1 [1].

Figure 1: System overview and the BRU components.

The BB provides L1 functionalities and is capable of 2.5 Gbit/s maximum data rate. It implements classical OFDM signal processing and digital MIMO. Together with the RF-DFE, the BRU can be used for single or multi-beam transmissions. RF-DFE will provide flexible interface to different types on antenna modules. Antenna module is considered to include RF front-end (transmitter and receiver hardware) and antennas for mmWave radio.

This report will focus on RF front-end design giving the architecture description and definition of the key RF specifications for EU side development. The practical implementation of RF front end is strongly linked (i) to baseband and digital RF front-end solutions provided by consortium





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partners to be used in the proof-of- concept demonstrations, (ii) the selection of RF beamforming as technology baseline for back-haul implementation and (iii) the selected antenna implementation technologies to be further studied as 5GCHAMPION project research goals. The practical design limitations coming from previous constraints affecting RF front-end design are discussed in this report. The front-end interfaces to antenna are described, but the detailed of antenna specification and implementation will be the topics of report D3.2.

As indicated in the IR2.1, three alternatives for RF beam former implementations are investigated, namely, phase shifter based beam former with phased-array antenna, electronically steerable antenna with p-i-n diode (lens type beam former) and hybrid p-i-n diode beamformer with 2×2 phased array as focal source. The schematic view of these different solutions is presented in Figure 2.

a)

b)

c)

Figure 2: a) RF beamformer with phase-shifters where the number of antenna elements are dimensioned based on the range-rate trade-off, b) RF beamformer with p-i-n diodes and c) RF hybrid-beamformer with phased-array and p-i-n diodes.

The front-end development in this report focuses first on the option shown in Figure 2 a) as this implementation provides a baseline for developing the RF frond-end required by the focal source shown in Figure 2 b).

The reminder of this document is as follows. Section 2 discusses the key assumptions behind the selected RF front-end architecture with phase-shifters and phased linear antenna array. It gives the detailed description of the implementation including block diagram and description of the functionality of the different parts. In Section 3 we detail the RF front end implementation with the description of the components and technologies as well as we discuss constraints in their selection. Section 4 provides RF system chain calculations and summarises the main RF specifications. Also, we investigate the implementation of the RF beamformer with the electronically reconfigurable transmit array antennas or discrete flat-lenses controlled with p-i-n diodes. Section 5 gives conclusion of the findings during RF design phase and explains how the design work is used by other work packages.

Focal source

2

mb1

ma

1

mb

mS

2

ma

Unit-cell

Antenna array

Phase-shifters

(fixed/switchable/tunable)

P1 P2

P4 P5P3





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2 RF front-end architecture description

2.1 RF architecture assumptions

The research in this project includes the study of the feasibility of the mobile backhaul working in the frequency band of 26.65 – 29.12 GHz (frequency range used in Korea in the planned location for the P-o-C demonstrations). The mobility brings more requirements with respect to conventional backhaul including beam steering and the requirement to manage farfield/nearfield problem with varying signal levels at receiver. To get the range the maximising the output power at transmitter is important.

The selected RF beamforming architecture is based on phase-shifters and linear antenna array providing 2D beamforming. The size of the array and corresponding array gain is the trade-off between the available power from the PA, physical dimensions coming from the number of PAs and array physical size and effective isotropic radiated power (EIRP). Increasing the array gain by increasing the number of array elements makes it possible to lower the power per power amplifier (PA) feeding the antenna array element but at the same time the practical implementation aspects of printed circuit board needs to be taken into account. EIRP which includes the effect of array gain is a parameter regulated by authorities and this limits the selection of power per PA and number of antenna elements independently.

For the phased array antennas we investigated an architecture where one power amplifier (PA) is driving a subarray which is compatible with the actual size of the PA. The physical size of the PA matches with the physical size of sub module array of 4 patch antenna with aperture-coupled feed as presented in Figure 3 a)-b). Preliminary simulations for 2×2 subarray show a main lobe gain of 12 dBi which was taken as working assumption for architecture work and link budget analyses system design. The simulated radiation pattern of the 2×2 subarray calculated at 26.5 GHz Figure 3 c).

a) b) c)

Figure 3: a)-b) Power amplifier dimension compared to 2×2 array at 28 GHz. c) Radiation pattern for 2×2 antenna element.





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2.2 Block diagram and functionality

TO FBRX

LO gen

IF input

Reference clock input

LEGEND

Power amplifier

Driver amplifier

Low noise amplifier

PIN diode switch

LO genPhase shifter

Frequencysynthesizer

MixerFilter

Power divider

Attenuator

2x2 antenna element

Directionalcoupler

Receivedsignal strength

indicatorRSSI

RSSI

Embedded processor for phase shifter, PA bias, LO gen and attenuator control incl. RSSI

measurement

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

TO FBRX

Figure 4: Block diagram of one transceiver channel.

2.2.1 Main functionality

The front-end electronics hardware shown in Figure 4 implements the RF signal paths from the intermediate frequency (IF) to final transmitter frequency fed into inputs of antennas. Since we have TDD system where the transmitter and the receiver are not operating at the same time, we have implemented a partially shared signal path and shared antennas for the transmitter and the receiver. The transmit (TX) and receive (RX) modes are separated by using p-i-n diode switches.

On the transmit path the following functionality is implemented:

Power division of IF signal to two separate paths,





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Frequency transition to final RF frequency using mixer for which LO-signal is fed from frequency synthesizer (LO-gen),

Signal amplifying before feeding to distribution network implemented by power dividers,

Signal phase shifting independently in each RF branch,

Signal amplification by power amplifier (PA) before,

Signal filtering before feeding to antenna element.

On receiver path the following functionality is implemented:

Signal filtering after antenna,

Signal amplification using low noise amplifier (LNA),

Signal phase shifting using phase shifter,

Signal combination from different antenna branches using power combiners,

Signal amplification and gain control,

Frequency transition to intermediate frequency IF.

Signal distribution to the phased array antenna is implemented in two parts due to practical printed circuit board implementation which targets to locate each driving PA as close to antenna subgroup as possible. Two parts share the same LO but have own mixer and amplifier paths.

2.2.2 Antennas and antenna filters

The linear phased array of 16 2x2 sub-elements was selected to fulfil the requirements used in

link budget calculations presented in report IR2.1 [1].The early simulations shown in Figure 5

indicate that it is possible to achieve antenna gains around 22 dBi as used in link budget

calculations. This is preliminary performance used in system calculations.

Figure 5: Linear phased array and radiation pattern at 26.5 GHz frequency.





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Antenna filter requirements are set mainly by out-of-band spurious emissions specifications.

As exact frequency and sites used for demonstration are not decided at the time of HW

architecture the following options for antenna filter are considered: ceramic laminate (LTCC)

filter implementation, commercial component or micro-strip implemented on front-end PCB.

2.2.3 AGC

In order to maximize the dynamic range of the receiver, an Automatic Gain Control (AGC) functionality is implemented on the RF board. A sample from IF signal is taken by means of microstrip directional coupler. The sample is then fed to a detector circuit which takes care of Received Signal Strength Indicator (RSSI) functionality. As an option, RSSI functionality exists also on the BB. Gain control (attenuation) is carried out with adjustable attenuators in the RF part of the RX chain. The controlling routine is run by an external microcontroller unit (MCU), which is commanded by a PC terminal. The schematic view of the ACG loop of the receiver is presented in Figure 6.

LO gen

RSSI

LOG

Detector

Attenuator

MCUAGC control SW

Figure 6: AGC loop of the receiver.

According to system calculations, the sensitivity level is calculated in level -63 dBm and maximum input signal level can be -37 dBm within linear gain area. These are calculated with next specifications:

Signal modulation 64 QAM,

Noise bandwidth 100 MHz,

Signal-to-Noise-ratio 22 dB,

Signal headroom 10 dB.

Between the sensitivity level and maximum input value the gain (attenuation) of the receiver chain can be adjusted so signal at mixer output is within acceptable limits. According to previous values, the dynamic range of the RX is 26 dB. The Figure 7 shows the functionality of the AGC including hysteresis of the control when received signal levels is increasing or decreasing.





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Figure 7: AGC functionality diagram.

2.2.4 Calibration

For the calibration purpose the applicable directional couplers are implemented on front-end board. Amplitude and phase errors can be corrected by changing the phase-shifter control words or the gains of the controllable amplifiers.

2.2.5 Control interface

RF front-end electronics require significant amount of control signals which are not presented

in the block diagram. The front-end board antenna controller unit includes an embedded

processor, additional control logic as well as voltage regulation to generate different control

signals at required voltage levels to individual components. The interface to the microprocessor

is designed in such a way that the front-end board can be used as an independent antenna

module for development and RF measurements and controlled directly from PC. Processor

and implementation of RSSI detection also allows the use of a front-end board for independent

algorithms development. This is also the first step in P-o-C integration where the TX/RX timing

information is controlled directly by the RF-DFE. In later phase the front-end module control

can be also connected directly to RF-DFE. Then phase-shifters are controlled in real-time by

the RF-DFE. Figure 8 shows the arrangements for the antenna module control.





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Figure 8: Antenna module control interfaces in RF hybrid-beamformer implementation with phased-array and PIN diodes.





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3 Selected technologies and implementation

The architecture and component selections are based mainly on available commercial components. This was due to tight time schedule on the project’s target to implement full system demonstrator connected to base-band and the frequency range which was not matching with custom based integrated circuit (IC) development projects in University of Oulu Centre of Wireless Communications research group.

3.1 Power amplifier

The study of power amplifier technology state of art ( Figure 9 , presented by University of Oulu [8]) provides clear indication that on the Ka band (26.5–40 GHz) GaN (Gallium nitride) technology offers significantly higher power levels compared to other technologies. From commercial GaN PA components the bare die version of component TGA2595 [9] was selected to optimize the PCB area and wiring losses. The study of different PA package options and effect on PCB form factor is presented in Figure 10.

Figure 9: PA technologies state of art.





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Figure 10: Study of PA package effects PCB area.

3.2 Other components (LNA, mixers, phase shifters)

A GaAs MMIC low noise amplifier MAAL-011111 [10] was selected for the receiver. It offers broadband performance that covers the KA-band while providing a noise figure of 2.5 dB.

A subharmonically pumped (x2) mixer HMC264LC3B [11] with an integrated LO amplifier was selected to achieve the required RF frequency. Subharmonic pumping alleviates the requirement for LO frequency synthesis.

Frequency synthesizer with integrated VCO ADF5355 [12] was selected as the component for LO signal generation. This wideband PLL can generate a maximum frequency of 13.6 GHz. Only one commercial phase shifter product that operates on the KA-band, TGP2100 [13], was

found. This bare die pHEMT component offers 5-bit 360⁰ phase control.

A bare die component MASW-011036 [14] was selected as the p-i-n diode switch to minimize insertion losses. Existing packaged products do not offer the same performance as the selected die component.

3.3 PCB

Low loss and highly temperature stable Isola Astra MT77 was selected as the substrate

material for the PCB. The material offers full core and prepreg build-up and a stable relative

permittivity and loss tangent.

2x2 radiators

2x2 radiators

2x2 radiators

2x2 radiators

2x2 radiators

2x2 radiators

2x2 radiators

2x2 radiators

TGA

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-CP

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MicrostripsDielectric

GND

VDDs & ctrl sign.Dielectric

DielectricControl signals

8 W PA PACK

4 W PA PACK

8 W PA DIE

8 W PA DIE,less capacitors

c

c

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cc

cc

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TGA

259

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P8

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TGA

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P8

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LNA

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Figure 11: An example of PCB layout design around power amplifier.

In order to improve the thermal performance of the design, the power amplifiers are soldered

on a Cu coin that perforates the PCB material and is directly attached to a heat sink on the

bottom of the PCB. An example of PCB layout design around a PA component is shown in

Figure 11. In addition the thermal simulations taking into account PA operation only (Figure 12)

indicate that a PA component will warm up significantly and so in addition to passive cooling

the hardware mechanics should be equipped with fans.

Figure 12: An example of thermal simulation result.





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4 Specifications

4.1 RF system partition

RF chain system calculations were done to make sure that selected component choices and

design options fulfil the requirement for the received signal level at IF input of RF-DFE. At the

transmitter side calculations are done to confirm that the signal stays in the linear region of the

components.

The results of RF chain calculations are shown in Figure 13 and Figure 14. These are

approximate calculations based on component data sheets. Since we do not have nonlinear

models for all the components in the chain, more accurate system simulations are not possible.

Microstrip losses are simulated with a 2.5D EM simulator at 28 GHz. The key specifications

can be derived from RF chain calculations reserving enough headroom for the practical

implementation.

4.2 Key RF specification

The key specifications for the RF front-end implementation are the following:

Frequency band: 27.5 – 30 GHz

Bandwidth: 400MHz

Noise figure (NF) : 10dB

Max transmit power Ptx (max): 27 dBm (per PA driving 2×2 antenna element)

Due to component limitations the predicted optimal working frequency range of the design is 27.5 – 30 GHz. Below 27.5 GHz and above 30 GHz the RF front-end module can be used with reduced performance.





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Figure 13: Cascaded TX gain and OIP3.

Figure 14: Cascaded RX gain and noise figure with minimum and maximum attenuation.





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5 Auxiliary architecture solution

The auxiliary antenna architecture is based on electronically reconfigurable transmit array antennas or discrete flat-lenses. A transmit array antenna (Figure 2(b)) is a spatial feeding array typically composed of one or more focal sources (called focal system) and a planar array or flat-lens realized in standard printed circuit board (PCB) technology. The transmit array operation principle is similar to the one of an optical lens; the energy radiated by the focal system is locally collected by the array elements and phase-shifted in order to focalize the beam in a specific direction of the free-space. The flat-lens array single elements are typically called unit-cells.

The proposed architecture will include p-i-n diodes to electronically control the phase-shift on each unit-cell and implement an analogue beamforming antenna. The unit-cell architecture, which will be developed in the 5GCHAMPION project is based on the previous works realized at CEA-Leti at X (around 10 GHz) [4] and Ka (around 29 GHz) [5] bands. In particular, the 1-bit linearly-polarized unit-cell proposed in [6] will be optimized in order to cover the European and Korean frequency bands. Two designs will be developed to obtain at least a 3 dB transmission bandwidth in the frequency bands 24.25 – 27.5 GHz (Korean transceiver) and 26.65 – 29.19 GHz (European transceiver).

1-bit of phase quantization, which implies a relaxed phase resolution with two phase states (0° or 180°) will be chosen at the cost of quantization loss. Quantization losses do not correspond to actual power losses, but only a reduction of the focusing capabilities of the array, i.e., a lower directivity, side lobe level, and aperture efficiency. The 1-bit phase quantization is selected to make a trade-off between the antenna and steering logic complexity, unit-cell bandwidth, insertion losses due to the integrated phase-shifters, cost of the full antenna and power efficiency.

5.1 Preliminary analysis on phase quantization effects

A preliminary analysis computed using the CEA-Leti proprietary transmit array analysis tool [7] has been performed to predict the impact of phase quantization on the transmit array performances. The simulated array is composed of 20×20 ideal unit-cells (size of the array

aperture is D = 10, where indicates the wavelength in the free space) illuminated by an ideal focal source having a directivity equal to 10 dBi. The ratio between the focal distance (F) and the aperture size indicated as F/D is equal to 0.43 and has been optimized to obtain the maximum efficiency. The array size has been selected to obtain a gain between 20 and 30 dBi, which corresponds to the requirements. Additional losses (around 3 dB when 50% efficiency is considered) will be obtained in the real implementation due to the loss factors of the real focal source and unit-cells, which are not 100% efficiency.

The results of the preliminary analysis are plotted in Figure 15. A 1- to 2-bit phase resolution (180 and 90 phase steps, respectively) typically results in a quantization loss of 1–4 dB. The impact on radiation pattern and steering capability are also analyzed. The pictures show that a gain around 26.1 dBi is theoretically obtained in the case of 1-bit phase quantization. This results must be compared to 29.5 dBi of the case of perfect phase distribution. A steering

capability in the range 60° could be obtained when 1-bit phase quantization is selected with a maximum loss on the gain of 3 dB. In conclusion, in our opinion 1- or 2-bit phase quantization design is a realistic objective for a real demonstration of a full electronically reconfigurable transmit array with a 3 dB relative bandwidth > 10% and an acceptable power efficiency.





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(a) (b)

(c)

Figure 15: Analysis of the 20×20-unit-cell ideal transmitarray performance as a function of the phase quantization. (a) Aperture efficiency as a function of the ratio F/D. (b) Radiation patterns on the E-plan and (c) gain as a function of the steering direction.

In order to reduce the implementation risks, the antenna cost in view of a future industrialization, and realize a full electronically reconfigurable transmitarray in line with the project objectives, a 1-bit phase quantization will be selected. The possibility to implement a 2-bit architecture will be also theoretical analyzed during the 5GCHAMPION project.

5.2 Integration of the transmit array and RF transceiver

The schematic view of the transceiver with the electronically reconfigurable transmit array is presented in Figure 16 and is composed of three different blocks: (i) the digital processing unit, (ii) the RF transceiver, and (c) the electronically steerable flat-lens. The beam-steering control signal is generated in the digital processing unit.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

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Figure 16: Schematic view of the transceiver with electronically reconfigurable transmit array.

5.3 Unit-cell and steering logic architecture

As discussed in the previous sections, the proposed transmit array antennas is based on an

optimized version of the 1-bit unit-cell previously developed at CEA-Leti [6]. The schematic

view of this unit-cell is presented in Figure 17. The cell is realized on a multilayer PCB

architecture composed of four metal layers and two dielectric substrates. Two rectangular

patch antennas loaded by a slot are printed on the top and bottom layers. Instead, a ground

plane and the bias lines are printed on the two inner layers. Two p-i-n diodes have been

integrated on the top patch antenna to locally control the transmission phase. The two diodes

are mounted in antiparallel configuration and could be biased by using a single bias lines. In

fact when one of diode is biased in the forward state with a positive current (between 1 and 10

mA), the second diode is maintained in reverse state using the threshold voltage. As a

consequence, in the case of a 20×20 transmit array (gain around 23 dBi including the phase

shifter losses), 800 diodes are integrated on the array aperture and 400 bias lines are needed

to individually control the transmission phase on each unit-cell.

Electronically steerable flat-lens

2×2 Phased Array

RF transceiver

Me

ch

an

ica

l inte

rfac

e

F3

mm

~ 110×110 mm²

Base Band Unit Steering Control Unit

Be

am

-ste

erin

g c

on

trol s

ign

al

Gain ~ 10 dBi

Digital processing unit





22 / 25

Figure 17: Schematic view of the 1-bit electronically reconfigurable unit-cell and an examples of unit-cell with 1 or 10 bias lines.

In order to obtain a simple architecture the flat-array will be biased considering four subarray

with 100 elements. As a consequence, each antenna subarray will contain 100 independent

bias lines (1 line per unit-cell), as illustrated in Figure 18.

p-i-n Diodes

Bias line

D1

D2





23 / 25

Figure 18: Schematic view of the bias line architecture.

Sub-array

10 10 cells

z

y

x

ml

1l

…

10

0-b

ias

lin

es1

00

-bia

s lines

10

0-b

ias lin

es1

00

-bia

s li

nes





24 / 25

6 Conclusion

In this report we have described the mmWave RF front-end architectures for 5GCHAMPION wireless backhaul solution. The feasibility of the architecture was verified by implementation technology selections to get realistic understanding of the constraints, limitations and design challenges for the selected architecture. These include for example component selections and PCB technology selection. The power amplifier component was selected based on the state-of-art study for power amplifier technology options. For many components the technology choices were limited by the frequency range and the commercial availability of the component during project development time. Based on selected technologies the system calculations were done to confirm the working assumption used in architecture design and for example in link budget calculations. Still calculations are based on nominal component performance parameters and models. Physical measurements are needed to confirm that selected architecture will fulfil the requirements.

Based on RF system calculations the key RF specifications were summarized. These will be used as the design specification for completing RF front-end implementation and antenna designs and theiy give target values for RF performance testing.

The main challenge of the selected architecture is to get EIPR above 40dBi required for targeted range of the wireless backhaul. The output power is limited by power amplifier linearity which might limit the use of higher order modulation schemes [3]. In selected architecture wiring losses are also significant contributor and there is close to 10 dB reservation in link budget for these.

This report will be used by tasks 3.1 to complete RF front-end development. Future work includes the physical implementation of the selected architecture and testing it. Report is also used as bases for antenna implementation and integration of antenna and RF front-end. Report will be used also by task 3.2 for full backhaul transceiver implementation.





25 / 25

References [1] 5GCHAMPION report “Preliminary 5GCHAMPION architecture specifications

(IR2.1),” 2016.

[2] T. Tuovinen, N. Tervo, H. Pennanen and A. Paerssinen, “Providing 10 Gbit/s in

Downlink to a Mobile Terminal with Practical Array Design Beamforming Aspects by,

API- and interface Using Orthogonal MIMO Beams,” in Proc. 22th European

Wireless Conference (European Wireless 2016), Oulu, Finland, pp. 1-6, May 2016.

[3] T. Tuovinen, N. Tervo and A. Paerssinen, “RF System Requirement Analysis and

Simulation Methods Towards 5G Radios Using Massive MIMO,” European

Microwave Conference (EuMC 2016), London, United Kingdom, Oct. 2016.

[4] A. Clemente, L. Dussopt, R. Sauleau, P. Potier, and P. Pouliguen, “Wideband 400-

element electronically reconfigurable transmitarray in X Band,” IEEE Transaction on

Antennas and Propag., vol. 61, no. 10, pp. 5017-5027, Oct. 2013.

[5] L. Di Palma, A. Clemente, L. Dussopt, R. Sauleau, P. Potier, and P. Pouliguen,

“Circularly-polarized reconfigurable transmitarray in Ka-band with beam scanning

and polarization switching capabilities,” IEEE Transaction on Antennas and Propag.,

in press.

[6] L. Di Palma, A. Clemente, L. Dussopt, R. Sauleau, P. Potier, and P. Pouliguen, “1-

bit reconfigurable unit-cell for Ka-band transmitarrays,” IEEE Antennas and Wireless

Propag. Letters, vol. 15, pp. 560-563, 2016.

[7] A. Clemente, L. Dussopt, R. Sauleau, P. Potier, and P. Pouliguen, “Focal distance

reduction of transmit-array antennas using multiple feeds,” IEEE Antennas and

Wireless Propag.. Letters, vol. 11, pp. 1311-1314, Nov. 2012.

[8] Aarno Pärssinen, “New system concepts stretching the requirements of RFICs,”

European Wireless 2016 EuMW workshop WW02 Trends in CMOS RF ICs.

[9] http://www.triquint.com/products/p/TGA2595.

[10] https://www.macom.com/products/product-detail/MAAL-011111

[11] http://www.analog.com/media/en/technical-documentation/data-

sheets/hmc264lc3b.pdf.

[12] http://www.analog.com/media/en/technical-documentation/data-

sheets/ADF5355.pdf.

[13] http://www.triquint.com/products/p/TGP2100.

[14] https://www.macom.com/products/product-detail/MASW-011036.

http://www.triquint.com/products/p/TGA2595

https://www.macom.com/products/product-detail/MAAL-011111

http://www.analog.com/media/en/technical-documentation/data-sheets/hmc264lc3b.pdf

http://www.analog.com/media/en/technical-documentation/data-sheets/hmc264lc3b.pdf

http://www.analog.com/media/en/technical-documentation/data-sheets/ADF5355.pdf

http://www.analog.com/media/en/technical-documentation/data-sheets/ADF5355.pdf

http://www.triquint.com/products/p/TGP2100

https://www.macom.com/products/product-detail/MASW-011036

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