Delay Components in Circuit

7/31/2019 Delay Components in Circuit

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CS623

CAD for VLSI

Lecture 30 : Delay Components in aCircuit

Shankar Balachandran

Dept. of Computer Science and Engineering

Indian Institute of Technology Madras

[email protected]

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The following slides are adopted from UTD 3325

Slides

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Combinational Circuit Timing Parameters

Rise Time (tr), the time required for a signal totransition from 10% of its maximum value to 90%

of its maximum value.

Fall Time (tf), the time required for a signal totransition from 90% of its maximum value to 10%

of its maximum value.

Propagation Delay (tpLH, tpHL), the delay measuredfrom the time the input is at 50% of its full swing

value to the time the output reaches its 50% value.

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Timing parameters (contd)

time

Vin

Vout

time

Vma x

0.5Vma x

0.5Vma x

Vma x0.9Vma x

0.1Vma x

tpLH tpHL

tr tf

0

0


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Example: Gate delayDetermine the worst case propagation delay throughthese circuits.

( ) ( ) ( ){ }max 2 5 , 3 5 , 3 8pt gd= + + =

2 ns 4 ns 2 gd

3 gd

5 gd

2 4 6pt ns= + =

2 gd

3 gd

5 gd

3 gd 6 gd

( ) ( ) ( ) ( ){ }max 2 5 , 3 5 , 3 , 6 3 9pt gd= + + + =

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Timing Analysis of Combinational Circuits

Using gates with finite propagation delays, tpLHand tpHL instead of zero gate delays used in

functional analysis.

4 ns5 nsXOR

2 ns3 nsINV

tp H Ltp LHGate

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Vin

V1

V2

V3

Vou t

t=0

4

2

3

2

5

8 ns

01 Transition on Vin

Vin

V1

V2

V3

Vou t 4

3

2

3

5

9 ns

10 Transition on Vin

4 ns5 nsXOR

2 ns3 nsINV

tpH LtpL HGate

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Setup and Hold Times

Setup time, tsu, is the time period prior to the clock

becoming active (edge or level) during which the

flip-flop inputs must remain stable.

Hold time, th, is the time after the clock becomes

inactive during which the flip-flop inputs must

remain stable.

Setup time and hold time define a window of time

during which the flip-flop inputs cannot change

quiescent interval.


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Propagation Delay

Propagation delay, tpHL and tpLH, has the same

meaning as in combinational circuit beware

propagation delays usually will not be equal for all

input to output pairs. There can be two propagation

delays: tC-Q (clockQ delay) and tD-Q (dataQ

delay).

For a level or pulse tr iggered latch:

Data input should remain stable till the clock becomes

inactive.

Clock should remain active till the input change is

propagated to Q output. That is, active period of the clock,

tw > max {tpLH, tpHL}

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Latch & Flip -flop Timing Parameters

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Latch and Flip-flop Timings

CLK

D

Q

Q

Flip-flop

Latch

tsuth

tC-Q

tsu

thtC-Q

tsuth

tC-QtD-Q

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Characterizing Timing Setup time, hold time

Propagation delays

tC-QtC-Q

tD-Q

Flip-FlopLatch

tD-CtD-C


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More Precise FF Setup & Hold Times

CLK

D

Q

t

t

t

Sampling Window

0

50

100

150

200

250

300

350

-200 -150 -100 -50 0 50 100 150 200

Data-Clk [ps]

Clk-Output[ps]

Setup Hold

Minimum Data-Output

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Sequential Circuit Timing

Once the functionality of a sequential network is

designed, its timing parameters must be

determined. Timing problems can be very subtle

because timing parameters can vary with device

age and other operating conditions.

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Global setup time (Tsu)

Global hold time (Th)

Maximum clock frequency

Clock skew.

These parameters are derived using the circuit (known) delays described

below.

tio delay from input of IFL to output of OFL

tif delay from circuit inputs of flip-flop inputs

tfo delay from flip-flop outputs to circuit outputs

tff delay from flip-flop outputs to flip-flop inputs

tc-q clock to Q propagation delay of flip-flopstsu setup time of flip-flops

th hold time of flip-flops

tc clock delay; time required for clock to reach all flip-flops

Timing Parameters

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X (at sequential circuit input)

Changes that occur at inputs can be delayed by as much as

maximum tif by the time they reach the flip-flop inputs. Hence, we

want to setup circuit inputs relative to clock edge appearing at the

flip-flops.

Similarly, hold time of the circuit inputs relative to the system clock

at the source is given by

= + max max min ifu su cs t t tT

= +max min max h if c hT t t t

Global Setup and Hold Times

Tsu Th

th

tsu

CLK (at clock source)tc

CK (at FF clock input)

tif

tif

D (at FF input)


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The limiting factor on the clocking rate is the propagation delaythrough the IFL block:

Changes on the Qs must propagate through the IFL before they

can affect the next state

Clock Frequency

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The limiting factor on the clocking rate is the propagation delay

through the combinational logic block (input forming logic):

Changes on the Qs must propagate through the combinational

logic before they can affect the next state

Clock Frequency

Comb.

logic

Q iD i

QjDj

CK i

CKj

tff

CL K

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Maximum Clock Frequency

For an edge-triggered circuit: minimum clock period is,

Maximum Clock Frequency:

+ +C Q ,ma x ff ,ma x su ,ma x clk t t tT

clk

clkT

f1

tsu

Tck (=Tclk)

CKi

Edge Triggering

tff

Dj

Qi

tC-Q

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Maximum Clock Frequency

For an edge-triggered circuit: minimum clock period is,

Maximum Clock Frequency:

+ +C Q ff su max max max

clk t t tT

clk

clkT

f1

Comb.

logic

Q iDi

Qj

Dj

CKi

CKj

tff

CL K

tsu

Tck (=Tclk)

CKi

Edge Triggering

tff

Dj

Qi

tC-Q


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Timing Violations

The clock period (Tclk) has a lower bound oftff.max .

If the clock period is equal to (tff.max + tC-Q.max) then the

flip-flop state changes can violate setup times.

Remedy:

Use faster flip-flops (decrease tC-Q )

Use faster gates (decrease tff)

Use a slower clock (increase clock period, Tclk)

+ +max maxmaxfC fl uc k Q st tT t

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The previous discussion assumes that clock signals arrive

at all flip-flops simultaneously - this is not a good

assumption since it is not true in practice.

Because of different wire lengths over which the clock

signals travel and the load at the destination, there is a

slight difference in clock arrival times at different flip-flop

inputs.

Clock skew, tskew, is the difference in time between

triggering edges seen at different flip-flops. Clock skew

affects minimum Tclk.

Clock Skew

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Therefore, for an edge-triggered circuit with clock skew,

Clock skew is a significant factor in determining the speed of high-performance

sequential circuits. The larger the skew, the slower the circuit will operate.

max,max,max,max, suffpskewclkttttT +++

Max. Clock Frequency wi th Skew

tsu

Tck (=Tclk)

CKi tskew

CKj tp

Qj tff

Di

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Therefore, for an edge-triggered circuit with clock skew,

Clock skew is a significant factor in determining the speed of high-performancesynchronous circuits. The larger the skew, the slower the circuit will operate.

max max max maxclk skew C Q ff suT t t t t

+ + +

Max. Clock Frequency with Skew

tsu

Tck(=Tclk)

CKi tskew

CKj tC-Q

Qj tff

Di

ts k ew

Comb.

logic

Q iDi

Qj

Dj

CK i

CKj

tff

CL K


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Can any skew be countered simply by slowing down the clock?

If the skew is too large, state change caused by an edge at FFi will changethe state ofFFj erroneously when the clock edge finally gets there!

In the worst case, iftff= 0 then,

flip-flops propagation delay must be greater than its hold time.

min maxallowedskew C Q ht t t

=

Maximum Allowable Clock SkewNo

CKj

C Q ff skew ht t t t + +CKi

Qi

Dj

state ofDj before

clock becomes active

state ofDj after

clock becomes active

tskew

thtC-Q

tff

tskew

Comb.logic

Q iD i

QjDj

CKi

CKj

tff

CL K

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For the circuit given below determine all the sequential circuit timing

parameters.

For a D flip-flop use: tsu = 2ns, th = 15ns and tC-Q = 20ns

For a NAND gate use: tp,max= 10ns and tp,min = 3ns

Timing Analysis Example

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.

Why is clock skew irrelevant in this example?

nstt

nstt

nstt

nstt

nstt

nstt

nandpc

nandpc

nandpff

nandpff

nandpif

nandpif

62

202

62

202

62

303

min,,min,

max,,max,

min,,min,

max,,max,

min,,min,

max,,max,

==

==

==

==

==

==

,max ,max ,min

,max ,min ,max

,max ,max ,max

,max

,max ,min ,min ,max

2 30 6 26

20 1 5 6 29

20 20 2 42

1 / 42 23.8

20 6 15 11

su su if c

h h if c

clk C Q ff su

clk

skew C Q ff h

T t t t ns

T t t t ns

T t t t ns

f ns MHzt t t t ns

= + = + =

= + = + =

+ + = + + =

= =

= + = + =

For a D flip-flop use: tsu = 2ns, th = 15ns, tC-Q = 20ns

For a NAND gate use: tp,max= 10ns, tp,min = 3ns

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1-Phase Clock w/ Level Triggering

( )

( )

and

ormin max ma

min max ma

x

max min max

min

min

m

x

i

max

n

w d q h skew

w d q h s

skew d q w

l

l

w

h

w su

l

ke

t t t t

t t t

t t t

t

t

t

t t

t

t

+ +

+

+ >

Latch must be open for less than the shortest combinational logic

delay but more than the worst setup time.

Positive clock skew


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Sequential Systems Using Latches

Latches can be used to create sequential systems. However, since these are

level-triggered clocking must be done carefully must ensure that state changes

only once per clock cycle.

Use narrow-width clock whosepulse width is less than the fastest possible path

through the combinational logic.

To guarantee correct next state, make sure that the clock period is longer thanthe worst-case propagation delay through the combinational logic.

tw< tff.min+ tD-Q.min

> (tD-Q.max + tff.max+ tsu.max)

CLK

ts k ew

Comb.

logicQ iD i

QjDj

CK i

CKj

tffCL K

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Clocking Constraints with Latches

th

CKi

tD-Q

Qi

tff

Di

tskewCKj

Dj

tw

min min max max

max

w D Q ff h skew

w su

t t t t t

t t

< +

>

tw

tsu

tskew

Comb.

logicQ iD i

QjDj

CKi

CKj

tffCLK

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Clocking Frequency with LatchesTclk

tsu

CKi

tD-Q

Qjtff

Dj

tskew

CKj

Di

( )max min max max maxclk skew w su D Q ff su

T t t t t t t

> + + + +

tsu

tw

ts k ew

Comb.

logicQ iD i

QjD

j

CK i

CKj

tffCL K

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Delay Components in Circuit