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System and SoC Verification Trends
Deepak Gupta, Senior Services Manager – AE
Past 10 years: IP bottom-up verification approach led by the Specman/e/eRM MDV solution
Metric Driven Verification Metric Driven Verification Metric Driven Verification Metric Driven Verification EnvironmentEnvironmentEnvironmentEnvironment
Automatic Data and BFM Signal Layer
Coverage Monitor
StimulusSequences
Customer’s Application Specific Components
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CPU subsystemCPU subsystem
3D Graphics Core
DSP A/V
Applica
tion
Acceler
ators
&
A
S
AES
&
Fabric
CPU
I $
D $
CPUI $
D $
L2 cache
Customer’s Application Specific Components
The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.
CPU subsystemCPU subsystem
3D Graphics Core
DSP A/V
High speed, wired interface peripherals
DDR3
PHY
Other peripherals
S
A
SATAMIPI
H
MI
HDMI
W
N
WLANL
E
LTE
Low-speed peripheral
subsystem
Low speed peripherals
P
U
PMUM
I
MIPIJ
G
JTAG
I
C
INTCI
C
I2CS
I
SPITi
er
Timer
G
O
GPIO
Dis
lay
Display
U
T
UART
Applica
tion
Acceler
ators
&
A
S
AES
&
Fabric
CPU
I $
D $
CPU
I $
D $
L2 cache
USB3.0
3.0PHY
2.0PHY
PCIeGen 2,3
PHY
Et
et
Ether-net
PHY
SoC XYZe or SystemVerilogor SystemVerilogor SystemVerilogor SystemVerilog
2 © 2012 Cadence Design Systems, Inc. All rights reserved.
AutomaticStimulus
Generation
Data and AssertionCheckers
BFM Signal Layer
Customer’s Application Specific ComponentsCPU subsystemCPU subsystem
3D Graphics Core
DSP A/V
High speed, wired interface peripherals
DDR3
PHY
Other peripherals
S
A
SATAMIPI
H
MI
HDMI
W
N
WLANL
E
LTE
Low-speed peripheral
subsystem
Low speed peripherals
P
U
PMUM
I
MIPIJ
G
JTAG
I
C
INTCI
C
I2CS
I
SPITi
er
Timer
G
O
GPIO
Dis
lay
Display
U
T
UART
Applica
tion
Acceler
ators
&
A
S
AES
&
Fabric
CPU
I $
D $
CPU
I $
D $
L2 cache
USB3.0
3.0PHY
2.0PHY
PCIeGen 2,3
PHY
Et
et
Ether-net
PHY
High speed, wired interface peripherals
DDR3
PHY
Other peripherals
S
A
SATAMIPI
H
MI
HDMI
W
N
WLANL
E
LTE
Low-speed peripheral
subsystem
Low speed peripherals
P
U
PMUM
I
MIPIJ
G
JTAG
I
C
INTCI
C
I2CS
I
SPITi
er
Timer
G
O
GPIO
Dis
lay
Display
U
T
UART
Fabric
USB3.0
3.0PHY
2.0PHY
PCIeGen 2,3
PHY
Et
et
Ether-net
PHY
DesignIP
RTL Simulator
Comprehensive IP and Sub-System verification: should work in ANY SoC context
Paradigm Shift In the Market
Ubiquity of software
Move to Standards-based protocols and IPs
Increasing complexity and # of IP’s to be integrated
Mixed Signal and Low Power Verification Design
Shift from:Serial HW/SW
Development
To:Parallel HW/SW
Development
3 © 2012 Cadence Design Systems, Inc. All rights reserved.
Application / end-user driven requirements
Shrinking time-to-money
Mixed Signal and Low Power Verification Complexity
Debug consuming over 50% of verification task
DesignTrends
Development
Shift from:IP Creation
To:SoC Integration
Debug is a Major Bottleneck in Verification
• Customers spending >50% verification effort in Debug
Verificationefforts
5% 10%
25%
10%Test planning
Test execution (formal + sim + HW)
Debug
Coverage analysis
4
• Verification complexity requires advanced class and macro debug
• Debug methodology shift from signals � Class / Transactions
50%25%
Test creation
Coverage analysis
From serial to parallel HW/SW development
Block Chip PrototypeSilicon lab test
Field test
ROMContent
Drivers / RTOS / ApplicationsDiagnostics& FirmwareHW/SW
Spec
Serial HW->SW Development
Block Chip PrototypeSilicon lab test
Field test
ROMContent
Drivers / RTOS / ApplicationsDiagnostics& FirmwareHW/SW
Spec
5 © 2012 Cadence Design Systems, Inc. All rights reserved.
Time to market
advantage of 6 to
9 months
Parallel HW->SW Development
Integrate HW/SW Early and Often
HW designed in SW context
Software exposed to Spec changes
HW/SW Requires High Performance Platforms
6 © 2012 Cadence Design Systems, Inc. All rights reserved.
SDK
•Highest speed•Ignore hardware•Earliest in the flow
Virtual Platform
•Almost at speed•Less accurate (or slower)
•Before RTL•Great to debug (but less detail)
•Easy replication
RTL Simulation
•KHz range•Accurate•Excellent HW debug
•Little SW execution
AccelerationEmulation
•MHz Range•RTL accurate•After RTL is available
•Good to debug with full detail
•Expensive to replicate
FPGA Prototype
•10’s of MHz •RTL accurate•After stable RTL is available
•OK to debug•More expensive than software to replicate
Prototyping Board
•Real time speed•Fully accurate•Post Silicon•Difficult to debug•Sometimes hard to replicate
• Multiple disconnected SoC simulation environments– Virtual Platform, RTL Sim, HW Acceleration/Emulation, FPGA
Prototype, Post Silicon
• Reducing SoC integration time and effort– Integrating many design IPs and SW components– Requires significant time and effort to verify integration
Main Challenges Integrating and Verifying Large-Scale Multicore SoCs
7 © 2012 Cadence Design Systems, Inc. All rights reserved.
– Requires significant time and effort to verify integration– High cost to re-integrate & re-verify changes– Debug is a major challenge to isolate the root cause– Verification effort for SoC derivatives is too high
• Verifying that SoC can support required SW applications– Increased software content to develop, integrate, & verify– SoC must be architected up front to support SW Use Cases– Must verify against functional, power & performance requirements
SoC/SW Integration Verification Vision
System Integration Automation
Application-Driven System Verification
Verification Planning & Management
System VIP SimulationVIP
AcceleratedVIP
SpeedBridge
VirtualBridge
Unified System Debugging
8 © 2012 Cadence Design Systems, Inc. All rights reserved.
System
Development
SuiteLinks to Post-silicon
Environment
9 © 2012 Cadence Design Systems, Inc. All rights reserved.