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    VHDL- A Hardware Discription Language

    Manish Kumar Jaiswal

    [email protected]

    Faculty MemberDepartment of Electronics Engineering

    ICFAI-Tech, Dehradun

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)

    VHDL- A Hardware Discription Language 1 / 34

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    Typical Design Flow

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)

    VHDL- A Hardware Discription Language 2 / 34

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    Design Abstraction Level

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)

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    Design Abstraction Level

    Lowest Level

    Transistor Level Design

    Next Upper Level

    Gate Level

    Next Higher Level

    RTL (Registre Transfer Logic) Level

    Highest Level

    Behaviour Level Design (wrtie a HDL program)

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 4 / 34

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    Design Abstraction Level

    Lowest Level

    Transistor Level Design

    Next Upper Level

    Gate Level

    Next Higher Level

    RTL (Registre Transfer Logic) Level

    Highest Level

    Behaviour Level Design (wrtie a HDL program)

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 4 / 34

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    Design Abstraction Level

    Lowest Level

    Transistor Level Design

    Next Upper Level

    Gate Level

    Next Higher Level

    RTL (Registre Transfer Logic) Level

    Highest Level

    Behaviour Level Design (wrtie a HDL program)

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 4 / 34

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    Design Abstraction Level

    Lowest Level

    Transistor Level Design

    Next Upper Level

    Gate Level

    Next Higher Level

    RTL (Registre Transfer Logic) Level

    Highest Level

    Behaviour Level Design (wrtie a HDL program)

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 4 / 34

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    Design Abstraction: Example of a MUX

    Behaviour Level

    do passes to y when s=0, andd1 passes to y when s=1

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 5 / 34

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    Design Abstraction: Example of a MUX

    Gate Level

    y = sdo + s d1

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 6 / 34

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    Design Abstraction: Example of a MUX

    Transistor Level

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 7 / 34

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    Introduction to VHDL

    VHDL Stands for:

    VHSIC-HDL (Very High Speed Integrated Circuit - Hardware

    Description Language)

    Jointly sponsored and developed by the U.S. Department of

    Defense and the IEEE (International Society for Electrical &Electronics Engineers) in the mid-1980s.

    Standardized by the IEEE in 1987 (VHDL-87), and later extended

    in 1993 (VHDL-93), and currently we have VHDL-2001.

    Verilog-HDL, Another very popular HDL, was first introduced in1984, and later in 1988, as a proprietary hardware description

    language by the two companies Synopsys and Cadence Design

    Systems. Currently we have Verilog-2001.

    In this course we will go through the VHDL.

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 8 / 34

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    Introduction to VHDL, Contd

    VHDL is similar to a regular computer programming language,

    such as C,C++. For exp, it has constructs for variable

    assignments, conditional statements, loops, functions, etc..

    In a computer programming language, a compiler is used to

    translate the high-level source code to machine code. In VHDL,however, a synthesizer is used to translate the source code to a

    description of the actual hardware circuit that implements the

    code. From this description, which we call a netlist, the actual

    physical digital device that realizes the source code can be made

    automatically.

    Functional and timing simulation of the code is also possible in

    order to test the correctness of the circuit.

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 9 / 34

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    Basic VHDL Structure

    Library IEEE;Use IEEE.std_logc_1164.all;

    entity entity_name is

    port{

    in1, in2 : in std_logic;

    out1 : out std_logic;};

    end entity_name;

    architecture arch_name of entity_name is

    - -signal-declaration

    begin

    - -concurrent-statement

    end arch_name;

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 10 / 34

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    Sample ExampleLibrary IEEE;

    Use IEEE.std_logc_1164.all;

    entity and_2 isport{

    in1, in2 : in std_logic;

    out1 : out std_logic;

    };

    end and_2;

    architecture dataflow_arch of and_2 isbegin

    out1

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    Basic Language Elements

    Comments

    - - - - - - This is a comment.

    Identifiers

    A sequence of one or more uppercase letters, lower case letters,digits and the underscore.

    Case insensitive

    First character must be a letter.

    The last character cannot be a underscore.

    Two underscore can not be together.

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 12 / 34

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    Basic Language Elements

    Data Objects: Signal , Variable, and constant

    SIGNAL represents logic signals on a wire in the ckt. A signal

    does not have memory, thus if source of the signal is removed, the

    signal will not have a value.

    A VARIABLE objects remember its content and is used for

    computation in a behaviour model. The scope of a VARIABLE islocal to the corresponding PROCESS.

    A CONSTANT object must be initialized with a value when

    declared and this value cannt be changed.

    Example

    SIGNAL x : BIT;

    VARIABLE y: INTEGER;

    CONSTANT one: std_logic_vector(3 downto 0) := "0001"

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 13 / 34

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    Basic Language Elements

    Data Objects: Signal , Variable, and constant

    SIGNAL represents logic signals on a wire in the ckt. A signal

    does not have memory, thus if source of the signal is removed, the

    signal will not have a value.

    A VARIABLE objects remember its content and is used for

    computation in a behaviour model. The scope of a VARIABLE islocal to the corresponding PROCESS.

    A CONSTANT object must be initialized with a value when

    declared and this value cannt be changed.

    Example

    SIGNAL x : BIT;

    VARIABLE y: INTEGER;

    CONSTANT one: std_logic_vector(3 downto 0) := "0001"

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 13 / 34

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    Basic Language Elements

    Data Types

    BIT & BIT_VECTOR (Predefined in VHDL. Can have Value 0 or

    1).

    STD_LOGIC & STD_LOGIC_VECTOR (Not Predefined n VHDL)

    Can have 9-value 0,1,Z,-,L,H,U,X,W.Need to add these lines.Library IEEE;Use IEEE.std_logic_1164.all;

    INTEGER (Predefined, Uses 32-bits to represents the binary

    numbers.)

    BOOLEAN (Predefined, having two value TRUE & FALSE)

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 14 / 34

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    Basic Language Elements

    Data Types

    Enumeration TYPE (Allow user to specify the values that the data

    can have)

    Syntax: TYPE identifier IS (value1, value2, ...);

    Example:TYPE state_type IS (S1, S2, S3);

    SIGNAL state: state_type;

    state

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    Basic Language Elements

    Data Types

    SUBTYPE (A subset of TYPE)

    Syntax: SUBTYPE identifier IS TYPE RANGE range;

    Example: SUBTYPE integer4 IS INTEGER RANGE -8 TO 7;

    SUBTYPE cell IS STD_LOGIC_VECTOR(3 downto 0);

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 16 / 34

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    Basic Language Elements

    Data Operators

    LOGICAL (AND, OR, NOT, NAND, NOR, XOR, XNOR)

    Arithmetic (a+b, a-b, a*b, a/b,a MOD b, a REM b, a**b,a&b(concatenation))

    Relational (=, /=, =)

    Shift (SLL(Shift left Logic), SRL, SLA(Shift Left Arithmetic), SRA,

    ROL(Rotate Left), ROR)

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 17 / 34

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    VHDL Terms

    Entity: Declares the external & users interface of the module.

    Architecture: Defines the actual implementation of the functionality of

    entity.

    Configuration: Used to bind a component instance to an

    entity-architecture pair.Package: Is a collection of commonly used data types and

    subprograms used in design.

    Generic: An information passed to ENTITY as a parameter, e.g for

    a generalised design.Process: A basic unit of execution. All operation that performs are

    broken into single or mutliple processes.

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 18 / 34

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    VHDL Terms

    ARCHITECTURE

    Syntax(Data Flow Model)

    architecture arch_name of entity_name is

    signal declaration;

    begin

    concurrent statements;end arch_name;

    Example

    architecture data_arch of module is

    signal t1: std_logic;

    begint1

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    VHDL Terms

    ARCHITECTURE

    Syntax(Behavioural Model)

    architecture arch_name of entity_name is

    signal declaration;

    function declaration;

    procedure declaration;

    begin

    PROCESS-blocks;

    concurrents statements;end arch_name;

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 21 / 34

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    VHDL Terms

    ARCHITECTURE

    Example(Behavioural Model)

    architecture behav_arch of module is

    signal t1: std_logic;

    begin

    PROCESS(M,N,O)

    BEGIN t1

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    VHDL Terms

    ARCHITECTURE

    Syntax(Structural Model)

    architecture arch_name of entity_name is

    signal declaration;component declaration;

    begin

    instance-name: PORT MAP-statement;

    concurrents statements;

    end arch_name;

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 23 / 34

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    VHDL Terms

    ARCHITECTURE

    Example(Structural Model)

    architecture struct_arch of module is

    COMPONENT OR2 {

    in1, in2: in std_logic; out1: out std_logic };end COMPONENT

    signal t1: std_logic;

    begin

    U0: OR2 PORT MAP (M, O, t1);

    S

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    VHDL Terms

    GENERIC

    Syntaxentity entity_name is

    GENERIC (identifier: type); - - no default value

    GENERIC (identifier: type:=constant); - - with default value

    port { - -list of port names and types;

    };

    end entity_name;

    Example

    entity adder is

    GENERIC (n: integer:=4); - - with default value of 4port { A,B: in std_logic_vector(n-1 downto 0);

    Sum: out std_logic_vector(n-1 downto 0);

    Cout: out std_logic };

    end adder;

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 25 / 34

    VHDL T

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    VHDL Terms

    GENERIC

    Component Declaration Syntax

    COMPONENT entity_name

    GENERIC (identifier: type:=constant); - - with an optional valuegiven by the constant

    port { - -list of port names and types;

    };

    end COMPONENT;

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 26 / 34

    VHDL T

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    VHDL Terms

    PACKAGE

    A PACKAGE provides a mechanism to group together and share

    declarations that are used by several entity units.

    A package itself includes a declaration and, optionally, a body.

    The PACKAGE declaration and body usually are stored together

    in a separate file from the rest of the design units.

    The file name given for this file must be the same as the package

    name.

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 27 / 34

    VHDL T

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    VHDL Terms

    PACKAGE Declaration Syntax

    PACKAGE package-name is

    type-declarations;

    subtype-declarations;

    signal-declarations;variable-declarations;

    constant-declarations;

    component-declarations;

    function-declarations;

    procedure-declarations;END package-name;

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 28 / 34

    VHDL T m

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    VHDL Terms

    PACKAGE BODY Declaration Syntax

    PACKAGE BODY package-name is

    function-definitions; - - For the function declared in packagedeclaration

    procedure-definitions; - - For the procedure declared in package

    declaration

    END package-name;

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 29 / 34

    VHDL Terms

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    VHDL Terms

    PACKAGE Example

    LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE my_package ISSUBTYPE bit4 IS STD_LOGIC_VECTOR(3 DOWNTO 0);FUNCTION Shiftright (input: IN bit4) RETURN bit4; declare a functionSIGNAL mysignal: bit4; a global signalEND my_package;PACKAGE BODY my_package IS implementation of the Shiftright functionFUNCTION Shiftright (input: IN bit4) RETURN bit4 IS

    BEGINRETURN 0 & input(3 DOWNTO 1);END shiftright;END my_package;

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 30 / 34

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    References

    References

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    References

    [1] VHDL Primer by J. Bhasker.

    [2] VHDL Programing by Example by Douglas L. Perry, TMH

    Publcation.

    [3] Digital Logic and Microprocessor Design with VHDL by Enough

    O. Hwang.

    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 32 / 34

    Thank you

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    M. K. Jaiswal [email protected] (Faculty Member Department of Electronics Engineering ICFAI-Tech, Dehradun)VHDL- A Hardware Discription Language 33 / 34