Dec.20l4l Jan.zDll Logic Design

USN

'Fime: 3 hrs.,'l

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5a.

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6a.

(06 Marks)

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(05 Marks)

(10 Marks)

(10 Marks)(06 Marks)

Third Semester B.E. Degree Examination, Dec.20l4l Jan.zDllLogic Design

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Note: Answer FIVE fuII qaestions, selectingst least Tl'yO questions from each part.

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PART _ A:..:.:

a. Whaf fl1d universal gates? Realize,-\(e + n). (o.

") using only universal gates.

,,:";,,',., (05 Marks)b. Discuss 1ftstpgsitive and negative logic and list the equivalences in positive and negative

logic. (05 Ntarks)c. An asymmetrical signal waveform is high for 2 m s€c and low for 3 m sec. Find

i) Frequency ii) Period iii) Duty cycle low iv) Duty cycle high. (05 Marks)d. Explain the structure of V.,tlOL / Verilog program.,ii,':

a. The system has four inputs, the output will be.high only when the majority of the inputs arehigh. Find the following :

i) Give the truth table and simplify by,gsing K-map.ii) Booleanexpressionin I* und,ftM form.

iii) Implement the simplified equation using NAND - NAND gates and NOR - NOR gates.(10 Marks)

b. Find essential prime implicants for the Boolean expression by using Quine - Mc Cluskymethod.

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fl A. g. C, D) : I m( I , 3, 6, 7,9. 10. 12, 13, 14, l5).

Implement the.Boolean function expressed by SOP : ,,. ':.

f(A,B,C,n) =)m (1, 2, 5, 6, g, l2)using 8 - to - 1 MUX.

Implement a,full adder using a 3 - to - 8 decoder.n"ii*"i-=' r.g*;r decoder using PLA.

Give state transition diagram of SR, D, JK and T Flip - Flop.'$fith a neat logic diagram and truth table, expluin th. workingFlip - Flop along with its implementation using NAND gates.Show how a D Flip - Flop can be convefted into JK Flip - Flop.

PART _ BWith a neat logic and timing diagram, explain the working of a 4-bit SISO register.

Design two 4-bit serial Adder.Write the verilog code for switched tail counter using "assign" and "always" statement.

(04 Marks)

Design synchronous mod-5 UP counter using JK Flip-Flop. (10 Marks)Explain a 3-bit binary Ripple down counter, give the block diagram, truth table and outputwaveforms. (10 Marks)

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7 a. With a neat block diagram, explain Mealay and Moore model. (10 Marks)b. Design an asynchronous sequential logic circuit for state transition diagram shown in

Fig. Q7 (b). (10 Marks)

-dr #.* r'16. V/ \u., 4rf"4Ss-= *..[\8 a. Exp@he R/2R Ladder technique of D/A conversion. tu-T,.,F', (10 Marks)

b. ExplaiffffiSpeat diagram, single slope A/D converters. '..fl=. u (10 Marks)

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Fig. Q7 (b)

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Dec.20l4l Jan.zDll Logic Design