Death of Logic Synthesis

SISPD Talk

Copyright 2004 MUSIC

Death of Logic Synthesis

Rajeev Madhavan

Magma Design Automation

Logic

Synthesis

1985-2005

SISPD Talk


The Fastest Path from RTL to Silicon

The following discussion contains forward-looking statements, and our actual results may differ materially from those discussed here.

Additional information concerning factors that could cause such a difference can be found in Magma’s Annual Report on Form 10-K for the year ended March 31, 2003. Forward-looking statements speak only as of the earlier of the date first published or the date hereof. Magma disclaims any obligation to update forward-looking statements.

3Copyright 2004 MAGMA

Design Starts by Geometry: Trend during economic Recession

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

2000 2001 2002 2003 2004 2005 2006 2007

>0.350.350.250.180.150.1390<90

• 0.18 micron is now mainstream technology.

• Most leading-edge designs targeted for 0.13 micron.

• Today 0.13 micron is fast becoming mainstream.

• Leading design teams now preparing for 90nm.

Source: IBS ’03


Traditional design flows will make Moore’s law economically infeasible

Challenges of SoC Designs at 90nm and 65nm

• 100M+ gate designs −18mm X 18mm, 2000 I/Os, 500Mhz

−Approximately 10M lines of RTL

• 80+ engineers−Experts in synthesis, P&R, signal integrity, power analysis,

design closure

• $80M investment−Requires $160M in 2 years to realize break even

−Where is the killer application for this??


Smaller Geometries= Higher Cost

Source: IBS Inc.

Wireless chip case

Networking chip case

0.18um 0.13um 90nm

10

20

30

40

50

0.15

Total Product Cost ($M)

Engineering Cost – 60% upManufacturing Cost – 40% upNRE/Mask Cost – 100% up

for each generation

ProductCost

$30M ~ $50M @ 90nm


We (EDA industry) give you the pieces …. You assemble it …

AssistanceAutomation

Electronic Design

ROI is essential to justify Silicon UsageReflects on State of the EDA industry


Synthesis History - Logic Optimization -> Infancy

• Logic Optimization −A lot of research in 1980’s−Birth of MIS/SIS and other

optimizers

• Companies were formed−RTL compilation followed−Mapper, buffering, sizing …

lots of interesting work

• Layout Engineers−APR had been automated −Fully done … boring …

layout engineers


Synthesis – Middle age crisis

• Around 1995−Capacity 10K gates, 3K cells

per block

−Manual time budgeting

−Thousands of lines of scripts

−Difficult to work with timing exceptions, latch based design

−Wireload models


1990’s Internet Boom Mantra - Time-to-Market

1 MillionUnits

5 10 15 20

B&W TVCable TV

Color TVVCR

PCCellular

PCSDVB

DVD

# UnitsSold

YearsSource: D. Merriman, “Wireless Communications Report,” BIS, 1995 + Dataquest

Time to 1 Million Units Sold


90’s - Customer Requirements – The Boom Days

• Unrelenting push for better size, speed, quality & cost.

Large, Complex Designs

Rapid Time To Market

High-Quality Designs

1995 – .35 & 2M gates 2001 – .13 & 100M gates

PC – 7 years to 1M unitsPlayStation – 3 days to 1M units

ReliabilityManufacturability


Synthesis – Middle age break through

• In 1996, product introductions included:− Capacity stretched to 100K gates

− Time budgeting introduced

− Distributed processing added

− Delay still based on random wireload models

• More new companies formed− Ambit Design Systems


Ingredients For a Successful Startup

• Right Technology

• Right Place

• Right Time


Startup #1 – Synthesis Technology - Ambit

• Founded: 1994

• Funding: $150K seed commitment - $135K.

• Product: Logic Synthesis - V1.0 November 1996.


Ambit – Business Proposition

Logic design was slow as tools was very slow and had limited capacity

Chip sizes were much bigger than logic design tools

Logical Physical

(layout)

Timing (netlist)

Logical


Ambit: Tracing the Dark Alleys!

Founded with $135K

1994Impossible to raise funding – attempt side product DFT

~ $500K (30+investors)

1995 Imminent ShutdownBridge loans(mortgages)Cadence/LSI

1996 Excess financing Problem

$4M … SGI, SUN, Chromatic

1997

Benchmark showing great results after

logic design- but bad layout results!

1997/98


Traditional Flow• No physical knowledge in synthesis

• Synthesis netlist unimplementable

• Partitioning and budgeting for synthesis only

• Timing from synthesis unachievable in layout

The only answer: Iterate

frozen sizes frozen netlist

frozen placement

Logic Synthesis

Placer

Router

Optimization

PDEFPDEFSDFSDFRCRC

manualmanualhackinghacking

Extractor


Ambit: Acquired in 1998!

Founded with $135K

1994Impossible to raise funding – attempt side product DFT

~ $500K (30+investors)

1995 Imminent ShutdownBridge loans(mortgages)Cadence/LSI

1996 Excess financing Problem

$4M … SGI, SUN, Chromatic

1997Acquired by Cadence

1998

Benchmark showing great netlist results, bad layout results!

1997/98


Ingredients For a Successful Startup

• Right Technology

• Right Place

• Right Time


Synthesis History – Old Age ….

• Physical Synthesis Evolution− Logic Optimization and

Placement combined

− Some used wireload

− Others used fixed timing

• New Companies Formed− Fixed timing gave larger

capacity


Design Flow Getting Obsolete Quickly

Masks

CONVENTIONAL PHYSICAL DESIGN SYSTEM FLOW

Logic Design Physical Design(synthesis) (place & route)

Tape-Out

Control the iterations from increasingControl the iterations from increasing

Wireload Based Physical synthesis – patch Wireload Based Physical synthesis – patch work for better wire delay estimation startedwork for better wire delay estimation started

Cost and complexity increasingCost and complexity increasing

Timing Closure Iterations


Key Benefits of FixedTiming – Closer Integration

Timing convergence iterations

TimingClosure

Masks

EXISTING SYSTEMSPhysical Design

Design Cycle Time (months)

Tape out

Logic Design

Wireload based flows

TimingClosure

MasksPhysical Design

Tape out

Wireload Synthesis

Fixed TimingMasksPhysical DesignWireload Synthesis

Tape outPredictable Handoff


EDA reaped change to physical synthesis

Netlist

Foundry

Silicon Design Team

Masks

Physical SynthesisPhysical DesignLogic Design

Tape out

Block ESP Timing

Sign-off


On going success criteria …

• Lower cost of manufacturing− Better performance on timing, area, SI and power

• Shorter turnaround time (TAT) by 50% to 90%− Predictability – early feedback on achievable performance

• Lower design cost by 30% to 50%− More gates per engineer, fewer licenses, shorter TAT

Stand alone logic synthesis plays insignificant roleAny capacity can now be synthesized flat ….


Maximizing Yield For a given process• DRs cannot capture all

manufacturability issues− The number and complexity of

DRs are exploding

• OPC is by no means DFM− OPC is done after design is

completed (post-layout)

− Getting more difficult to correct post-layout

• Little is done during design− Fixing yield disturbs timing,

area, power ……

− Anything during synthesis, placement, routing?

YieldIssues

YieldIssues

Logic

Synthesis

Logic

Synthesis

Physical

Synthesis

Physical

Synthesis

RoutingRouting

Design Verificati

on

Design Verificati

on

MaskMask

RET (OPC)RET

(OPC)

ProcessProcess

Design RulesDesign Rules

??

More Complexities during tail end


Statistical Design vs. Worst Case Design

StatisticalDesign

Optimization

slack0

Yield loss

“Put elephant diet” – The low carb way! Changes at Routing Stage

Deep Nanometer Mandates Design Paradigm Shift


Design Imperatives

Physical SynthesisIntegrated RTL-GDSII system

1990s 1999 2001 2003 2005

.25u+ 0.18u 0.13u 0.09u 65nm

• Wire delay dominates cell delay• Wireload model based synthesis breaks down• Need logic synthesis integrated with placement

Signal Integrity / CrosstalkNeed integrated router

On chip variations (OCV)Need integrated clock synthesis

Severe crosstalk, OCV problems50M+ gate designsHundreds of macrosYield/manufacturability problems

Place &Route

LogicSynthesis

InterConnect Synthesis


Fate of Logic Synthesis

• Almost all optimizations are migrating downstream

• Decisions can only be made further down the chain

• Other EDA pieces will follow−Signoff in the loop!

Resistance is futile. You will be (have been) assimilated


Customer Problem/Solution/Value Proposition

RTL

GDSII

ImplementationSystem

SignoffSystem

RTL

GDSII

Implementation+ Signoff

Older SystemsOlder Systems New ApproachNew Approach

Customer Wish

• Customer Problem: Flows aren’t correct-by-construction, costing productivity

• Historic EDA Problem: Ship tools for revenue – not productivity!!!

• Value Proposition: Deliver a correct-by-construction flow, and provide engines for signoff - making signoff to a checklist activity”

“Signoffin theLoop”

SISPD Talk



You will be

Remembered …

…….

……….

……………

1985-2005


Contributions from Logic Synthesis Technology

• RTL Compilation−Language support for Verilog and VHDL

−Pragmas, templates …

−Poor quality of logic generated will result in poor results

• Technology Mapping

• Logic Structuring/re-structuring

• Data Path Compiler−Standard operators

−Good architectures assist in good QOR


IC Silicon Platform Alternatives

• Design platform solutions to all IC Silicon alternatives− Specifically SOC’s that combine different architectures

• Business models based on extended IP sales need to evolve

Unified EDA Flow

FPGA

Standard Cell

StructuredASIC

Create

Fusion

Blast Architecture

Create-SA

Structured ASIC - BE

Perf

orm

an

ce /

Den

sit

y

Design Cost / NRE

Tu

rn-A

rou

nd

/Fle

xib

ilit

y

FPGA


Silicon Design Cost Reduction … Re-thinking ...

Source: IBS Inc.

Wireless chip case

Networking chip case

0.18um 0.13um 90nm

10

20

30

40

50

0.15

Total Product Cost ($M)

Engineering Cost – 60% upManufacturing Cost – 40% upNRE/Mask Cost – 100% up

for each generation

ProductCost

$30M ~ $50M @ 90nm


Integrated Approach for High-Complexity Designs

Electronic Design Assistance

VLSI COMPILER

RTLGoals

GDS II

Si CompilerDesign ClosureGates/Engineer

Pro

cess

, Lib

rary

Automated Approach for High-Complexity Designs

PR

OT

OT

YP

EP

RO

TO

TY

PE

FloorplanFloorplan

GDSII

Physical Synthesis

Clock Tree Synthesis

SI-Driven Routing

BackendBackend

RTL

RTL Synthesis

DFT Analysis

Frontend Frontend

Physical Synthesis

TIM

ING

, P

OW

ER

, N

OIS

ET

IMIN

G,

PO

WE

R,

NO

ISE

Electronic Design Automation


The TALL THIN VLSI ENGINEER for 65nm

• There is no front end engineer, no DFT engineer, no backend engineer, no extraction/analysis ….

• Engineers built along design domains – for now− Digital, Analog and RF

VLSI COMPILER

RTLGoals

GDS II

Si CompilerDesign Closure

Pro

cess

, Lib

rary

SISPD Talk



You will be

Remembered …

RTL

Datapath

Tech Mapping

Support platforms

Optimization Algorithms

1985-2005

Documents

Death of Logic Synthesis