De Lab Viva Questions 1

8/12/2019 De Lab Viva Questions 1

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DE LAB VIVA QUESTIONS

Q.1 The NAND gate output will be low if the two inputs are

(A) 0,0 (B) 0,1(C) 1,0 (D) 1,1

Ans: D

Q.2 What is the binary equivalent of the decimal number !" (A)

101110000 (B) 110110000 (C)111010000 (D) 111100000

Ans: A

Q.3 The decimal equivalent of he# number 1A$ is

(A) !%& (B) !%&

(C) !&% (D) !%&

Ans: B

Q.4 (%')" = ( )1!(A) ( 1 D (B) D ( 1(C) 1 ( D (D) 1 D (

Ans: D

)%'*" + )1 D (*1!

Q.5 The simplification of the oolean e#pression (A()+(A()is(A) 0 (B) 1(C) A (D) (

Ans: B

The oolean e#pression is (ABC)+ (ABC)is equivalent to 1(ABC)- (ABC)= A-B -C -A-B -C + A -B - ( - A - - C

+ )A-A*)-B *)(-C * + 1.1.1 + 1

Q.6 The number of control lines for a " / to / 1 multiple#er is(A) (B)

(C) ' (D) $

Ans: B

Q.7 ow many 2lip32lops are required for mod/1! counter4(A) $ (B) !

(C) (D) '


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Ans: D

Q.8 56789 contents can be erased by e#posing it to

(A) :ltraviolet rays; (B)


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Q.14 Data can be changed from special code to temporal code by using(A) hift registers (B) counters

(C) (ombinational circuits (D) ABD converters;

Ans: AData can be changed from special code to temporal code by using hift 7egisters;

)A 7egister in which data gets shifted towards left or right when clocC

pulses are applied is Cnown as a hift 7egister;*

Q.15 A ring counter consisting of five 2lip32lops will have

(A) $ states (B) 10 states(C) states (D) s complement of the number 1101101 is

(A) 0101110 (B) 0111110(C) 0110010 (D) 0010011

Ans: D

Q.18 The correction to be applied in decimal adder to the generated sum is(A) 00101 (B) 00110

(C) 01101 (D) 01010

Ans: BThe correction to be applied in decimal adder to the generated sum is 00110;

When the four bit sum is more than & then the sum is invalid;


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Q.21 The code where all successive numbers differ from their preceding number by single bit is

(A) inary code; (B) (D;

(C) 5#cess / ; (D) ?ray;

Ans: D

)?ray is an unweighted code; The most important characteristic of this code is

that only a singlebitchangeoccurs when going from one code number to ne#t;*

Q.22 3" is equal to signed binary number

(A) 10001000 (B) 00001000

(C) 10000000 (D) 11000000

Ans: A3 " is equal to signed binary number 10001000

Q.23 De9organ>s first theorem shows the equivalence of

(A) 87 gate and 5#clusive 87gate; (B)N87 gate and ubbled

AND gate; (C)N87 gateand

NAND gate;(D)NAND gate and N8T gate

Ans: B

Q.24 The device which changes from serial data to paralleldata is (A) (8:NT57 (B)

9:@T


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Q.27 The following switching functions are to be implemented using a DecoderH

f1 = I m(1, , ',",10,1') f + I m), $, &,11*

f + I m), ', $, !, %*

The minimum configuration of the decoder should be

(A) / to / ' line; (B) / to / " line;(C) ' / to / 1! line; (D) $ / to / line;

Ans: C

Q.28 The decimal equivalent of inary number 11010 is

(A) ! (B) !; (C) 1!; (D) ;

Ans: A

Q.2 1>s complement representation of decimal number of 31% by using " bit representation is(A) 1110 1110 (B) 1101 1101

(C) 1100 1100 (D) 0001 0001

Ans: A

Q.3! The e#cess code of decimal number ! is(A) 0100 1001 (B) 01011001

(C) 1000 1001 (D) 01001101

Ans: B

Q.31 ow many AND gates are required to realie J + (D-52-?

(A) ' (B) $

(C) (D)

Ans: D

Q.32 ow many select lines will a 1! to 1 multiple#er will have

(A) ' (B) (C) $ (D) 1

Ans: A

Q.33 ow many flip flops are required to construct a decade counter

(A) 10 (B) (C) ' (D)

Ans: C

Decade counter counts 10 states from 0 to & ) i;e; from 0000 to 1001 *

Thus four 2lip2lopKs are required;


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Q.34 The he#adecimal number for (&$;$)10(A) ($2;")1!(C) (5;2)1!

is

(B) (&A;)1!(D) ($A;')1!

Ans: A

Q.35 The octal equivalent of ('%)10 is

(A) ($)" (B) ($0)"(C) (!%)" (D) ('00)"

Ans: C

Q.36


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Q.54 The commercially available "3input multiple#er integrated circuit in the TT@ family is(A) %'&$; (B) %'1$;

(C) %'1$'; (D) %'1$1;

Ans: B

Q.56 The 9< chip %'%' is

(A) Dual edge triggered EF flip3flop )TT@*;

(B) Dual edge triggered D flip3flop )(98*;(C) Dual edge triggered D flip3flop )TT@*;

(D) Dual edge triggered EF flip3flop )(98*;

Ans: C

Q.5 When the set of input data to an even parity generator is 0111, the output will be(A) 1 (B) 0

(C) :npredictable (D) Depends on the previous input

Ans: B

Q.6! The number 1'0 in octal is equivalent to

(A) (&!)10; (B) ("!)10;(C) (&0)10; (D) none of these;

Ans: A

Q.61 The N87 gate output will be low if the two inputs are

(A) 0,0 (B) 0,1

(C) 1,0 (D) 1,1

Ans: B" C" #$ D

Q.62 Which of the following is the fastest logic4

(A) 5(@ (B) TT@(C) (98 (D) @s complement subtraction of (%)10 (11)10 ; (4)

Ans:>s (omplements ubtraction of )%*10/ )11*102irst convert the decimal numbers % and 11 to its binary equivalents;

)%*10 + )0111*)11*10 + )1011* in '3bit system

Then find out the >s complement for 1011 i;e;,

1>s (omplement of 1011 is 0100

>s (omplement of 1011 is 0101o, )%*10/ )11*10 + 0111

0101

3333333331100

333333333

1


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D E ! DI % I T A L S ELE C T & O NICS

ince there is no carry over flow occurring in the summation, the result is a negative

number, to find out its magnitude, >s (omplement of the result must be found;

>s (omplement of 1100 is 00111

33333333

0100

33333333ere the answer is )3'*10 )or* in >s complement it is 1100;

Q.4 What is the ?ray equivalent of ($)10

; (2)

Ans:?ray equivalent of )$*10The binary equivalent of Decimal number $ is )00100101*

1; The left most bit )9* in gray code is the same as the left most in binary

; Add the left most bit to the adQacent bit

; Add the ne#t adQacent pair and so on;, Discard if we get a carry;0 - 0 - 1 - 0 - 0 - 1 - 0 - 1

0 0 1 1 0 1 1 1 ?ray Number

Q.5 5valuate # + A.+ ((A.D)using the convention A + True and + 2alse; (4)

Ans:

5valuate # +A; - C(A;D)+ A - ( )A-D *)ince

+A. - ( .A - (. D

A;D + A - D by using Demorgan>s @aw*

y using the given convention, A + True + 1R + 2alse + 0

+1.0 - (;1- (;D + 0 - 0 - (;D + (;D

Q.6 implify the oolean e#pression 2 + () - (*)A - - (*; (6)

Ans:

implify the oolean 5#pression 2 + ( ) -(* )A--(*

2 + ( )-(* )A--(*+ ( - (( M)A--(*+ ( - ( M)A--(* )G (( + (*

+ (A - ( - (( - (A - ( - ((

+ A( - ( - ( - (A - ( - (( )G ( +( O (( + (*+ A( - ( - (A - ( )G (-(-( + (R (( + (*

+ A( - ( - ( )1-A*

+ A( - ( - ( )G 1-A + 1*

+ A( - ( )1-*


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D E ! D I % IT A L S ELE C T & O N I CS

+ A( - ( )G 1- + 1*

+ ( )1-A* + ( SG )1-A*+1

Q.7 implify the following e#pression into sum of products using Farnaugh map

2)A, , (, D* = I

)1,,',$,!,%,&,1,1*

(7)

Ans:implification of the following e#pression into sum of products using Farnaugh

9apH

2)A,,(,D* + )1,,',$,!,%,&,1,1*

Farnaugh 9ap for the e#pression 2)A,,(,D* + )1,,',$,!,%,&,1,1*is shown in 2ig;')a*; The grouping of cells is also shown in the 2igure;

The equations for )1* is AR )* is C DR )* is ADR )'* is C

ence, the implified 5#pression for the above Farnaugh map is

2)A,,(,D* + A-C D-AD-C

+ A) - D* -C ) - D*

Q.8 implify and draw the logic diagram for the given e#pression

2 = A( + A( + A( + A( + A( ; (7)

Ans:

implification of the logic e#pression

2 + ABC -AB ( - AC - ABC - AB

( 2 +ABC -AB ( - AC - ABC - A

B (


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2 + A-B -C - )A-B *( -AC - A )B -C * - AB

(

)G ABC + A-B -C and AB + A-B by using Demorgan>s @aw*

+ A-B -C -A( -B ( - AC - AB - AC - AB (

+A-A(-B -B ( -C - AC -AC -AB - AB (

+ A)1-(*-B )1 - (* -C )1 - A* - AC - AB - AB (

+ A-B -C -AC - AB - AB ( SG )1-(* + 1 and )1-A* + 1

+ )A - AB * -B )1 - A(* -C )1-A*

+ )A-B *-B -C SG )A - AB * + )A-B *R )1-A(* + 1 and )1-A*

+1 2 + )A-B -C *)G B -B +B *

The logic diagram for the simplified e#pression 2 + )A-B -C * is given in fig;$)a*

_

AA

_

B _ _ _B F = A +B+

C

_

CC

,.5(0) L#, ,0$0 -#$ /9 ;$ss,#n = (A+B +C )

Q. Determine the binary numbers represented by the following decimal numbers; (6)

)i* $;$ )ii* 10;!$ )iiii* 0;!"%$

Ans:

(,) C#n*$s,#n #- ,0 n$ 25.5 ,n/# ,n0$ n$:ere integer part is $ and fractional part is 0;$; 2irst convert the integer part $ into its

equivalent binary number i;e;, divide $ by till the quotient becomes 0 shown in table)a*

Guotient 7emainder

$

1 1

1

! 0

!

0

1 1

1

0 1

T0 2(0)

'


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o, integer part )$*10 is equivalent to the binary number 11001; Ne#t convert

fractional part 0;$ into binary form i;e;, multiply the fractional part 0;$ by till you get

remainder as 00;$

.

333333

1;0 7emainder

1 )Guotient*The decimal fractional part 0;$ is equivalent to binary number 0;1; ence, the

decimal number $;$ is equal to the binary number 11001;1

(,,) C#n*$s,#n #- ,0 n$ 1!.625 ,n/# ,n0$ n$:ere integer part is 10 and fractional part is 0;!$; 2irst convert the decimal number 10

into its equivalent binary number i;e;, divide 10 by till the quotient becomes 0shown in table )b*

Guotient 7emainder

10

$ 0

$

1

1 0

1

0 1

T0 2()

o, the integer part 10 is equal to binary number 1010; Ne#t convert the decimalfractional part 0;!$ into its binary form i;e;, multiply 0;!$ by till the

remainder becomes 0

0;!$ 0;$0 0;$0. . .

3333333 33333333 3333333

1;$0 0;$0 1;0 )7emainder*

1 0 1 )Guotient*

o, the decimal fractional part 0;!$ is equal to binary number 0;101; ence the

decimal number 1!.625 is equal to binary number 1!1!.1!1;

(,,,)C#n*$s,#n #- -$0/,#n0 n$ !.6875 ,n/# ,/s


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0;!"%$ 0;%$0 0;%$ 0;$

. . . .

1;%$0 0;%$ 1;$ 1;0 )7emainder*

1 0 1 1 )Guotient*

o, the decimal fractional number !.6875 is equal to binary number !.1!11;

Q.1! 6erform the following subtractions using >s complement method; (8))i* 01000 / 01001 )ii* 01100 / 00011 )iii* 0011;1001 / 0001;1110

Ans:(,) S/$0/,#n #- !1!!!!1!!1: 1>s complement of 01001 is 10110 and >s

complement is10110- 1 +10111; ence

01000 + 01000

3 01001 + -10111 )Ks complement*3333333333333333333333333

11111 )ummation*3333333333333333333333333

ince the 9 of the sum is 1, which means the result is negative and it is in Ks

complement form; o, Ks complement of 1111 +00001+ )1*10; Therefore, the result is / 1;

(,,) S/$0/,#n #- !11!!!!!11: 1>s complement of 00011 is 11100 and >s complement

is 11100 - 1 + 11101; ence

01100 + 01100

/ 00011 + - 11101 )Ks complement*

333333333333333333333333333333333333333333333333331 01001 + - &

s complement is 1110;0010;

0011;1001 + 0011;10013 0001;1110 + - 1110;1011 )>s complement*

3333333333333333333333333333333333333333333

1 0001;101< + - 1 ;!"!$


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+ A( - A - (A - (A

+ A()1 - * - A)1 - (*

%


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+ A( - A Secause )1 - * + 1 and )1 - (* +1

(,,,) .J - XZ - .Y U ).J - U*

= .J - XZ - .Y U ).J - U*

+ .J - XZ - ..JY U - .Y U U

+ .J - XZ - .Y U )ecause JY + 0 O UU + U*

+ .J - X - Z - .Y U )ecause XZ + X - Z *

+X - .J - Z - .Y U

=X - . )J -Y U* - Z

=X - . )J -U* - Z )ecause J -Y U + J -U*

=X - . J )U-Z * - .U - Z )ecause U-Z +1*

=X - . J U - .JZ - .U - Z

=X - .U )1- J* - Z )1-.J*

+X - .U - Z )ecause 1- J + 1 O1-.J + 1*

+X - .U* - Z

+)X - U* - Z )ecause X - .U + X - U+X -) U - Z *

+X -1 )ecause U - Z + 1*

+1 )ecause X -1 + 1*

Q.12 9inimie the logic function J(A" " (" D) = I m(0"1"""$"%"""&"11"1') ; :se Farnaugh map;

Draw logic circuit for the simplified function; ()

Ans:

2ig; ')a* shows the Farnaugh map; ince the e#pression has ' variables, the

maphas 1! cells; The digit 1 has been written in the cells having a term in the given

e#pression; The decimal number has been added as subscript to indicate the

binary number for the concerned cell; The term ABC D cannot be combined with

any other

cell; o this term will appear as such in the final e#pression; There are four

groupings of ' cells each; These correspond to the min terms )0, 1, , *, )0, 1, ", &*,

)1, ,$,%* and )1, , &, 11*; These are shown in the map; ince all the terms )e#cept

1'* have been included in groups of ' cells, there is no need to form groups of two

cells;


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"


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The simplified e#pression is Y )A,B,(,D) +ABC D -A B -B C -B D-A

D 2ig;' )b* shows the logic diagram for the simplified e#pression

Y )A,B, (, D) +ABC D -A B -B C -B D-AD

A B C D

_

A B C

D

_ _

A B

_

A D Y

_ _

B C

_

B D

,.4() L#, ,0$0 -#$ >

Q.13 implify the given e#pression to its um of 6roducts )86* form; Draw the logic circuit

for the simplified 86 function J = (A+ )(A+ A)(+ A(+()+A+A(

(5)

Ans:

implification of given e#pression

J + )A - * )A - AB * ( - A) - C * - A - A(

in some of products )86* formH3


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&


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J + )A - * )A - AB * ( - A) - C * - A - A(

+)A - * )A - AB * ( - A) - C * - A - A(

+)A - * )A - A-B *( - A) - C * - A - A(

+)A - * )1-B *( - A) - C * - A - A( )ecause A - A + 1*

+ )A - * )(-B (* - A - A C - A - A(

+ )A - * )(-B (* - A - A C - A - A(

+A( - AB ( - ( - B ( - A - A C - A - A(

+ A( - A()B - * - ( - 0 - A - A C - A )ecause B + 0*

+ A( - A(- (- A - A C )ecause B - + 1*

+ A(- (- A - A C )ecause A( - A( + A(*

+ ( )A- * - A) - C *

A B C

C

A + B

C (A + B)

Y_

A _ _

A(B +C)

B_

B +C_

C

,.4() S,;,-, L#, C,$,/

Q.14 Design a " to 1 multiple#er by using the four variable function given by

2(A" " (" D) = I m(0"1""'"""&"1$) ; (1!)

Ans:D s, n #- 8 /# 1 / ,; $: This is a four3variable function and therefore we need a

multiple#er with three selection lines and eight inputs; We choose to apply variables B,

(, and D to the selection lines; This is shown inTable ";1; The first half of the mintermsare associated withA' and the second half withA. y circling the minterms of the function

and applying the rules for finding values for the multiple#er inputs, the implementation

shown in Table;";;The given function can be implemented with a "3to31 multiple#er as shown in fig;")a*;Three of the variables, , ( and D are applied to the selection lines in that order i;e;, is

connected to s, ( to s1 and D to s0; The inputs of the multiple#er are 0, 1, A and A>;

When (D + 000,001 O 111 output 2 + 1since , >, (> andm& + A> > ( produce a 1 output; When (D + 010, 101 and 110, output 2 + 0, since

0


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,n/$ A B C D

0 0 0 0 0 1

1 0 0 0 1 1

0 0 1 0 0

0 0 1 1 1

' 0 1 0 0 1

$ 0 1 0 1 0! 0 1 1 0 0

% 0 1 1 1 0

" 1 0 0 0 1

& 1 0 0 1 1

10 1 0 1 0 0

11 1 0 1 1 0

1 1 1 0 0 0

1 1 1 0 1 0

1' 1 1 1 0 0

1$ 1 1 1 1 1T0 .8.1 T$/9 T0 -#$ 81 /,;$

T0 8.2 I;n/0/,#n T0 -#$ 8 /# 1 U?

1


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1 I0

I1

0 I2

I3

8 X 1Y F

MUXI4

I5

I6

S S SA

I7 2 1 0

B

C

D

,.8(0) L#, ,$,/ -#$ 8/#1 /,;$

Q.15 (onvert the decimal number ";!% to its binary, he#adecimal and octal equivalents; (6)

Ans:

(,)C#n*$s,#n #- D,0 n$ 82.67 /# ,/s B,n0$ E


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Now taCing the fractional part i;e;, 0;!%

2raction 2raction . 7emainder

New

2raction


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1!

" 7emainder 33333 0 )@*

' 7emainder 33333 0

7emainder 33333 0

1 7emainder 3333330

0 7emainder 33333 1)9*


Ans:

A,/,#n #- 2! 0n (15) s,n 2s C#;n/:

0

10 7emainder 33333 0 )@*

$ 7emainder 33333 0

7emainder 33333 1

1 7emainder 3333330

0 7emainder 33333 1)9*

)0*10 + 1 0 1 0 0 )1!*10 + 1 0 0 0 0

)31!*10 + 0 1 1 1 1)1>s (omplement*

-1)>s (omplement*333333333333333333333

1 0 0 0 0

333333333333333333333Therefore, 0 + 1 0 1 0 0

31! + 1 0 0 0 0

33333333333333333333333333333

1 0 0 1 0 0

)Neglect*

33333333333333333333333333333333ince the 9 of the sum is 0, which means /9 $s/ ,s ;#s,/,* ,. +4

Q.17 Add !'" and '"% in (D code; (4)

Ans:

A,/,#n #- 648 0n 487 ,n BCD C#:

! ' " + 0 1 1 0 0 1 0 0 1 0 0 0

' " % + 0 1 0 0 1 0 0 0 0 1 1 1

333333333333333333333333333333333333333333333333331 0 1 0 1 1 0 0 1 1 1 1

10 1 1$

33333333333333333333333333333333333333333333333333


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! ' " + 0 1 1 0 0 1 0 0 1 0 0 0

' " % + 0 1 0 0 1 0 0 0 0 1 1 1

333333333333333333333333333333333333333333333333331 0 1 0 1 1 0 0 1 1 1 1

0 1 1 0 0 1 1 0 0 1 1 0

1 1 1 1 1 1 1 1

3333333333333333333333333333333333333333333333333333330001 0 0 0 1 0 0 1 1 0 1 0 1

1 1 $3333333333333333333333333333333333333333333333333333333

A,/,#n #- 648 0n 487 ,n BCD C# ,s 1135.

Q.18 6rove the following oolean identities; (4)

)i* .J - JU - Y U + .J - U

)ii* A. + A. + A. = A +

Ans:

(,) '$#* /9 B##0n In/,/ .J - JU - Y U + .J - U

[email protected] + .J - JU - Y U

+ .J)U- Z * - JU + Y U )G U - Z + 1*

= .JU - .JZ - JU + Y U

= JU)1-.* - .JZ -Y U

= JU - .JZ -Y U )G 1-. + 1*

+ U )J-Y * - .JZ

+ U - .JZ )G J-Y +1*

+ U - .J)GU - .JZ + U - .J*+ &[email protected] (@n '$#*)

(,,) '$#* /9 B##0n In/,/ A - A - A B + A -

&[email protected] +A -

= A) - B * - )A - A* )G - B + 1 O A - A + 1*

+ A) - B * - )A - A*

+ A - A B - A - A

+ A - AB - A )A - A + A*+ [email protected] (@n '$#*)

Q.1 2or 2 = A..( + .(.D + A..( , write the truth table; implify using Farnaugh map

andrealie the function using NAND gates only; (1!)

Ans:

S,;,-,0/,#n #- L#, n/,#n 2 + A ( - C D - A (


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$


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1'

0


BBC

C

B BD

D

_

__

F = BC . BD = BC + BD

,. 4() NANDNAND &0,0/,#n

Q.2! Determine the analog output voltage of !3bit DA( )737 ladder networC* with V ref as $V whenthe digital input is 011100; (1!)

Ans:2or !3bit 737 DA( ladder networC, the output voltage is given by

VR

(n 1 n 1 0

)V0=

n an1+

an ++

a1+

a0

?iven Data H V7 + $V, n + !, a$+0, a'+1,a+1,a+1,a1+0,a0+0

V0= $ (a

! $

$ (

$+ a

$

'+ a

'

+ a

+ a

1+ a

0 )

1 0 )V0=

!0 +1

+1

+1

+ 0

+ 0

V = $"

0!'

+ 2.1875 V

Q.21 olve the following equations for . (6))i* .!10 = .

)ii* !$;$$10 + .1!

Ans:

(,) S#* /9


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%


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2raction 2raction . 7emainder new

fraction


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(,) 2irst convert the two numbers 0 and ! into its "3bit binary equivalent and find out the>s complement of 0, then add 30 to -!;

0 + 0 0 0 1 0 1 0 0 )"3bit binary equivalent of 0*

0 + 1 1 1 0 1 0 1 1 )1>s complement*

-13333333333333333333333333333333

0 + 30 + 1 1 1 0 1 1 0 0 )>s complement of 0*

-! + 0 0 0 1 1 0 1 0 )"3bit binary equivalent of !*33333333333333333333333333333

Addition of 30 to -!

+ -! + 0 0 0 0 0 1 1 033333333333333333333333333333

ence 30 to -! + )!*10 + )0110*;

(,,) 2irst convert the two numbers $ and 1$ into its "3bit binary equivalent and find

out the >s complement of 1$, then add -$ to 31$;

1$ + 0 0 0 0 1 1 1 1 )"3bit binary equivalent of 1$*

1$ + 1 1 1 1 0 0 0 0 )1>s complement*

-1333333333333333333333333333333

1$ + 31$ + 1 1 1 1 0 0 0 1 )>s complement of 1$*

-$ + 0 0 0 1 1 0 0 1 )"3bit binary equivalent of $*333333333333333333333333333333

Addition of 31$ to -$

+ -10 + 0 0 0 0 1 0 1 03333333333333333333333333333333

ence31$ to -$ + )10*10 + )1010*;

Q.23 )i* (onvert the decimal number '0 to 5#cess3 codeH (6))ii* (onvert the binary number 10110 to ?ray codeH

Ans:(,) 5#cess is a digital code obtained by adding to each decimal digit and then

converting the result to four bit binary;


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A ( A;)B;C* )A;B*;C

0 0 0 1 1

0 0 1 1 0

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 1

1 1 1 1 1


add the left most bit )1* to the adQacent bit )0* then add the ne#t adQacent pair and

discard the carry; (ontinue this process till completion;

- - - -

1 ! 1 1 !

1 1 1 ! 1ence ?ray equivalent of inary number 10110 is 11101;

Q.24 Verify that the following operations are commutative but not associative (6)

)i* NAND )ii* N87

Ans:

(,) (ommutative @aw is AB + BA ; To verify whether the NAND operation is(ommutative or not, prepare truth table shown in Table No;;1

A AB BA0 0 1 1

0 1 1 1

1 0 1 1

1 1 0 0

T0 N#.3.1

2rom the Table No;;1, we observe that the last two columns are identical, which means

AB + BA

Associative @aw is A;)B;C

*

= )A;B*;C

To verify whether the NAND operation is Associative or not, prepare truth table shown in

Table No;;

T0 N#.3.2

2rom the Table No;;, we observe that the last two columns are not identical, which means

A;)B;C* )A;B*;C

'0


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(,,) (ommutative @aw is A+B +B +A; To verify whether the N87 operation is(ommutative or not, prepare truth table shown in Table No;;

A A+B B +A0 0 1 1

0 1 0 01 0 0 0

1 1 1 1

T0 N#.3.3

2rom the Table No;;, we observe that the last two columns are identical, which means

A+B + B +A

Associative @aw is A+ )B + C* = )A +B* + C

To verify whether the N87 operation is Associative or not, prepare truth table shown in

Table No;;'

A ( A+ )B + C* )A +B* + C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 1

1 1 1 0 0

T0 N#.3.42rom the Table No;;', we observe that the last two columns are not identical, which means

A;+ )B + C* )A +B* + C

Q.25 6rove the following equations using the oolean algebraic theoremsH (5)

)i* A -A; - A ;B + A - )ii* A( - AB ( - AC - A( + A - ( - A(

Ans:

(,) ?iven equation is A -A; - A;B + A -

[email protected]; + A -A; - A;B

+ )A - A;B * - A;

= A )1-B * - A;

= A - A; )G 1-B +1*

= )A - A* )A - *

= )A - * )G A - A + 1*+ &[email protected]

@n '$#*

'1


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(,,) ?iven equation is A( - AB ( - AC - A( + A - ( - A(

[email protected] = A( - AB ( - AC - A(

+ A( - AB ( - AC - A(

= A( - AB ( - A )( -C *

= A( - AB ( - A )G ( -C + 1*

= A( - A ) -B (*

+ A( - A ) - (* )G -B ( + - (*

+ A( - A - A(

+ ( )A - A* - A - A(

+ ( )A - * - A - A( )G A - A + A - *+ A( - ( - A - A(

+ A - ( - A( )G A( - A( + A(*+ &[email protected]

@n '$#*

Q.26 A staircase light is controlled by two switches one at the top of the stairs and another at thebottom of stairs (5))i* 9aCe a truth table for this system;

)ii* Write the logic equation is 86 form;

)iii* 7ealie the circuit using AND387 gates;

Ans:

A staircase light is controlled by two switches 1 and , one at the top of the stairs andanother at the bottom of the stairs; The circuit diagram of the system is shown in fig;')a*;

1 00 1

S S1

SU PPLY

L

BULB

2

ON = 1

OFF = 0

,.4(0) C,$,/ ,0$0

(,) The truth table for the system is given in truth table ';1

1 @

0 0 0

0 1 1

1 0 1

1 1 0

T0 4.1

(,,) The logic equation for the system is given by @ + S1

- 1 S

'


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(,,,) 7ealiation of the circuit using AND387 gates is shown in fig ')b*

_

S . S

S 12

1

S 2 L

_

S . S1 2

,.4() L#, D,0$0 -#$ /9 ss/

Q.27 9inimie the following logic function using F3maps and realie using NAND and N87 gates;

2(A" " (" D) = I m(1""$"""&"11"1$) +

d("1)

()

Ans:9inimiation of the logic function 2)A, , (, D* + I m)1,,$,",&,11;1$* - d),1* using F3

maps and 7ealiation using NAND and N87 ?ates

(,) 0$n09 0; -#$ /9 #, -n/,#n ,s ,*n ,n /0 4.1

The minimied logic e#pression in 86 form is 2 + A B C - C D - BD - ADThe minimied logic e#pression in 68 form is 2 + )A - B -C * )C -D* )B-D* )A-D*

(,,) &0,0/,#n #- /9 ;$ss,#n s,n NAND 0/s:

The minimied logic e#pression in 86 form is 2 + AB C - C D - BD - AD andthe logic diagram for the simplified e#pression is given in fig;')c*

'


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A B C D

_

A + B + C

_

C +D

F_

B +D

_ _

A +D

,.4() L#, D,0$0

(,,,) &0,0/,#n #- /9 ;$ss,#n s,n NO& 0/s:

The minimied logic e#pression in 68 form is 2 + )A - B -C * )C -D* )B-D*

)A-D*and the logic diagram for the simplified e#pression is given in fig;')d*

A B C D _

_ _

A+B+C

_

C +D

_F

_

B +D

A +D

,.4() L#, D,0$0

Q.28 Design a ' to 1 9ultiple#er by using the three variable function given by2(A" " () = I m(1""$"!)

Ans:Ds,n #- 4 /# 1 /,;$ s,n /9 /9$ *0$,0 -n/,#n ,*n

(A"B"C) = I (1"3"5"6)

(7)

The function (A"B"C) = I (1"3"5"6) can be implemented with a '3to31 multiple#er as

shown in 2ig;%)a*; Two of the variables, and ( are applied to the selection lines inthat order, i;e;, B is connected to 1 and ( to S0. The inputs of the multiple#er are 0,


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''


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m5 +AB'Cproduce a 1 output, since the output is 1; whenBC + 01 regardless of thevalue ofA.

WhenBC + 10, input I2 is selected; ince A is connected to this input, the output will

be equal to 1 only for minterm m6 +ABC',but not for minterm m2 +A' BC',because whenA' +


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0 I0

1 I1 4 1

MUXY F

A I2

A! I3

S1 S 0

B

C

,.7() L#, D,0$0 #- 4?1 /,;$

Q.2 2ind the conversion time of a uccessive Appro#imation ABD converter which uses a 9

clocC and a $3bit binary ladder containing "V reference; What is the (onversion 7ate4

Ans:

%,*n 0/0:2requency of the clocC )2* + 9U

Number of bits )n* + $

(4)

)i* (onversion Time )T* +n

+cloc!a"#

$

X10!

+ ;$ sec

)ii* (onversion 7ate +1

+$

1

;$X10!

+ '00,000 conversionsBsec

Q.3! A !3bit 737 ladder DBA converter has a reference voltage of !;$V;


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'!


46/164

%


V =!;$ [0;!1 +1X $1 +1X '1 +1X 1 + 0X 1 + 0X 0 ]%

!

V =!;$ ['+ + ]

!

V% = ;"' V;

Q.31 (onvert in e#adecimal number; (4)

Ans:

1! 1" 1'

1! " 10 +"A5

0 "

Q.32 ubtract /% from !" using >s complements; (6)

Ans:

!"3)3%*+!"3)3%*using >s complement

>s complement representation of !"+01000100)!'-'*

>s complement representation of 3 )3%* + 00011011 +- %

11100101 +3% in >s complement

Now add !" and %

!" 0 1 0 0 0 1 0 0

3)3%* - 0 0 0 1 1 0 1 1

&$ 0 1 0 1 1 1 1 1 1

Which is equal to -&$

Q.33 Divide (101110)

by (101)

; (4)

Ans:

1 0 1 1 0 1 1 1 0 1 0 0 1

1 0 1

0 0 0 1 1 0

1 0 1

0 0 1

Guotient 31001

7emainder 3001

Q.34 6rove the following identities using oolean algebraH

)i* (A + )(A+ A)(+ A(+ ()+A + A( = ((A + )+ A(+ () ;)ii* A(A) (A)= A ;

'%


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)iii* A+ A + A = 0; ()

Ans:

(,) )A-*)A-A>>*(-A>)-(>*-A>-A(

+()A-*-A>)-(>*

L@S )A-*)A-A>->*(-A>-A>(>-A>-A(+ )A-*)1->*(-A>- A>(>-A( as )A-A>+1*

+ )A-*;1;(-A>- A>(>-A(

+ A-A(-A>- A>(>-A(

+ A(-A-A(-A(-A>-A>(>

A)(-1*-A()-1* -A>- A>(>

+ A-A(-A>- A>(>

+ ()A-* - A>)-(>* + &@S

@n '$#*

(,,) A)A;B*;B)A;B*=

A B

@et us taCe

o we have

X = A)A;B*

Y =B)A;B*

X ;Y =A

B3333333

Also X =A)A;B*

+A)A+B *

y using De9organ>s @aw )A*>+A>->

. + )A)A>->**>+)AA>-A>*>+)A>*>+)A>-* 3333331

Now J + ))A*>*>+M)A>->*>+ MA>->>+)A>*>+)A->* 333333

Now (ombining . O J from 1 O above, we have @;; in as H

))A->*)A>-**>

+MAA>--A>>-A>

+)A-A>>*>

+A .87 + &@S

@n '$#*

(,,,) ))A*>-A>-A*>+0

@ )AB+A+AB*

+ )1+A*

since AB +AB =1

+ 1since 1+A=1

+ 0 = &@S @n '$#*

Q.35 A combinational circuit has inputs A, , ( and output 2; 2 is true for following inputcombinations

A is 2alse, is True

A is2alse, ( is True

A, , ( are 2alseA, , ( are True

'"


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)i* Write the Truth table for 2; :se the convention True+1 and 2alse + 0;

)ii* Write the simplified e#pression for 2 in 86 form;

)iii* Write the simplified e#pression for 2 in 68 form;)iv* Draw logic circuit using minimum number of 3input NAND gates; (7)

Ans:

(,) 0,n /9 /$/9 /0A ( 2

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

A is false b is true 2or both value of c 2 is true;

(,,) S,;,-, ;$ss,#n -#$ 0n -#n 0;

-(

(,,,) S,;,-, ;$ss,#n -#$ ,n 'OS -#$+)A;)(*>*

2Y+2+)A;)(*>*>

(,*) L#, ,$,/ s,n ,n, n$ #- 2,n;/ NAND 0/s

Q.36 9inimise the logic function

2 (A, , (, D)= Z 9 (1, , , ", &, 10, 11,1') d (%, 1$):se Farnaugh map; Draw the logic circuit for the simplified function using N87 gates

only; (7)

'&


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Ans:

2+[9)1,,,",&,10,11,1'*;d)%, 1$*

2>+>D->(-A(-A>y (omplementing 2

2+)>D->(-A(-A>*>

+ M)>D*>)>(*>)A(*>)A>*>>+ )-D>*)-(>*)A>-(>*)A>-*

TaCing complement twice and without opening the bracCet

2+M)-D>*-)-(>*>)=A>-(>*-)A>-*>The logic circuit for the simplified function using N87 gates

Q.37 The capacity of F 1! 6789 is to be e#panded to 1! F 1!; 2ind the number of 6789chips required and the number of address lines in the e#panded memory; (4)

Ans:7equired capacity +1!C # 1!

Available chip )6789* +C # 1!The no of chip +1!C # 1! + "

C # 1!


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Thus the address line required for the single chip + 11


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$1


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"


2 )A, , (* + Im )1,',$,!,%* in standard 68 form; (8)

Ans:( (A,B,C )& \ (1,',$,!,%) in standard 68 form2 + m1 - m' - m$ - m! - m%2 + \m)1,',$,!,%*

+ [ 9)0,,*+ 90 9 9

+ )A--(*)A- -(*)A- -( *

Q.41 Design a H1 multiple#er using two 1!H1 multiple#ers and a H1 multiple#er; (8)

Ans:

To design a . 1 9:. using

I0

I15

I16

I31

"3 "2 "10

16 X1MUX

"2 "1"3 "0

16X1MUX

2X1 #

MUX

S$%$&' %$ M

Two 1! . 1 9:. O one . 1

There are total input lines and one 8B6 line; The . 1 9:. will transmit

one of the two


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Q.43 6erform the following operations using the >s complement methodH

)i* / '" )ii* / '" / (4)

Ans:

(,) 3 '"add them

0 1 0 1 1 1

* )3 '"* - 0 1 0 0 0 0

%1 1 0 0 1 1 1

(,,)/ '" 3 + 3 '" - )3*

3'" + 1 1 0 1 0 0 0 0

3 + 1 1 1 0 1 0 0 1

1 1 0 1 1 1 0 0 1 + 3%1

(arry is discarded

Q.44 6rove the following oolean identities using the laws of oolean algebraH)i* (A + )(A +()= A + ()ii* A( + A( + A( = A( +

()

(4)

Ans:)i* )A-*)A-(*+A-(

L@S AA-A(-A-(+A-A(-A-(

87 A))(-1*-A)-1**-(

87 A-A-(

87 A-( + &@S

@n '$#*

)ii* A(-A>(-A(>+A) - (*

L@S A()->*-A)(-(>*

87 A(-A

87 A)-(*+ &@S

@n '$#*

$


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Q.45 The Farnaugh map for a 86 function is given below in 2ig;1; Determine the simplified86 oolean e#pression; (5)

Ans:

Q.46 A certain memory has a capacity of 'F"

)i* ow many data input and data output lines does it have4

)ii* ow many address lines does it have4)iii* What is its capacity in bytes4 (5)

Ans:

(,) available capacity +'F#"+

10#

10# "

+ 1

#"

As in the 'F#" ,the second number represents the number of bits in each word so the

number of data input lines will be ")also the data output lines* ;(,,)


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Q.48 An "3bit successive appro#imation AD( has a resolution of 0mV; What will be its digitaloutput for an analog input of ;1%V4 (4)

Ans:7esolution +0mv

Analog input +;1%v

5quivalent value+);1%*B);1%*+10";$5quivalent inary value+1101100;1

Q.4 A microprocessor uses 7A9 chips of 10'1capacity;

(,) ow many chips will be required and how many address lines will be connected to

provide capacity of 10' bytes;(,,) ow many chips will be required to obtain a memory of capacity of 1! F bytes; (5)

Ans:) i * Available chips + 10' # 1 capacity

7equired capacity + 10' # " capacity*o. o( C+-=

10' ."= "

10'.1

Number of address lines are required + 10 )i;e; 10' + 10

*

As the word capacity is same ) 10' * so same address lines will be connected to all chips;

) ii *

*o.%( C+-R#/!# =1! .1 0' ."

= 1"10'.1

Q.5! 2ind the oolean e#pression for logic circuit shown in 2ig;1 below and reduce it using

oolean algebra; (6)

Ans:J + )A*> - )A> - *>

= A> - > - A> :sing Demorgan>s Theorem;= A> - >)1-A*

= A> - > ince 1-A+1

Q.51


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Ans:

J)A,,(*+I),,$,!*

@et us taCe ,( as the select bits and A as input; To decide the input we write;

J + A>(>-A>(-A>(-A(>+ 0 if +0, (+0

+ A if +0, (+1

+ 1 if +1, (+0+ A>if +1, (+1

The corresponding implementation is shown in the figure; Thus

0

A '#1 J

1 9:.

A>

(

Q.52 Design a mod31 ynchronous up counter; (8)

Ans:

Ds,n 0 # 12 sn9$#n#s #n/$ s,n D-,;-#;s.

I s /0/ /0

6resent state Ne#t state 7equired D


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2irst draw the state table having present state, ne#t state and required flip3flop input to give

the transition; D flip flop gives the output same as the ne#t state itself; Then solve by using F

maps to find out DA D D( DD for all states;

:nused states are 1100,1101,1110,1111 they can be treated as don>t care conditions from the

table; Draw Farnaugh3maps for DA, D, D( and DD as follows and obtainoolean e#pressionsforthem;

$%


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$"


59/164


L#, ,0$0 -#$ #12 Sn9$#n#s ;#n/$

Q.53 2ind how many bits of AD( are required to get an resolution of 0;$ mV if the ma#imum

full scale voltage is 10 V; (8)

Ans:

7esolution+;$mv

2ull scale output+-10v

Xresolution +)$mv*B10#100+0;0$X

No of bits +@og)#1000* + 0

Q.54 (onvert the decimal number '$!%" to its he#adecimal equivalent number; (4)

Ans:)'$!%"*10+)!5*1!

$&


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1! '$!%"

1! "$'

1! 1%"

1'

!

1! 11

0 11


5!

)'$!%"*10+)!5*1!

Q.55 Write the truth table of N87 gate; (4)

Ans:A 2

0 0 10 1 0

1 0 01 1 0

Q.56 Design a (D to e#cess code converter using minimum number of NAND gates; intHuse C map techniques; (8)

Ans:

2irst we maCe the truth table

(D no

A ( D

5.(53 N8

W . J U0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

Then by using F maps we can have simplified functions for w, #, y, as shown belowH

!0


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!1


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NAND 0/ ,;n/0/,#n -#$ s,;,-, -n/,#n

!


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W + D - AD - A> - (

y complementing twice we get

W + ))D - AD - A> - (*>*>

+ ))D*> ; )AD*> ; )A>*> ; )(*>*>

. + (>D - >D - >(

y complementing twice we get. + (>D - >D - >(

+ ))(>D*> ; )>D*> ; )>(*>*>

J + (>D> - (D

+ ))(>D>*> - )(D*>*>

U + D>

L#, ,0$0 -#$ BCD /# ss 3 # #n*$/$ s,n ,n, n$ #-

NAND 0/s

Q.57 With the help of a suitable diagram, e#plain how do you convert a EF flipflop to T type

flipflop; (4)

!


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65/164

" 1%% 1

" 6

" 2

0


Q.5 (onvert (1%%;$)10 to octal; (8)

Ans:)1%%;$*10 + ) *"2irst we taCe integer part

Thus )1%%*10 + )!1*"

Now as 0;$ # " + ;00

and 0;00 # " + 0Thus )0;$*10 + )0;*"Therefore, Thus )1%%;$*10 + )!1;*"

Q.6! 6erform the following subtraction using 1>s complement

)i* 11001 / 10110 )ii* 11011 3 11001 (8)

Ans:

)i* 11001 / 10110 + . / J

. + 11001

1>s complement of J + 01001um + 1 00010

5nd around carry + 1

o .3J + 00011)ii* 11011 / 11001 + . / J

. + 11011

1>s complement of J + 00110um + 1 00001

5nd around carry + 1

o .3J + 00010

Q.61 6rove the following identities

)i* A (+

A (+

A (+

A (=

()ii* A + A ( + A + A ( = +A (

(8)

Ans:

(,) L@S + A>>(> - A>(> - A>(> - A(>+ A>(> )> - * - A(> )> - *

+ A>(> - A(> Mas >- + 1

+ (> )A> - A*+ (> Mas A>-A +1

!$


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+ &@S.

@n '$#*

(,,) L@S + A - A( - A> - A>( + - A(+ )A - A>* - A( ) - >*

+ - A( Mas - > + A - A> + 1

+ - A(+ &@S.

@n '$#*

Q.62 2ind the boolean e#pression for the logic circuit shown below; (8)

Ans:

8utput of ?ate31 )NAND* + )A*>8utput of ?ate3 )N87* + )A>-*>

8utput of ?ate3 )N87* + M)A*> - )A>-*>>

Now applying De39organs law, ).-J*> + .>J>and ).J*> + ).>-J>*

M)A*> - )A>-*>> + M)A*>> M)A>-*>>

+ )A* )A>-*+ AA> - A+ A

+ A;

Q.63 7educe the following equation using C3map

J = ( D + A ( D + A ( D + A ( D + A

( D(8)

Ans:

9ultiplying the first term by )A-A>*

J + A>(>D> - A(>D> - A>(>D - A(>D - A>(D - A(D+ I )',1,$,%,1$,1*+ (> - D

!!


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Q.64


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" # 1

9:.


many lines of these will be common to each chip4)iii* ow many bits must be decoded for chip select4 What is the sie of decoder4

(8)

Ans:

(,)Available 7A9 chips + 1" # "

7equired memory capacity + 0'" # "Number of chips required + )0'" # "* B )1" # "*

+ 1!;(,,) (hips available are of 1" # " in sie;


69/164


Q.66 ow many bits are required at the input of a ladder DBA converter, if it is required to give aresolution of $mV and if the full scale output is -$V; 2ind the Xage resolution;

(8)

Ans:2irst we find out the ratio of 2ull scale output to 7esolution + $V B $ mV + 1000;

Now number of bits + log 1000 + 10;

6ercentage 7esolution + $ mV B $ V ^ 100 + 0;1X

Q.67 A !3bit Dual lope ABD converter uses a reference of /!V and a 1 9clocC;


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'A&T III

D E SC& I ' TI V E S

Q.1 Distinguish between min terms and ma# terms; (6)

Ans: Distinguish between 9interms and 9a#termsH

)i* 5ach individual term in standard um 8f 6roducts form is called as minterm whereas

each individual term in standard 6roduct 8f ums form is called ma#term;

)ii* The unbarred letter represent 1>s and the barred letter represent 0>s in min terms,

whereas the unbarred letter represent 0>s and the barred represent 1>s in ma#terms;)iii*


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_

B

_

A AC

C

_

_ _

(AB) (AC) = AB + AC

,.4() L#, D,0$0 -#$ /9 ;$ss,#n ? = A (B + C)

Q.3 9ention the various


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A (

0 0 0 0

0 1 1 0

1 0 1 01 1 0 1

T0 6.1 T$/9 T0 -#$ @0- A$

2rom the truth table, we obtain the logical e#pressions for and ( outputs as

+ A -A B( + A

The logic diagram for an alf3adder using gates is shown in fig;!)a*

ASB

C

,.6(0) L#, D,0$0 -#$ 0n @0-0$

Q.5 :sing a suitable logic diagram e#plain the worCing of a 13to31! de multiple#er;(7)

Ans:

G#$,n #- 0 1/#16 D/,;$: A demultiple#er taCes in data from one line and

directs it to any of its N outputs depending on the status of the selected inputs;


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Demulti-

plexer

Input

Selection

Lines

D C B A

Logic

Function

Demultiplexer Outputs

D0 D1 D2 D3 D4 D D! D" D# D$ D10 D11 D12 D13 D14 D1

0 0 0 0 0 D CB A 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 0 0 0 1 D CBA 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 0 0 1 0 D CB A 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1

3 0 0 1 1 D C B A 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1

4 0 1 0 0 D CB A 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

5 0 1 0 1 D CB A 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

6 0 1 1 0 D C BA 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1

7 0 1 1 1 D C B A 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1

8 1 0 0 0DCB A 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

1 0 0 1DC BA 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1

10 1 0 1 0

DC B A

1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1

11 1 0 1 1D C B A 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1

12 1 1 0 0D CB A 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1

13 1 1 0 1D CB A 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1

14 1 1 1 0D C B A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1

15 1 1 1 1 D C B A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

T0 7.1 T$/9 T0 #- 1/#16 D/,;$

%


74/164


,_

A _

_BC

_

D A

B

_

1 ,

_ _ _ _

D ( A B C D )

0

_ _ _

D ( A B C D )

1

_ _ _

D ( A B C D )

2D-' -I/'

_

,2

_ _

D ( A B C D )

3

C

_ _ _A D ( A B C D )

A4

_

A_ _

D ( A B C D )5

S

B

LB

C _

B

L

I

N CD

C

S_

C

_ _

D ( A B CD )

6

_

D ( A B CD )

7

_ _ _

D ( A B CD )

8

_ _D ( A B C D

)

D _ _D

D ( A B C D )_ 10

D

_

_ D (A B C D )

C11

_ _

D ( A B C D )

12

_ _

B D ( A B C D )

13

_

A_

D ( A B C D )14

A D (AB C D )BC 15D

,.7(0) L#, D,0$0 #- 1/#16 D /,;$


75/164

%'


76/164


Q.6 ; With relevant logic diagram and truth table e#plain the worCing of a two input 5.387 gate;

(7)

Ans:T#In;/ E?O& %0/: An 5#clusive387 )5.387* gate recognies words which have

an odd number of ones; 2ig;%)b* shows the logic diagram of an 5.387 gate and 2ig;%)c*

shows the symbol of an 5.387 ?ate; The upper AND gate gives an output A and the

lower AND gate gives an output AB ;

__A

A A B

__

A BB

B

_ _

Y = A B+A

B

,.7() L#, D,0$0 #- E?O& %0/

A

BY

,.7() S# #- E?O& %0/

Therefore, the output equation becomes J + A - A B + A 5.387 + A


77/164


inary (ounter has ma#imum of

states i;e;, " states, which requires 2lip32lops;

The word inary (ounter means a counter which counts and produces binary

outputs000,001,01033111;


78/164

%


&I'& % %0 1 2

( % ( %

0 01

1

(

2

%

2

CLOC)FF FF FF

*+LS,S 0

) 0 Cr

1

)1 Cr

2

)2 Cr

CL,A-

,.8(0) L#, D,0$0 #- 3B,/ B,n0$ &,;; C#n/$

7ipple counters are simple to fabricate but have the problem that the carry has to propagatethrough anumberof flip flops; The delay times of all the flip flops are added; Therefore,

they are very slow for some applications; Another problem is that unwanted pulses occur atthe output of gates;

1CLOC

1 2 3 4 5 6 7 8 10

PULSS 0

1%

00

1%

1 0

1

%2

0 $

,.8() T,,n D,0$0 #- 3,/ B,n0$ &,;; C#n/$

The timing diagram is shown in F.). FF0 is @ flip flop and FF2 is the 9 flip

flop; ince FF0 receives each clocC pulse, G0 toggles once per negative clocC edge as

shown in 2ig; ").The remaining flip flops toggle less often because they receivenegative clocC edge from preceding flip flops; When G0 goes from 1 to 0, FF1 receives

a negative edge and toggles; imilarly, when G1 changes from 1 to 0, FF2 receives a

negative edge and toggles; 2inally when G changes from 1 to 0, FF3 receives a

negativeedge and toggles; Thus whenever a flip flop resets to 0, the ne#t higher flip floptoggles;

This counter is Cnown as ripple counter because the "th clocC pulse is applied, the trailing

edge of "thpulse causes a transition in each flip flop; G0 goes from igh to @ow, thiscauses G1 go from igh to @ow which causes G to go from igh to @ow which causes

G


79/164

%%


80/164

0


to go from igh to @ow; Thus the effect ripples through the counter;


81/164

1

o


This completes the serial entry of ' bit data into the register; Now the @ 0 is on theoutput G;

!; (locC pulse $ is applied; @ 0 is shifted out; The ne#t bit 1 appears on G output;%; (locC pulse ! is applied; The 1 on G is shifted out and 0 appears on G output;"; (locC pulse % is applied; 0 on G is shifted out; Now 1 appears on G output;&; (locC pulse " is applied; 1 on G is shifted out;

10; When the bits are being shifted out )on (@F pulse $ to "* more data bits can beentered in;

Q. With the help of 737 binary ladder, e#plain the worCing of a '3bit DBA converter (14)

Ans:&2& L0$ n/#$ /9#:


82/164


Whenever any of the bit or bits of the digital input word D D D1D0 is high,the corresponding transistor switch is 8N .#. connected to virtual ground and the current of

that vertical branch of the ladder comes from the output, otherwise the current of the

vertical branch comes directly from the actual ground without any effect on the output;ence the output current )lout* gives the analog current value corresponding to the digital

input word; This analog current gets converted to the analog voltage Vo;

An &2& 4B,/ L0$ N/#$ DAC 0s #n $-$n *#/0: An 737 '3bit @adderNetworC DBA (onverter is shown in fig; 10)b*

LO9

D

: I,:

D D

$#

D0 1 2 3

#

2 2 2 2

2

-

A B C D

+

o

,.1!() &2& 4,/ L0$ N/#$ DHA C#n*$/$

' $ ## - :

S/; 1: s theorem at .1,.1> , the circuit of fig;10)c* becomes the equivalent

circuit showninfig;10)d*

"0


83/164


#

X2

X1

B C D

-

o

+

+

; 2* $#

2 2 2

X !1

X !2

,.1!() &2& L0$ N/#$ DHA C#n*$/$ 9n T9*n,ns T9#$ 0;;,

0/ ?1 0n ?1

Again Applying Thevenin>s Theorem at .,.>, then the circuit of fig;10)d* becomes the

equivalent circuit shown in fig;10)e*;

#

X2

X3

C D

-

+

o

+

; 4

* $ #

2 2

X !2

X !3

,.1!() &2& L0$ N/#$ DHA C#n*$/$ 9n T9*n,ns T9#$ 0;;, 0/

?2 0n ?2

Again Applying Thevenin>s Theorem at .,.> the circuit of fig;10)e* becomes theequivalent circuit shown in fig;10)f*H

#

X4

X3

D

-

+

o

+ 2

; 8

* $ #

X !3

X!4

,.1!(-) &2& L0$ N/#$ DHA C#n*$/$ 9n T9*n,ns T9#$ 0;;, 0/

?3 0n ?3

"1


84/164

o


8nce Again applying Thevenin>s theorem at section .', .'> the circuit of fig;10)f* finally

becomes the equivalent circuit shown in fig;10)g*.

#

#

- 2

; 16 -

+$#

+

o

+

; 16

* $#

,.1!() &2& L0$ N/#$ DHA C#n*$/$ 9n T9*n,ns T9#$ 0;;,

0/ ?4 0n ?4

S/; 2: s Theorem, three times and reducing the circuit each time at sections.1, ., . we finally get the circuit as shown in fig;10)i*;

#

2

; 8 -$#

+

o

,.1!(,) E


85/164


S/; 3: 7epeating the same e#ercise of D igh and other bits @ow, we get the

finally reduced (ircuit as shown in fig;10)Q*;

#

2

; 4 -$#

+

o

,.1!() E


86/164

(

'


ence the derived equivalent circuit of the 737 ladder networC proves that the bits of the

input digital wordD, D, D1, D0 receive the applied voltages as per their binary weights

and we get the corresponding analog value at Vo; Therefore,

V!#( D D D D

V = ;R

+

+

1

+

0

%

V!#(

R '

D D

" 1!

D V = ;R

n1+

n +;;;;;+

0%

R(

'

n


87/164

"'


88/164

M *S

< *

F F


(,,,) T# S/0/:


89/164


In;/s O/;/

67 (@7 (@F E F G

0 0 . . . 7ace (ondition

0 1 . . . 11 0 . . . 0

1 1 . 0 0 No change

1 1 0 1 0

1 1 1 0 1

1 1 1 1 Toggle

T0 11.1 T$/9 T0 #- F 0s/$S0* ,;#;

Q.11 (ompare the memory devices 7A9 and 789; (5)

Ans:

(omparison of emi3conductor 9emories 789 and 7A9

T9 0*0n/0s #- &O 0$:

1;


90/164

B


_

AA

A A + B

B

__

BA + BB

_ _

A . B

,.3(0) L#, ,0$0 -#$ A + B ,.3() L#, ,0$0 -#$ AB

The equality of the logic diagrams of fig; )a* O )b* is proved by the truth table shown in

table )c*

In;/s In/$,0/ V0s O/;/s

A A - A B A + B A B0 0 0 1 1 1 1

0 1 1 1 0 0 0

1 0 1 0 1 0 0

1 1 1 0 0 0 0

T0 2()

(,,) S/0/n/ #- s#n /9#$: AB = A + B

'$##-: The two sides of the equationshown in fig;)c* O )d*;

AB = A +B is represented by the logic diagrams

_

AA

A A . B

B

_

A . BB

_ _A + B

,.3() L#, ,0$0 -#$ AB ,.3() L#, ,0$0 -#$ A + B

The equality of the logic diagrams of fig;)c* O )d* is proved by the truth table shown in

table )d*

In;/s In/$,0/ V0s O/;/s

A A ; A B A;B A - B

0 0 0 1 1 1 1

0 1 0 1 0 1 1

1 0 0 0 1 1 1

1 1 1 0 0 0 0

T0 2()

Q.13 Discuss in detail, the worCing of 2ull Adder logic circuit and e#tend your discussion toe#plain a binary adder, which can be used to add two binary numbers; (14)

"%


91/164

An

1 1

1 1


Ans:A$: A half3adder has only two inputs and there is no provision to add a carry

from the lower order bits when multibit addition is performed; 2or this purpose, a third

input terminal is added and this circuit is used to add An, n, and (n31, where An and nare the nth order bits of the numbers, A and respectively and (n31 is the carry

generated from the addition of )n31*th order bits; This circuit is referred to as full3

adder and its truth table is given in Table $;1


92/164

""


93/164


The logic diagrams for the n and (n are shown in fig;$)c* O fig;$)d*;

A

B C

*1

Sn

,.5() NANDNAND &0,0/,#n #- Sn

A

B

CC

n*1

A

C*1

,.5() NANDNAND &0,0/,#n #- Cn

B,n0$ A$: The full adder forms the sum of two bits and a previous carry; Two binarynumbers of nbitseach can be added by means of inary Adder;


94/164

C

1

S


A inary 6arallel Adder is a digital function that produces the arithmetic sum of two binarynumbers in parallel; , J>, U>* is equal to 1 represents the minterm equivalent of the binary

number presently available in the input lines;

&0


95/164


In;/s

? > K

O/;/s

D! D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

T0 6.1 T$/9 T0 #- 3/#8 ,n D#$

D 5 Y5 650

D 5 Y5 61

D 5 Y 652

> D 5 Y 63

D Y5 65Y

4

X

D Y5 6

D Y 65!

D Y 6"

,. 6(0) L#, C,$,/ #- 3/#8 ,n D#$

Q.15 What is an encoder4 Draw the logic circuit of Decimal to (D encoder and e#plain its

worCing; (7)

&1


96/164


Ans:En#$H An 5ncoder is a combinational logic circuit which converts Alphanumeric

characters into inary codes; 3 >2 >1 >!

0 0 0 0 0

1 0 0 0 1

0 0 1 0

0 0 1 1

' 0 1 0 0

$ 0 1 0 1

! 0 1 1 0

% 0 1 1 1

" 1 0 0 0

& 1 0 0 1


97/164

&


98/164


1Y 7 LSB 8

0

2

3

Y1

4

5

6Y

2

7

8

Y 7 2SB 8

3

,.6() L#, ,0$0 -#$ D,0 /# BCD En#$

Q.16 What is a flip3flop4 What is the difference between a latch and a flip3flop4 @ist out the

application of flip3flop; (4)

Ans:,;#;: A flip3flop is a basic memory element used to store one bit of information; oth

2lip3flops and latches are bistable logic circuits and can reside in any of the two stable

states due to a feedbacC arrangement; The main difference between them is in the methodused for changing the state;

A;;,0/,#ns #- #;#;s:)1* ounce elimination switch

)* 6arallel Data torage in 7egisters)* Transfer of Data from one bit to another;

)'* (ounters

)$* 2requency Division

Q.17 Draw the circuit diagram of a 9aster3slave E3F flip3flop using NAND gates; What is race

around condition4 ow is it eliminated in a 9aster3slave E3F flip3flop; (1!)

Ans:L#, D,0$0 #- 0s/$S0* F ,;#; s,n NAND %0/s: 2ig;%)a* shows

the logic diagram of 9aster3lave E3F 2lip32lop using NAND gates;

&


99/164

M


P,

3M,

1M SM S

t care;

D,0 D,,/

D,s;0

In;/s O/;/s

A B C D 0 -

0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1

0 0 1 1 1 1 1 1 0 0 1

' 0 1 0 0 0 1 1 0 0 1 1$ 0 1 0 1 1 0 1 1 0 1 1

! 0 1 1 0 0 0 1 1 1 1 1

% 0 1 1 1 1 1 1 0 0 0 0

" 1 0 0 0 1 1 1 1 1 1 1

& 1 0 0 1 1 1 1 0 0 1 1

T0 6.1 T$/9 T0 #- BCD/#7 Sn/ D#$

(,) 0; 0n L#, D,0$0 -#$ D,,/0 O/;/ 0:

10"


114/164


The simplified e#pressions for the 2ig;!)d* is given by a + B D - D - (D - A and thelogic diagram is given in 2ig;!)e*

_

B

_

D

B

9D

C

D

_

A

,.6() L#, D,0$0 -#$ O/;/ 0

(,,) 0; 0n L#, D,0$0 -#$ D,,/0 O/;/ :

The simplified e#pressions for the 2ig;!)f* is given by b + B - C D - (D and the logicdiagram is given in 2ig;!)g*

_

C

_

D

:C

D

B

,.6() L#, D,0$0 -#$ O/;/

(,,,) 0; 0n L#, D,0$0 -#$ D,,/0 O/;/ :

10&


115/164


The simplified e#pressions for the 2ig;!)h* is given by c + B - C - D and the logic diagram isgiven in 2ig;!)i*

_

B

C c_

D

,.6(,) L#, D,0$0 -#$ O/;/

(,*) 0; 0n L#, D,0$0 -#$ D,,/0 O/;/:

110


116/164


The simplified e#pressions for the 2ig;!)Q* is given by

d + B D - (D - B ( -C D and the logic diagram is given in 2ig;!)C*

_

B

_

D

C_

D

_ ;

B

C

B_

C

D

,.6() L#, D,0$0 -#$ O/;/

(*) 0; 0n L#, D,0$0 -#$ D,,/0 O/;/ :

The simplified e#pressions for the 2ig;!)l* is given by e + B D - (D and the logicdiagram is given in 2ig;!)m*

_

B

_

D

eC

_

D

,.6() L#, D,0$0 -#$ O/;/

111


117/164


(*,) 0; 0n L#, D,0$0 -#$ D,,/0 O/;/ -:

The simplified e#pressions for the 2ig;!)n* is given by f + A -C D - C -D and thelogic diagram is given in 2ig;!)o*

_

C

_

D

B

_

C


118/164


(*,,)0; 0n L#, D,0$0 -#$ D,,/0 O/;/ :

The simplified e#pressions for the 2ig;!)p* is given by g + A - C - B (- ( D and thelogic diagram is given in fig;!)q*;

B

_

C_

B

C g

C

_

D_

A

,.6(


119/164

In;/

Dn

O/;/

Qn+1

0 0

1 1

U


DA A INPUD

0

OS D

0 1

PU

S1 D

2S

D3

,.7(0) L#, C,$,/ #- 1:4 D/,;$

Q.3! ?ive the truth table of 37 and D3flipflops; (onvert the given 37 flipflop to a D3flipflop; (8)

Ans:The Truth Table of 37 2lip32lop is shown in 2ig;%)b* and truth table of D 2lip32lop is

shown in 2ig;%)c*

In;/s O/;/

Sn &n Qn+1

0 0 Gn

1 0 1

0 1 0

1 1 4

,.7() T$/9 T0 -#$ S& ,;#; ,.7() T$/9 T0 -#$ D,;#;


120/164


P

P

SD

CL

S*

FLIP*FLOP

_

=

D

CL

=D

FLIP*FLOP

_

C C

,.7 () S& ,;#; #n*$/ ,n/# 0 D,;#; ,.7 () L#, S# #- D ,;#;

Q.31 Define a register; (onstruct a shift register from 37 flip3flops; 5#plain its worCing;(8)

Ans:

&,s/$: A register consists of a group of flip3flops and gates that effect theirtransition; The flip flops hold the binary information and the gates control when and

how new information is transformed into the register;S& ,;#; S9,-/ &,s/$: hift registers can be built by using 7 flip3flops;2ig;&)a*

shows the '3bit shift register, which uses 7 flip3flops;


121/164


Ans:S9,-/ &,s/$ 0s 0 &,n C#n/$: A 7ing (ounter is a (ircular hift 7egister with only

one flip3flop being set at any particular timeR all other are cleared; The single bit is shifted

from one flip3flop to the other to produce the sequence of timing signals; 2ig;&)b* shows a'3bit shift register connected as a ring counter; The initial value of the register is 1000,

which produces the variable T0; The single bit is shifted right with every clocC pulse and

circulates bacC from T to T0; 5ach flip3flop is in the 1 state once every four clocC pulsesand produces one of the four timing signals shown in 2ig;&)c*; 5ach output becomes 1

after the negative3edge transition of a clocC pulse and remains 1 during the ne#t clocC

pulse;

S: IF I,:

,IS

0 1 2 3

,.() 4,/ s9,-/ $,s/$ #nn/ 0s 0 $,n #n/$.

C LOC PU LS

0

1

2

3

,.() G0*-#$s 0/ /9 #/;/ #- ,;#;s

Q.33 Differentiate between linear addressing and matri# addressing modes with e#amples; Which ofthem is the best method4 (4)

Ans:L,n0$ A$ss,n: Addressing is the process of selecting one of the cells in a memory to

be written into or to be read from;


122/164

16

X

1

=

=

=

=

=

=


1 COLUMN

1

1

2

3

16

O9S

16

,.11 (0) L,n0$ A$ss,n #

0/$, A$ss,n #: The arrangement that requires the fewest address lines is asquare array of n rows and n columns for a total memory capacity of n # n + n

cells; Thisarrangement of n rows and n columns is frequently referred to as 9atri# Addressing which

is shown in fig;11)b*;

4 COLUMNS

1 2 3 4

1

O9S3

4

4 4

,.11() 0/$, A$ss,n #

Bs/ /9#: 9atri# Addressing is the best method, because this configuration onlyrequires " address lines )i;e;,' rows and ' columns*, whereas @inear Addressing method

requires a total of 1% address lines )i;e;, 1 column and 1! rows*;The square configuration is

so widely used in industry;

Q.34 Write short note on the followingH Eohnson counter; (4)

Ans:

F#9ns#n C#n/$: Eohnson (ounter is an synchronous counter, where all flip3flops areclocCed simultaneously and the clocC pulses drive the clocC input of all the flip3flops

together so that there is no propagation delay; 2ig;11)e* shows the circuit of Eohnson

counter;


123/164


has a total of " states ) nbit sequence will have 2n states*; Thus an nbit Eohnson counter

will have a modulus of 2n.

The G output of each stage feeds theD input of ne#t stage; ut the output of the last

stage feeds theDinput of first stage; The counter fills up with 1>s from left to right and

then fills up 0s again as shown in Table 11;; 2ig; 11() shows the waveshapesBtiming

diagram of ' bit Eohnson counter;

% % % %0 1 2 3

D % D % D % D %0 0 1 1

2 23 3

FF FF FF FF

30 1 2

%3

CLOC)

,.11() L#, D,0$0 #- F#9ns#n #n/$

(locC 6ulse G0 G1 G G

0 0 0 0 0

1 1 0 0 0

1 1 0 0

1 1 1 0

' 1 1 1 1$ 0 1 1 1

! 0 0 1 1

% 0 0 0 1

T0 11.2 S


124/164


Q.35 The voltage waveforms shown in 2ig;1 are applied at the inputs of 3input AND and 87 gates;Determine the output waveforms; (3)

Ans:The 8utput waveforms for AND and 87 gates are shown in fig;)a*

1

A

00 1 2 3 4 5

1

B

0

'$ (")

'$ (")

1

A/ D OF A > B

i=e=? A B0

1

O- OF A > B

i=e=? A @ B0

,.3(0) O/;/ G0*-#$s

Q.36 What are the advantages of (98 logic and e#plain (98


125/164


+ CC

S2

(*

&-$%)2

D I2 D

, D

D1

(*&-$%)

1S

1

,.5(0) L#, D,0$0 #- COS In*$/$

Q.37 What is Tri3state logic and e#plain Tri3state logic inverter with the help of a circuit diagram;

?ive its Truth Table; (7)

Ans:T$,s/0/ L#,H


126/164

4


+ C C

C 7)'7%

5

1

2D -'-()./'

Y

D 9t 9 out pu t

3

,.5() L#, D,0$0 #- T$,s/0/ L#, In*$/$

Data


127/164


128/164


Q.3 What is a hift 7egister4 What are its various types4 @ist out some applications of hift7egister; (6)

Ans:

S9,-/ &,s/$: A register in which data gets shifted towards left or right when clocC

pulses are applied is Cnown as a hift 7egister;

T;s #- S9,-/ &,s/$s:)i* erial3


129/164


,;#; A:

The initial state is 0;


130/164

B


0; -#$ FC 0; -#$ CFC = AB C = A,.(*) ,.(*,)

,.8() 0$n09 0;s -#$ FA"A"FB"B"FC"C

A C

B

1 ( A

A

( ( CB C

CLOC)

*+LS,SFF

A

1 ) A A

FFB

)

B B

FFC

)

C C

,.8() L#, D,0$0 -#$ OD6 Sn9$#n#s C#n/$

Q.41 What is 7894


131/164


two bits )A,A2) are decoded by the decoder D@ which activates one of the four columnsense amplifiers;

0 1 2 3 C OLUM N

O9

D D00 01 D 02

0

D03

A0

1 # 4

DCOD

DL

A1

D10

D11 D

12

1

D13

2

D20

D21

D22 D 23

4*BI

AD DSS

O9

DIS

DIOD

MA

IX

D30 D 31

D32

3

D33

A

21 # 4

DCOD

D

COLUM

N N

ABL

C OLUM NSN

SAM

PLIFIS

:

A3

C :IPSLC

(C S)

D AA OUPU

,.() L#, D,0$0 #- 16,/ &O 0$$0

The diode matri# is formed by connecting one diode along with a switch between each

row and column; 2or e#ample the diode D1 is connected between row and column

1;The output is enabled by applying logic 1 at the chip select CS) input; 6rogramming a789 means to selectively open and close the switches in series with the diodes; 2or

e#ample, if the switch of diode D1 is in closed position and if the address input is 0110,

the row is activated connecting it to the column 1; Also the sense amplifier of column1 is enabled which gives logic 1 output if the chip is selected CS + 1*; This shows that a

logic1 is storedat the address 0110; 8n the other hand if the switch of diode D 1 is open,logic 0 is stored at the address 0110;

Q.43 5#plain briefly, why dynamic 7A9s require refreshing4 (3)

Ans:ecause of the charge>s natural tendency to distribute itself into a lower energy3state

configuration )i;e;, the charge stored on capacitors leaC3off with time*, dynamic 7A9s

require periodic charge refreshing to maintain data storage;

1!


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R

+


Q.44 Draw the schematic circuit of an Analog to Digital converter using Voltage3to 2requencyconversion and e#plain its principle of operation; Draw its relevant Waveforms; (1!)

Ans:An0# /# D,,/0 C#n*$/$ Us,n V#/0/#$


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1%


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-


0'

*

C

1

0

'

,.1!() G0*-#$s #- V#/0/#$


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F

2

-

2 22 2 2 2

+

LSB

0 1 0 1 0 1 0 1 0

M SB

1

,.11(0) L#, D,0$0 #- &2& L0$ DHA C#n*$/$

X Y >

2

2 2 2 2

X ! Y ! > !

LSB M SB

,.11() 3 ,/ &2& L0$ DHA N/#$

The circuit is simplified using TheveninKs theorem; Applying TheveninKs theorem atXX', weobtain the circuit of 2ig; 2

; 2

2 2

X !Y ! > !

,.11() E


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Y > 2

2 2 ; 2

Y !> !

,.11() E>

> 2

3 ; 2

> !

,.11() E


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Q.46 What is meant by Wired3AND connection of digital ;)(;D*>+)A;-(;D*>

G,$ AND C#nn/,#n


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Q.47 What is the necessity of


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#, ,0$0 #- 4,/ # ;0$,/ 9$ s,n E?NO& 0/s

6arity checCer networCs are logic circuits with e#clusive / 87 functions; 5# 87 operation ofparity bit is a scheme for detecting errors during transmission of binary information;


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Q.4 What is a Decoder4 (ompare a decoder and a demultiple#er with suitable blocC diagrams;

(4)

Ans:

D#$H3 is

connected to the decoder;


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T9 #, ,0$0 #- 4,/ T,s/ &,n #n/$

2or decoding the count, two input AND ?ates are required Decoding logic for ' stage twisted

ring counter are

1$


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Q.51 5#plain the following characteristics for digital s; (8)

)i* 6ropagation delay )ii* 6ower dissipation

Ans:

' $ # ; 00/ , #n D 0H3 The speed of operation of a digital


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Ds,n &


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The delay times are measured between the $0 percent voltage levels of input andoutput wave forms; There are two delay times tphl, when the 8B6 goes from the high

state to low state and tphl, when 8B6 goes from low state to high state;

'#$ D,ss,;0/,#n: This is the amount of power dissipated in an


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the output;


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Ans:'$,#$,/ n#$ An encoder is a combinational circuit that performs the inverse operation

of a decoder;


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Q.57 What is a flip3flop4 Write the truth table for a clocCed E3F flip3flop that is triggered by the

positive3going edge of the clocC signal; 5#plain the operation of this flip3flop for the

following conditions;

output to be 1; (1!)

Ans:2lip /flop is single bit memory cell;


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1'


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Q.58 ow is it possible to maCe a modulo n

counter using N3flipflops4 Name the two types ofsuch counters; (4)

Ans:

9odule n counter counts total n distinguishable states we Cnow that n3bit can represent

nunique combinations for eg; 9od3" counter will count total " states and as "+)

* each

state will have combination of bits;Two types of such counters areH

9od " counter

9od 1! counter

Q.5


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Ans:

&0 A$#n C#n,/,#n:

En Fn G)n-1* output

0

1

01

0

0

11

G)n*

1

0G)n*>


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whole range of voltage in an interval is represented by only one digital value ;This error is

referred to an quantiation error which is because of process of quantiation;

Q.64 ?ive the details of e#cess code and gray code using four binary digits; (ompare the two codes;

(8)

Ans:

inary no 5#cess ?ray code

0 0 0 0 0 0 1 1 0 0 0 0

0 0 0 1 0 1 0 0 0 0 0 1

0 0 1 0 0 1 0 1 0 0 1 1

0 0 1 1 0 1 1 0 0 0 1 0

0 1 0 0 0 1 1 1 0 1 1 0

0 1 0 1 1 0 0 0 0 1 1 1

0 1 1 0 1 0 0 1 0 1 0 1

0 1 1 1 1 0 1 0 0 1 0 0

1 0 0 0 1 0 1 1 1 1 0 0

1 0 0 1 1 1 0 0 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

Ess 3 C#1;


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Ans:

5 9ode 9825T Depletion 9ode 9825T

01; No channel e#ists between rain and

source at V? + 001; (hannel e#ists at V? + 0 Min

fabrication n type impurity is diffused

between two n- regions

0; Threshold voltage is positive for

n98 Device;

0; Threshold voltage is negative for

n98 Device;

0; No current flows for negative V?Mn98

0; (urrent flows even for negative V?

Q.66 The clocC and the input waveforms shown below are applied to the D input of a positive edge

triggered D flipflop; Cetch the output waveforms; (6)

Ans:

As it is D 2lip 2lop at the positive edge ,output will be same as the input;

1'!


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Q.67 What are the specificationsB characteristics used by the manufacturers to describe a digital toanalog converter; 5#plain each one briefly; (8)

Ans:

T9 90$0/$,s/,s #- DHA #n*$/$ 0$(,)&s#/,#n: This is the smaller possible change in output voltage as a function of percentage of

full scale output voltage;(,,) L,n0$,/:


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2ollowing are the advantages of (98H

oth n3channel O p3channel devices are fabricated on the same substrate; @ow power dissipation, so more efficiency; ?ood noise immunity; igh pacCing density;Q.6 What is parallel adder4 Draw and e#plain blocC diagram for ' bit parallel adder; (8)

Ans:

y using full adder circuit, any two bits can be added with third input as carry;


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T$/9 /0

G ? > K ' C

0 0 0 0 0 1

0 0 0 0 1 1

0 0 0 1 0 10 0 0 1 1 0

0 0 1 0 0 1

0 0 1 0 1 0

0 0 1 1 0 0

0 0 1 1 1 1

0 1 0 0 0 1

0 1 0 0 1 0

0 1 0 1 0 0

0 1 0 1 1 1

0 1 1 0 0 0

0 1 1 0 1 1

0 1 1 1 0 1

0 1 1 1 1 0

1 0 0 0 0 1

1 0 0 0 1 0

1 0 0 1 0 0

1 0 0 1 1 1

1 0 1 0 0 0

1 0 1 0 1 1

1 0 1 1 0 1

1 0 1 1 1 01 1 0 0 0 0

1 1 0 0 1 1

1 1 0 1 0 1

1 1 0 1 1 0

1 1 1 0 0 1

1 1 1 0 1 0

1 1 1 1 0 0

1 1 1 1 1 1

Q.71 Describe the operation of parallel in parallel out )6


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Ans:

'0$0 In '0$0 O/


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A A A1 A0 d! d$ d' d d d1 d0 k #

3 3 3 3 3 3 3 3 3 3 3 333 3

0 0 0 3 3 3 3 3 3 3 0 k 0

0 0 0 3 3 3 3 3 3 3 1 k 1

0 0 1 3 3 3 3 3 3 0 3 k 0

0 0 1 3 3 3 3 3 3 1 3 k 1

0 1 0 3 3 3 3 3 0 3 3 k 0

0 1 0 3 3 3 3 3 1 3 3 k 1

0 1 1 3 3 3 3 0 3 3 3 k 0

0 1 1 3 3 3 3 1 3 3 3 k 1

1 0 0 3 3 3 0 3 3 3 3 k 0

1 0 0 3 3 3 1 3 3 3 3 k 1

1 0 1 3 3 0 3 3 3 3 3 k 0

1 0 1 3 3 1 3 3 3 3 3 k 1

1 1 0 3 0 3 3 3 3 3 3 k 0

1 1 0 3 1 3 3 3 3 3 3 k 1

G;% Draw and e#plain the function of dual slope analogue to digital converter; Derive the

equations used; (8)

Ans.Dual slope A to D converterH


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n

31 clocC pulses are applied; At the ne#t clocC pulse n

the counter is cleared and G becomes1; This controls the state of 1 which now moves to position 1 at T1, thereby connecting 3V7 to

the input of the integrator; The output of the integrator now starts to move in the positive

direction; The counter continues to count until V0 is less than 0; As soon as V0 goes positive atT, V( goes @8W disabling the AND ?ate;

1$


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Wave form of dual slope ABD convertor

The time T1 is given byT1 +

NT( where T1 is time period of clocC pulse;

When the switch 1 is in position 1, the output voltage of the integrator is given by

V0 + 0 at t + T

Therefore,T /T1 +

@et the count recorded in the counter be n at T therefore T/ T1 + n T( +

whichgivesn+

G;%' What is a 9ultiple#er Tree4 Why is it needed4 Draw the blocC diagram of a H19ultiple#er Tree and e#plain how input is directed to the output in this system; (1!)

Ans

/,;$ T$: The largest available 9:.


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There are two 1! to 1 9:. 91 and 9 having data inputs 0;;1$ and 1!;;1respectively; The selection lines are 1 0 , which are able to select one input

among 1! inputs; Now the strobe pin is used as fifth selection line that is if it is 0 than

one input among the upper 9:. is selected and if A + 1, than one among the data inputof lower 9:. is selected; The output of both the 9:. are 8 7ed;

G; %$ With the help of a neat diagram, e#plain the worCing of a weighted3resistor DBA c onverter;()

Ans

G,9/ &,s/$ DHA C#n*$/$:

N it digital input is applied to a register networC through electronic switch; Thiselectronic switch produces current < at 9 )corresponding to @ogic 1*,


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)ii* igned binary numbers (7)

Ans

(,) B,n0$ N$ Ss/The number of system with base or 7adi# two is Cnown as the inary Number ystem;

To represent the number, 0 O 1 are used; These are Cnown as bits;


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contacts;


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ere D8 input is not connected to any 8 7 gateR the binary output must be all eroes inthis case and all 0>s output is also obtained, when all inputs are eroes; This discrepancy

can be resolved by providing one more output to indicate the fact that all inputs are not

eroes;

T$/9 /0

In;/s O/;/s

D! D1 D2 D3 D4 D5 D6 D7

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

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De Lab Viva Questions 1