DDR SDRAMDDR SDRAMThe Memory of ChoiceThe Memory of Choicefor Mobile Computingfor Mobile Computing

Bill GervasiBill Gervasi

Technology Analyst, Transmeta CorporationTechnology Analyst, Transmeta Corporation

Chairman, JEDEC Memory ParametricsChairman, JEDEC Memory Parametrics

bilge@transmeta.combilge@transmeta.com

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Topics to CoverTopics to Cover

Market Segments & FragmentsMarket Segments & Fragments

Mobile Design ArchitecturesMobile Design Architectures

DDR and SDR Power AnalysisDDR and SDR Power Analysis

DDR SO-DIMM DetailsDDR SO-DIMM Details

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Segments & FragmentsSegments & FragmentsServers

Workstations

PC Segment 2

PC Segment 1

PC Segment 0

Mobile

Graphics

2H99 1H00 2H00 1H01

PC100 DDR

PC100 DDR

PC100 Rambus DDR

PC100

PC100

PC66 PC100 DDR

PC133

PC133

SS167 DDR (x16 and x32)

DDR

2H01

DDR

PC133

PC133

PC133

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RAM EvolutionRAM Evolution

320MB/s400MB/s

1000MB/s

2100MB/s

MainstreamMemories

FPEDO

SDR

DDR

Simple,incrementalsteps

DDR II3200MB/s

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Mobile DesignsMobile Designs

Two Sockets, T-stubTwo Sockets, T-stub 133MHz clock (for now)133MHz clock (for now) 2.1GB/s transfer (for now)2.1GB/s transfer (for now)

Mobile

Memory

Controller

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Butterfly SO-DIMMsButterfly SO-DIMMs

Perfect for notebookPerfect for notebook Especially thin & light!Especially thin & light!

Single access door to both SO-DIMMsSingle access door to both SO-DIMMs Internet Appliance: 1 or 2 SO-DIMMsInternet Appliance: 1 or 2 SO-DIMMs

CPUNB

SO-DIMM SOCKET

CPUSO-DIMM SOCKET

Motherboard

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Mobile Market RequirementsMobile Market Requirements

Long battery life Long battery life

Small form factorSmall form factor

End-user upgradeEnd-user upgrade

Low power, low heatLow power, low heat

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Power = CVPower = CV22f%f%

Factors:Factors: Capacitance (C)Capacitance (C) Voltage (V)Voltage (V) Frequency (f)Frequency (f) Duty cycle (%)Duty cycle (%) Power statesPower states

Keys to mobileKeys to mobile

design:design:

Reduce C and VReduce C and V Match f to demandMatch f to demand Minimize duty cycleMinimize duty cycle Utilize power statesUtilize power states

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Power: CapacitancePower: Capacitance

DDR capacitance 20% less than SDRDDR capacitance 20% less than SDR Tight circuit board designTight circuit board design Low parasitic socketsLow parasitic sockets

CapacitanceCapacitance

VoltageVoltage

FrequencyFrequency

Duty cycleDuty cycle

Power statesPower states

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Power: DDR vs SDRPower: DDR vs SDRCapacitanceCapacitance

VoltageVoltage

FrequencyFrequency

Duty cycleDuty cycle

Power statesPower states

0

0.5

1

1.5

2

Relative Watts

PC100

(3.3V)

1.2X

PC266

(2.5V)

1.0X

PC133

(3.3V)

2.0X

Lower Voltage means

Lower Power

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Power: DDR vs SDRPower: DDR vs SDRCapacitanceCapacitance

VoltageVoltage

FrequencyFrequency

Duty cycleDuty cycle

Power statesPower states

0

0.2

0.4

0.6

0.8

1

Relative MB/s per Watt

PC100

.31X

PC266

1.0X

PC133

.25X

Double the Bandwidth yet Lower Power

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Power: FrequencyPower: Frequency

Memory speed to match task demandMemory speed to match task demand Adjust memory clock for lowest powerAdjust memory clock for lowest power

Stream back to back operations on open Stream back to back operations on open bank, then closebank, then close DDR burst efficiency really shinesDDR burst efficiency really shines

CapacitanceCapacitance

VoltageVoltage

FrequencyFrequency

Duty cycleDuty cycle

Power statesPower states

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Power: Duty CyclePower: Duty Cycle

Caches minimize memory demandsCaches minimize memory demands DDR cuts burst time in halfDDR cuts burst time in half

Get back into low power state soonerGet back into low power state sooner

CapacitanceCapacitance

VoltageVoltage

FrequencyFrequency

Duty cycleDuty cycle

Power statesPower states

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Long Battery LifeLong Battery Life

Lowest power to perform a taskLowest power to perform a task Desktop performance expectedDesktop performance expected

Battery extending technologies:Battery extending technologies: SpeedStepSpeedStepTMTM

LongRunLongRunTMTM

SpeedStep and LongRun are trademarks of Intel Corporationand Transmeta Corporation, respectively

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Introducing LongRunIntroducing LongRunTMTM

CapacitanceCapacitance

VoltageVoltage

FrequencyFrequency

Duty cycleDuty cycle

Power statesPower states

The number 11 is a trademark of Spinal Tap

LongRunSpeedStep

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LongRunLongRunTMTM Technology Technology

Smart reprogramming of memory Smart reprogramming of memory frequency based on demandfrequency based on demand CPU monitors trends in CPU demandCPU monitors trends in CPU demand Automatically adjust CPU voltage,Automatically adjust CPU voltage,

CPU & memory frequency as neededCPU & memory frequency as needed Utilize all memory power statesUtilize all memory power states

Lowest power state possibleLowest power state possible Close banks between burstsClose banks between bursts

CapacitanceCapacitance

VoltageVoltage

FrequencyFrequency

Duty cycleDuty cycle

Power statesPower states

LongRun is a trademark of Transmeta Corporation

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LongRunLongRunTMTM Advantage AdvantageCapacitanceCapacitance

VoltageVoltage

FrequencyFrequency

Duty cycleDuty cycle

Power statesPower states

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Mobile Market RequirementsMobile Market Requirements

Long battery lifeLong battery life

Low power, low heatLow power, low heat

Small form factorSmall form factor

End-user upgradeEnd-user upgrade

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End User UpgradeEnd User Upgrade

DDR SO-DIMM StatusDDR SO-DIMM Status 63.6 x 31.75mm63.6 x 31.75mm 200 pins on .60mm centers, staggered200 pins on .60mm centers, staggered x64 and x72 (ECC) supportedx64 and x72 (ECC) supported JEDEC specification votes being countedJEDEC specification votes being counted

Multiple mobile designs in progressMultiple mobile designs in progress Samples in test now, production 1Q01Samples in test now, production 1Q01 Also great for small (Flex ATX) desktopAlso great for small (Flex ATX) desktop

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ConclusionsConclusions

Memory of choice for the futureMemory of choice for the future Enables mobile computingEnables mobile computing

Low power yields long battery lifeLow power yields long battery life Small form factor end-user upgradesSmall form factor end-user upgrades

Smart power management schemesSmart power management schemes

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SummarySummary

DDR is here todayDDR is here today Double the bandwidth at lower powerDouble the bandwidth at lower power Evolutionary design change over SDREvolutionary design change over SDR Applies to all market segmentsApplies to all market segments

Industry StandardsIndustry Standards Detailed complete data sheet & modelsDetailed complete data sheet & models Module designs on the webModule designs on the web Visit http://www.ami2.orgVisit http://www.ami2.org

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Thank YouThank You