dcld lab

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EXPERIMMENT NO.: - 1(A)Aim: - Verification of the truth tables of TTL gates, e.g., 7400, 7402, 7404, 7408, 7432,

7486.

Apparatus: - A digital trainer kit, 7400, 7402, 7404, 7408, 7432, 7486 ICs &

connecting wires.

Theory: - These all ICs are 14 pin ICs. Pin 7 is for ground & pin 14 is for +VCC.

(a) 7400 (NAND Gates): - This IC is used to verify NAND gate. Here the

input is at pin 1 & pin 2 & output is at pin 3. IC wills working if both I/Ps are low or

either of I/P is low. It will not work if both I/Ps are high.

Y = A.B

(b) 7402 (NORGates): - This IC is used to verify NOR gate. Here I/P are at pin

2 & pin 3 & O/P is at pin 1. IC will work both I/Ps are low. If either of I/P is high or

when both I/P are high IC will not work.

Y = A + B

(c) 7404 NOTGates): - This IC is used to verify NOT gate. Here I/P is at pin 1

& O/P is at pin 2. If I/P is low then O/P is high & vice-versa.

Y = A(d) 7408 (ANDGates): - This IC is used to verify AND gate. Here I/P are at pin

1 & pin 2 & corresponding O/P is at pin 3. If either of I/P is low, then O/P is high.

Y = A.B(e) 7432 (OR Gates): - This IC is used to verify OR gates. Here I/P are at pin 1

& pi 2 & corresponding O/P is at pin 3. If either of I/P is high, then O/P is high.

Y = A + B(f) 7486 (X-OR Gates): -This IC is used to verify X-OR gate. Here I/P are at pin

1 & 2 & corresponding O/P is at pin 3. O/P is low if both I/Ps are same else high.

Y = A + B

Y = AB + AB

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Diagrams of Different ICs: -

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Truth Tables for Different Gates: -

I/Ps O/Ps

A B NAND NOR AND OR X-OR

0 0 1 1 0 0 0

0 1 1 0 0 1 11 0 1 0 0 1 1

1 1 0 0 1 1 0

Procedure: -

1) Place the IC on IC Trainer Kit.

2) Connect the inputs to the input switches provided in the IC trainer kit.

3) Connect the outputs to the switches of output LEDs.

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I/Ps O/PsA NOT0 11 0

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4) Connect Vcc & ground supply to the respective pins of IC trainer kit.

5) Apply various combinations of inputs according to the truth table & observe

condition of LEDs.

Precaution:

1) Apply GND at pin no-7 &Vcc pin no -14 of all the IC,s

2) Insert and remove the IC;s with care

3) Connection should be neat &clean

4) Handle the trainer kit with care

5) Remove the ic with the help of Tweezer

Result:

Truth table of all the Logic gates have been verfied

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EXPERIMENT NO.: - 2(A)

Aim: - Verification of the truth table of Multiplexer IC74150

Apparatus: - Digital trainer kit, IC 74150(16:1 MUX), Connecting leads.

Theory: -

A multiplexer or data selector is a logic circuit that accepts several data I/Ps & allows only

one of them at a time to get through the O/P. The routing of desired data I/P to the O/P is

controlled by select I/P.IC74150 is multiplexer having four select lines A, B, C & D.

Other I/Ps of MUX are stroke & ta I/Ps (D0 – D15). Various Combinations of 0 & 1 on

select lines A, B, C & D give the corresponding O/P.The O/P is taken at pin no. 10 i.e. Y.

The O/P obtained is due complement of the I/P i.e. if data I/P D0 is 1 then O/P at Y will be

D0 i.e. 0

I/P = O/P

D0 = D0

The truth table shows this different combinations of 1 i.e. HIGH (H) & 0 i.e. LOW (L).

Diagram: -

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‘

Procedure: -






condition of LEDs.

TruthTable: -

I/Ps O/PStroke Select Lines Data I/P Y

A B C DL L L L L D0 D0

L L L L H D1 D1

L L L H L D2 D2

L L L H H D3 D3

L L H L L D4 D4

L L H L H D5 D5

L L H H L D6 D6

L L H H H D7 D7

L H L L L D8 D8

L H L L H D9 D9

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L H L H L D10 D10

L H L H H D11 D11

L H H L L D12 D12

L H H L H D13 D13

L H H H L D14 D14

L H H H H D15 D15

Precaution: !)Insert and remove the IC;s with care

2)Connection should be neat &clean

3)Handle the trainer kit with care

4)Remove the ic with the help of Tweezer

Result: Verification of the truth table of Multiplexer IC74150 EXPERIMENT NO.: - 2(B)

Aim: - Verification of the truth table of the De-Multiplexer 74154.

Apparatus: - DEMUX-74154, digital trainer kit & connecting leads.

Theory: - De-MUX transforms the reverse operation to that of a multiplier. It accepts a

single I/P & distributes it over several O/Ps. It is also a type of combinational logic circuits.

A basic De-MUX transforms the given data taken from a single source to several sources.

The function is realized by using decoders & the select I/P code, determines to which O/P

data will be transmitted. In short, a digital multiplexer is a device in which logic data from a

single I/P line are sequentially switched into several O/P lines.

Diagram: -

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Procedure: -






condition of LEDs.

Truth Table: -

S Data

A B C D Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y1

5

L L L L L L L H H H H H H H H H H H H H H HL L L L L H H L H H H H H H H H H H H H H H

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IC74154

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L L L L H L H H L H H H H H H H H H H H H HL L L L H H H H H L H H H H H H H H H H H HL L L H L L H H H H L H H H H H H H H H H HL L L H L H H H H H H L H H H H H H H H H HL L L H H L H H H H H H L H H H H H H H H HL L L H H H H H H H H H H L H H H H H H H HL L H L L L H H H H H H H H L H H H H H H HL L H L L H H H H H H H H H H L H H H H H HL L H L H L H H H H H H H H H H L H H H H HL L H L H H H H H H H H H H H H H L H H H HL L H H L L H H H H H H H H H H H H L H H HL L H H L H H H H H H H H H H H H H H L H HL L H H H L H H H H H H H H H H H H H H L HL L H H H H H H H H H H H H H H H H H H H L

Precaution:

!)Insert and remove the IC;s with care



4)Remove the ic with the help of Tweez

Result: Verification of the truth table of Multiplexer IC74154

EXPERIMENT NO. – 3(A)

Aim: -To verify a 4 bit binary adder using IC-7483.

Apparatus: - Digital trainer kit, connecting leads, IC-7483

Diagram:

Theory: -

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The half adder has 2 I/Ps A & B & produces O/P of SUM, So or CARRY C1. Full Adder

has three I/Ps & can produces O/P of SUM or CARRY or both SUM & CARRY. To

illustrate the working of binary adder let us add decimal no. 24. The binary equivalent of

13 is 1101 & of 11 is 1011. The equivalent binary addition is: -

1101

1011

1000 SUM

CARRY

The half adder adds 1 & 1 & gives a sum 0 & carry of 1. This 1 goes to first full adder

where 1, 1 & 0 are added to give sum of 0 & carry of 1 which goes to the next full adder

& so on. IN IC-7483, there are 14 pins out of which there are four I/Ps A0, A1, A2, A3 are

of A four bit B0, B1, B2 & B3 are of 4-bit binary I/P B. There are also 2 carry I/Ps & four

O/P pins.

Procedure: -






condition of LEDs.

Observations: -

Precaution:

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I/Ps O/Ps

A4 A3 A2 A1 C0 B4 B3 B2 B1 C1 I4 I3 I2 I1

0 0 1 0 0 1 0 0 1 1 0 1 1 1

0 0 1 1 1 1 1 1 0 1 0 1 1 0

1 0 1 0 0 0 0 0 1 0 0 1 1 1

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1)Insert and remove the IC;s with care




Result: To construct a 4 bit binary adder using IC-7483.

EXPERIMENT NO. – 3(B)

Aim-To realize half-adder using X-OR & AND gates.

Apparatus: -7486 & 7408 ICs, Digital Trainer Kit, Connecting Wires.

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Theory: - The half-adder is a circuit which is used to add two bits. The circuit accepts

two binary digits as it’s I/P & two binary digits as its O/P, sum bit & carry bit.

0 + 0 = 0; 0 + 1 = 1; 1 + 0 = 1; 1 + 1 = 0 with carry 1

The sum can be implements using X-OR & carry can be implemented using AND gate.

The Boolean expression for sum is

S = AB + AB = A + B

& for carry is

C = A.B

The circuit diagram is obtained using these equations.

Procedure: - 1) Verify the gates.

2) Make the connections as per the circuit diagram.

3) Switch on Vcc and apply various combinations of input

according to the truth table.

4) Note down the output reading of half adder and the carry bit for

different combinations of inputs.

Truth Table for Half Adder:

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I/Ps O/Ps

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

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Precaution:





Result:. To realize half-adder using X-OR & AND gates

EXPERIMENT NO. – 3(C)

Aim:-To design & verify truth table of full adder.

Apparatus: - IC-7486, IC-7400, Digital Trainer Kit.

Diagram: -

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Theory: -A full adder is an arithmetic circuit that has three I/P A, B & C. The two O/Ps

are sum S & O/P carry Coi which is produced & added to next stage. A circuit that produces

correct sum & carry is represented by following equations: -

S = ABC + ABC + ABC + ABC

= (AB + AB)C + (AB + AB)C

= (A + B)C + (A + B)C

S = (A + B) + C

& Coi = AB + BC + AC

= AC(B + B) +BC (A + A) + A.0

= ABC + ABC + ABC + AB

= AB(C + 1) + (AB + AB)C

Coi = A.B + (A + B)C

Truth Table of Full-Adder: -

A B Cin S Co

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

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1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Precaution:





Result:. To realize half-adder using X-OR & AND gates

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EXPERIMENT NO. 4

Aim: - To verify the Function table of 4 bit ALU( IC 74181.

Apparatus Required: -IC 74181, etc.

Pin detail & Function table:-

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Precaution:





Result:. To verify the Function table of 4 bit ALU IC 74181.

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EXPERIMMENT NO.: 5

Aim: - Design fabrication and testing of differentiator and integrator

circuits using OP AMP

Apparatus: - Dual-trace oscilloscope, Audio-function generator, ±15–V power supply,

351 op-amp, 100-kΩ resistor, 10kΩ resistors, 0.1-µf capacitor, 0.01-µf capacitor,

0.05-µf capacitor, 1.5kΩ resistor, 82kΩ resistors, 0.005- µf capacitor.

Diagram: -

Figure 1

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Figure 2

Procedure: -

For Integrator: -

1) Connect the circuit as shown in figure 1 (the pin no. indicated in this figure refer to

the 8 – pin mini DIP).

2) Set the function generator for a square wave output, and adjust its amplitude to 1 v

pp. Set the frequency of the square wave at 1 kHz initially.

3) Connect one channel of the scope at the input and the other at the output terminal of

the op-amp and slowly adjust the input frequency until the output is as good (linear)

a triangle wave as possible. Measure the frequency of the input wave form and

record it in Table 1. Also measure the amplitude and frequency of the output

waveform and record them in Table 1.

4) Repeat step 3 for C F=0.05 µf and 0.1 µf, one at a time.

5) Set the function generator to for a sine wave output. Adjust the amplitude of the sine

wave to 1V pp, and set the frequency at 1 kHz initially. Remove the 0.1 µf capacitor

and reconnected the 0.01 µf capacitor in its place.

6) Connect the one channel of the scope at the output terminal of the op-amp. Adjust

the frequency of the input until output is a negative going cosine wave. Make sure

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that the scope is triggered properly .Measure the frequency of input waveform and

record it in table 1. Also, measure the amplitude and frequency of the output

waveform and record them in Table 1.

For Differentiator: -

1) Connect the circuit as shown in figure 2, expect do not apply the signal from the

function generator yet.

2) Set the function generator for a square wave output, and adjust its amplitude to 1 V

pp. Also set the frequency of the square wave at 1khz.apply the square wave output

of the function generator to the circuit of figure 2 as Vin.

3. Connect one channel of the oscilloscope at the input and the other at the output

terminal of the op-amp. The output should be a spike waveform. If not, you may

adjust the input frequency to obtain a good spike output. Measure the frequency of

the input waveform and record it in table. Also, measure the amplitude and

frequency of the output waveform and record them in table.

4. Repeat step 3 for C1=0.01 µf and 0.05 µf, one at a time.

5. Next, set the function generator for a sine wave output. Adjust the amplitude of the

sine wave to 1V pp, and set the frequency at 1khz.Remove the 0.05 µf capacitor and

reconnect the 0.1- µf capacitor in its place.

6. Connect one channel of the scope at the input and the other at output terminal of the

op-amp. The output should be a positive-going cosine wave. If not, adjust the

frequency of the input until it is. Measure the frequency of the input waveform and

record in it table 2. Also, measure the amplitude and the frequency of the output

waveform and record them in table 2.

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Data Table: -

Table 1 (Integrator)

R1

( KΩ )CF

(µF)Input waveform Output waveform

Type Amplitude Frequency Type Amplitude Frequency

10101010

0.010.050.10.01

SquareSquareSquareSine

1 v pp1 v pp1 v pp1 v pp

`

Table 2 (Differentiator)

CF

(µF)Input waveform Output waveform

Type Amplitude Frequency Type Amplitude Frequency

0.10.010.050.1

SquareSquareSquareSine

1 v pp1 v pp1 v pp1 v pp

`

Precaution:





Result : testing of differentiator and integrator circuits using OP

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EXPERIMMENT NO.: - 6

Aim: - Design fabrication and testing of differentiator and integrator

circuits using OP AMP

Apparatus: - Dual-trace oscilloscope, Audio-signal generator, ±15V power supply, Digital

multi-meter, 741 or 351 op-amp, 1N914 or equivalent small signal diode, 10kΩ resistor,

10kΩ potentiometer, 4.7-kΩ resistor, 0.1- µf capacitor.

Procedure: -

1) Connect the positive clipper circuit as shown in fig. 1(a). Use a digital multi-meter

to set the reference voltage Vref = 1V.

2) Apply 2V pp sine wave at 1 kHz as an input and measure the input and output

waveforms using the oscilloscope.

3) Draw the measured waveform in figure 1(b).

4) Reverse the diode connections, and again measure the input and output wave forms.

Draw these waveforms in figure 1(c).

5) Next, disconnect the 10-kΩ potentiometer from the +15 V supply, and reconnect it

to the -15 V supply. Using the digital multi-meter, set –Vref=-1V.

6) Measure the input and output waveforms with the scope and draw these in figure

1(d).

7) Again, reverse the diode connections so that it will be in its original position.

Measure the input and output waveforms with the scope, and draw the measured

waveforms in figure 1(e).

8) Now, connect the clamper circuit of figure 2(a).Set Verf = 1V, and sine wave input

of 2 V pp at 100 Hz.

9) Measure the input and output waveforms using the scope and draw these in figure :

-2(b)

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10) Next, connect the 10-kΩ potentiometer across -15V instead of +15 V supply

voltage. Also, reverse the diode connections. Set –Verf =-1V and apply VIN = 2 V pp

sine wave at 100 Hz.

11) Measure the input and output waveforms using the scope and draw the waveforms i

Diagrams:-

Figure 1: - Positive Clipper Circuit. Input & output waveforms for (b) step 3, (c)

step 4, (d) step 6, and (e) step 7.

Figure 2: - (a) Clamper circuit. Input & output waveforms for (b) step 9, (c) step 11

Precaution: 1) Insert and remove the IC;s with care




Result: testing of differentiator and integrator circuits using OP

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EXPERIMMENT NO.: - 7

Aim: - Design fabrication and testing of free running multi vibrator at 1 KHz

and1 Hz using 555 with 50% duty cycle. Verify the timing from theoretical

calculations. 8. Design fabricates and tests a switch depouncer using 7400

Apparatus: - Dual – trace oscilloscope, Audio square wave generator, + 5 –V power

supply, NE555, 1N914 or equivalent, 2.5-MΩ potentiometer, 100-kΩ resistor, 20-kΩ

resistor, 12-kΩ resistor, 10-kΩ resistor, 10-kΩ potentiometer, 6.8kΩ resistor, 4.7-kΩ resistor,

two 3.3 – KΩ resistor, 2.2–kΩ resistor, 1-kΩ resistor, 10.0- µf capacitor, 1.0- µf capacitor.

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Procedure: -

1. Connect the monostable multivibrator as shown in figure.

2. Set the square-wave generator for 5v pp output at 50 Hz. Connect channels 1 and 2 of

the scope to the input and output terminals, respectively of the monostable

multivibrator. Make sure that switch SW 1 is in positive A ( pin 4 connected +5 v )

3. Measure the pulse width of the output waveform and enter the measured value in

table.

4. Momentarily switch off the generator and power supply, and replace the 12-kΩ

resistor.

5. Turn the generator and power supply back on and repeat step 3.

6. Complete table for remaining values of RA.

7. With Ra = 2.2 KΩ , C = 1 µf , and dual trace scope connected to the input and output

terminals of the multivibrator , place switch SW 1 in position . Observe the output

waveform .Enter the amplitude and frequency of the output waveform in table.

8. Return switch SW 1 to the original position A connect the series combination of the

10 KΩ resistor and the 2.5MΩ potentiometer between the control voltage pin 5 and

ground (across C 2 ) vary the 2.5 -MΩ potentiometer and simultaneously observe

the output wave form . In the table, enter the amplitude and pulse – width of the

output waveform for the minimum and maximum values of the potentiometer.

Remove the 10kΩ resistor and 2.5 MΩ potentiometer connected across C2.

9. Remove the wave shaping components C1, R1 and D1, from the circuit of the figure

and apply the 50 Hz square wave directly to the trigger pin 2 using the scope,

simultaneously observe the input and output waveforms. Enter the amplitude and time

period of input waveform in table. Also, enter the amplitude and time period of the

input waveform in table also; enter the amplitude pulse width of the output waveform

in table.

10. Connect the astable multivibrator of given figure 2.

11. Connect the scope to the output terminal and measure the frequency and duty cycle

of the output waveform. Enter the measure the value in 17 (a).

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12. Momentarily switch off the power supply and replace Rb of 1kΩ by 10KΩ. Turn the

power supply back on and repeat step 11.

13. Complete the table for the remaining values of Rb.

14. Switch off the power supply again, and replace the 3.3-kΩ value of Ra by a series

combination of a 1KΩ resistor and a 10KΩ potentiometer. Also, connect a 1N914

diode across Rb such that the anode of the diode is connected to junction of Rb and

Ra and the cathode to the junction two of Rb and a C. Connect the scope to the

output terminal of the astable multivibrator and a turn on the power supply . Adjust

the 10KΩ potentiometer until the output is square wave. Measure the frequency and

the duty cycle of the output wave form. Enter the total value Ra in table 17.2(b).

Data Table: -

Table 17.1(a)

C (µF) RA

(KΩ)

Output pulse width (s)

Measured Calculated

( tp= 1.1 RA C)

1

1

1

1

12

6.8

4.7

2.2

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Table 17.1(b)

Output waveform

Amplitude (V) Frequency

(Hz)

DATA

Table 17.1(c)

2.5 MΩ

potentiometer

setting

Output waveform

Amplitude (V) Pulse-width (ms)

Minimum ( oΩ )

Maximum (2.5 MΩ)

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Table 17.1(d)

Input waveform Output waveform

Amplitude

(V)

Time Period

(ms)

Amplitude Pulse-width (ms)

C

(µF)

RA

(KΩ)

RB

(KΩ)

% Duty Cycle Output frequency

Measured Calculated

100 RB

RA + 2RB

Measured Calculated

f=1.45

(RA + 2RB )C

0.01

0.01

0.01

0.01

3.3

3.3

3.3

3.3

1

10

100

3.3

Table 17.2(b)

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C (µF) RB (KΩ) RA (KΩ) % Duty Cycle

=100tp/T

Output frequency

0.01 3.3

Precaution:





Result : testing of free running multi vibrator at 1

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EXPERIMMENT NO.: - 9(A)

Aim: - Design and test of an S-R flip-flop using NOR/NAND gates

Apparatus: - IC-7400, connecting leads, digital trainers board, power supply.

Theory: - A flip flop is basically a bi-stable multi-vibrator having two stages (1 or 0).

The flip flop can be made to change state from one logic level to another. With an

appropriate toggle command, one of simplest storage device of digital information i.e. SET

RESEST (SR) flip flop & can be constructed using NAND gates. The O/P of flip flop is low

or high (0 or 1) & remains the same. If we want to change the O/P state of flip flop, we’ve to

trigger circuit by I/P called trigger. From the circuit diagram of SR flip flop, when clock is

high, operation of SR flip flop is as follows:-

1) If R = 0 & S = 0, O/P of gate N3 & N4 will be 1. The O/P of gates N1 & N2 depends

upon the value of Qn. We also say that O/P is latched or locked to its least value.

2) If R = 0 & S = 1, this will happen when a trigger is applied to S I/P. The O/P of N 3

will be 0 & N4 will be 1. Since one of I/P of N1 is 0, its O/P will be certainly high.

Consequently, both I/Ps of N2 will be 1 giving low O/P. Hence this state is referred to

a SET state.

3) If R = 1 & S = 0, this will happen when trigger is applied to R. The O/P of N3 & N4 is

1 or 0. I/P of N2 is 0. O/P is high. Hence this state is referred as RESET state.

4) If R = 1 & S = 1, will happen when a trigger is applied to both at same time & both

O/P will become 1 which is not allowed & therefore this condition is prohibited.

Diagram: -

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Procedure: -

1) Connections are made as per circuit diagram.

2) The truth table is verified for various combinations of inputs.

Truth Table: -

I/Ps O/Ps

Clk S R Qn Qn

0 0 No Change

0 1 0 1

1 0 1 0

1 1 Invalid Case

Precaution: 1)Insert and remove the IC;s with care




Result : test of an S-R flip-flop using NOR/NAND gates

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EXPERIMMENT NO.: -9(B)

Aim: - Verify the truth table of a J-K flip-flop (7476)

Apparatus: - Connecting leads, digital trainer kit, IC-7476 (Dual J-K Flip flop)

Theory:- JK flip flop differs from SR edge triggered flip flop in that Q-I/Ps is connected to I/P of

gate G1 as shown. The flip flops have 2 more inputs which are asynchronous. They are labeled preset

& reset direct. An active level on the clear I/P will reset it. To prevent any possibility of a "race"

condition occurring when both the S and R inputs are at logic 1 when the CLK input falls from logic 1

to logic 0, we must somehow prevent one of those inputs from having an effect on the master latch

in the circuit. At the same time, we still want the flip-flop to be able to change state on each falling

edge of the CLK input, if the input logic signals call for this. Therefore, the S or R input to be disabled

depends on the current state of the slave latch outputs.

Diagram:

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Procedure: -

1) Connections are made as per circuit diagram.

2) The truth table is verified for various combinations of inputs.

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Truth Table: -

I/Ps O/Ps

Pr Clr Clk J K Q Q

L H X X X H L

H L X X X L H

L L X X X H H

H H L L Q0 Q0

H H H L H L

H H L H L H

H H H H Toggle

H H H X X Q0 Q0

Precaution:





Result : Verify the truth table of a J-K flip-flop (7476)

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EXPERIMMENT NO.: - 9(C)

Aim: - Verify the truth table of a D flip-flop (7474) and study its operation in the toggle

and asyneronous modes

Apparatus: - IC-7474, connecting leads, digital trainer board.

Theory: - A flip flop is a basic memory element. It can store 1 bit. It is a bi-stable multi-

vibrator; the two stable states are denoted by 1 or 0. It has got complementary O/Ps Q

& Q i.e. Q = 1 & Q = 0 & vice-versa.

A flip flop has one or two controls I/Ps. D flips flop have one control O/P.

Diagram: -

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IC7474

(Dual D-type positive edge triggered flip flop with preset & clear)

Truth Table: -

Digital Electronics

I/Ps O/Ps

Pr Clr Clock D Q Q

L H X X H L

H L X X L H

L L X X H H

H H H H L

H H L L H

H H L X Q0 Q0

DAVIET

Precaution:





Result : the truth table of a D flip-flop (7474) and study its operation in the toggle and

asyneronous modes

EXPERIMMENT NO.: -10

Aim: - Operate the counters 7490, 7493 and 74192. Verify the frequency division at

each stage. With a low frequency clock (say 1 Hz) display the count on LEDs

Apparatus: - IC - 7490, IC-74193, Digital trainer kit, connecting leads.

T Precaution:





Result : test of an S-R flip-flop using NOR/NAND gates

Digital Electronics

DAVIET

Theory: - A counter is a circuit composed of flip flop in cascaded form, capable of

counting the number of clock pulses that have arrived at its clock I/P.

Initially, let Q4Q3Q2Q1 = 0000 when CLR I/P goes high the action begins. The flip

flops are in toggle mode. Now Q toggles for every negative edge of clock pulses

while the other flip flop toggles for negative edge of the Q O/P of preceding stage.

From the table shown O/Ps Q4Q3Q2Q1 pulses from the binary equivalent of the no. of

clock pulses arrive at I/P of logic level 1. Thus a four bit counter has 24 states. An n-

bit counter can count upto 2n-1 & it can have 2n states. A decade counter is one which

has 16 states.

The count sequence counts from 0 to 9 in fig. (2). In fig. (3), the circuit skips the

count from 10-15 & reset back to 0 after the 9th count. The circuit can be explained by

following steps: -

1) The counter is initially reset (i.e. Q4Q3Q2Q1 = 0000) using CLR line. Making CLR

line logic level 0, O/P of gate 1 is 0.

2) For the counter operation CLR is set to logic level, the counter then counts from 0 to

9.

The counter then reaches the tenth counter i.e. Q4Q3Q2Q1 = 1010 the O/P of gate

becomes 0, making the O/P of gate 1 zero thereby resettinsg the

Diagrams & Truth Table: -

Digital Electronics

DAVIET

Decade Counter

Procedure: - 1) Place the IC on IC Trainer Kit.





condition of LEDs.

Precaution:

1) Insert and remove the IC;s with care

Digital Electronics

DAVIET




Result : the counters 7490, 7493 and 74192. Verify the frequency division at each stage.

With a low frequency clock (say 1 Hz) display the count on LEDs

the counters 7490, 7493 and 74192. Verify the frequency division at each stage. With a low

frequency clock (say 1 Hz) display the count on LED

Digital Electronics

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