14
© CAP-XX Pty Limited 2020 | Tel +61 2 9420 0690 | www.cap-xx.com Page 1 of 14 DATASHEET GY SERIES SUPERCAPACITOR Revision 2.2, Mar 2020 The GY series of supercapacitors are cylindrical cells offering excellent value. They are available as single cells, or dual cell modules with a choice of cell balancing options. Features: High power output to support peak current loads On-board energy storage to handle power surges (high capacitance and energy density) Long cycle life Applications: Energy Harvesting for wireless sensors Peak power support for GSM/GPRS transmission Last gasp power for remote meter status transmission Peak power support for locks & actuators Peak power support for portable drug delivery systems Short term bridging power to ride through power Interruptions or for battery hot swap

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Page 1: DATASHEET GY SERIES SUPERCAPACITOR - cap-xx.com€¦ · 1 (mm) Cap (F) ESR Max @ 1KHz (mΩ) ESR Max @ DC (mΩ) Thickness X Width (mm) 120 Hrs Length DCL max @ (µA) 2 Mass (gm) Shrink

© CAP-XX Pty Limited 2020 | Tel +61 2 9420 0690 | www.cap-xx.com Page 1 of 14

DATASHEET

GY SERIES SUPERCAPACITOR Revision 2.2, Mar 2020

The GY series of supercapacitors are cylindrical cells offering excellent value. They are available as single cells, or dual cell modules with a choice of cell balancing options.

Features:

High power output to support peak current loads

On-board energy storage to handle power surges (high capacitance and energy density)

Long cycle life

Applications:

Energy Harvesting for wireless sensors

Peak power support for GSM/GPRS transmission

Last gasp power for remote meter status transmission

Peak power support for locks & actuators

Peak power support for portable drug delivery systems

Short term bridging power to ride through power Interruptions or for battery hot swap

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Revision 2.2, Mar 2020

GY SERIES DATASHEET

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Electrical Specifications

Single cells

Part numbering code

G Y N vvv dd mmm S ccc R

Model Cylindrical # of cells

Voltage Diameter

(mm) Length (mm)

Tolerance Capacitance

(µF) Lead format

1 2R7 = 2.7V 6C = 6.3

08 = 8.0 10 = 10 1B = 12.5 16 = 16 18 = 18

012 = 12 068 = 68 120 = 120

M ± 20% S +50% /-20% V +30% /-10%

Two digits + number of zeros. e.g. 155 = 1500000µF = 1.5F

R = radial S = 2 solder pins W = 4 Cu tabs

Rated Voltage: 2.7V

Temperature Range: -40C to +65C

Parameters measured at 25C

CAP-XX Part no. Cap (F)

ESR Max @ 1KHz

(mΩ)

ESR Max @ DC (mΩ) Dia (mm)

Length (mm)

DCL max @ 120

Hrs (µA) Mass (gm)

Radial Lead

GY12R76C012S105R 1 240 390 6.3 12 6 0.60

GY12R708012S105R 1 180 250 8 12 6 0.85

GY12R708016S205R 2 100 150 8 16 10 1.05

GY12R708020S335R 3.3 95 130 8 20 11 1.25

GY12R708025S505R 5 85 115 8 25 15 1.70

GY12R710020S505R 5 70 105 10 20 15 2.1

GY12R710020S705R 7 70 100 10 20 18 2.4

GY12R710025S705R 7 60 100 10 25 20 2.5

GY12R710025M106R 10 60 110 10 25 30 2.8

GY12R710030M106R 10 50 60 10 30 30 3.1

GY12R71B020M106R 10 50 60 12.5 20 30 3.4

GY12R71B030M156R 15 40 50 12.5 30 50 4.3

GY12R71B035M226R 22 34 45 12.5 35 60 5.3

GY12R716025M256R 25 27 40 16 25 60 7.2

GY12R716030M306R 30 20 30 16 30 70 8.2

GY12R718040M506R 50 18 20 18 40 75 12.7

GY12R718060M107R 100 10 15 18 60 260 20.7

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Dual Cell Modules

Part numbering code

G Y N vvv dd mm S ccc R B

Model Cylindrical # of

cells Voltage

Diameter

(mm)

Length

(mm) Tolerance

Cap.

(µF)

Lead & package format

Balancing

2 5R5 =

5.5V 6C = 6.3 08 = 8.0 10 = 10 1B = 12.5

12 = 12 68 = 68

M ± 20% S +30% /-10% V +25% / -5%

Two digits + number of zeros.

R,S,T = shrink wrap/radial – see dwg P,Q,O = plastic/radial – see dwg

R = Resistor* A = Active*

*R pair of balancing resistors, 0402 resistors, 100KΩ unless otherwise stated in the order, *A = CAP-XX active balancing circuit which draws < 1µA. For active balancing, lead alignment, L, must be “S” or “Q”.

Rated Voltage: 5.5V

Temperature Range: -40C to +65C

Parameters measured at 25C

CAP-XX Part no.1 Cap (F) ESR Max @ 1KHz

(mΩ)

ESR Max @ DC (mΩ)

Thickness X Width (mm)

Length (mm)

DCL max @ 120 Hrs

(µA)2

Mass (gm)

Shrink Wrap

GY25R50814S474RR 0.47 360 500 8 X 16 14 2 1.95

GY25R50818S105RR 1 200 300 8 X16 18 6 2.3

GY25R50822S155RR 1.5 200 260 8 X16 22 10 2.6

GY25R51022S255RR 2.5 150 210 10 X 20 22 20 4.2

GY25R51027S355RR 3.5 140 220 10 X 20 27 23 5.4

GY25R51B22S505RR 5 100 120 12.5 X 25 22 25 7.0

GY25R51B32M755RR 7.5 90 100 12.5 X 25 32 65 9.5

Plastic Package

GY25R50916S474PR 0.47 360 500 9 X18 16 2 6.6

GY25R50920S105PR 1 200 300 9 X18 20 6 6.0

GY25R50924S155PR 1.5 200 260 9 X 18 24 10 6.3

GY25R51125S255PR 2.5 180 210 11 X 23 25 20 9.5

GY25R51130S355PR 3.5 120 200 11 X 23 30 23 9.8

Notes: 1. Part numbers shown for lead orientation R, P and for balancing resistors, R. 2. Leakage current at rated voltage, without including the current drawn by the balancing circuit.

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Dimensions (mm)

GY1 Series Shrink Wrap Radial Lead 1F – 100F

ΦD P Φd

6.3 2.3 0.6

8 3.5 0.6

10 5.5 0.6

12.5 5.5 0.6

16 8 0.8

18 8 0.8

GY2 Series Shrink Wrap, 0.47F – 12.5F; L = R, S or T

Note: All modules ordered with the active balance option must be S type.

Cell dia. (ΦD)

D W P

Φd R S T

8 8 16 11.5 8.0 4.5 0.6

10 10 20 15.5 10.0 5.0 0.6

12.5 12.5 25 18.0 13.0 7.5 0.6

R Type:

S Type:

T Type:

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GY2 Series Plastic Package, 0.47F – 12.5F; L = P, Q or O

Note: All modules ordered with the active balance option must be Q type.

Cell dia. D W P

Φd P Q O

8 9 18 11.5 8.0 4.5 0.6

10 11 23 15.5 10.0 5.0 0.6

P Type:

Q Type:

O Type:

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Measurement of capacitance

Capacitance is measured at 25C using the method specified by IEC62391 shown in Fig 1. This measures DC capacitance. The capacitor is charged to rated voltage, VR, at constant current, held at rated voltage for at least 30 minutes and then discharged at constant current. The time taken to discharge from 0.8 x VR to 0.4 x VR is measured to calculate capacitance as:

C = I x (T1 – T2)/(V1 – V2)

Fig 1: GY12R708012S105R Capacitance measurement

In this case, C = 0.1A x 12.38s /1V = 1.24F, which is well within the 1F +50% / - 20% tolerance for a GY12R708012S105R cell.

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Measurement of ESR

Equivalent Series Resistance (ESR) is measured at 25C by applying a step load current to the supercapacitor and measuring the resulting voltage drop. CAP-XX waits for a delay of 200µs after the step current is applied to ensure the voltage and current have settled. In this case, for a GY12R708012S105R the ESR is measured as 140mV/1A = 140mΩ.

Fig 2: GY12R708012S105R ESR Measurement

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Measurement of Leakage Current

Leakage current is measured by holding the supercapacitor at rated voltage at 25C and charging

it through a low value current limit resistor, in this case, 28. After the current through the 28 resistor has decayed the supercapacitor is then held on charge with a higher value sense resistor, typically 1KΩ or 2.2KΩ, and measuring the voltage across this resistor to determine leakage current. The leakage current decays over time as shown in Fig 3 which shows the leakage current for 4 samples each of 10F, 15F, 22F and 25F supercapacitors. Leakage current is typically 1µA/F but the datasheet quotes the maximum values. Leakage current in the datasheet is quoted after 120hrs at rated voltage.

Fig 3: Leakage current measurement

0

50

100

150

200

250

300

350

400

450

500

0 20 40 60 80 100 120 140 160

Le

ak

ag

e C

urr

en

t(µ

A)

Time (Hrs)

Leakage Current 10F 1

10F 2

10F 3

10F 4

15F 1

15F 2

15F 3

15F 4

22F 1

22F 2

22F 3

22F 4

25F 1

25F 2

25F 3

25F 4

Leakage current measured by measuring voltage across a 28Ω resistor. Start with a lower value resistor to charge high C capacitors more rapidly.

Voltage measured across a 2.2KΩ resistor for an accurate reading once the leakage current has decayed.

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Variation in DC Capacitance and ESR with temperature

Figure 4 shows that DC capacitance does not vary with significantly over the operating

temperature range of -40C to +65C.

Fig 4: Variation in DC Capacitance over the operating temperature range

Figure 5 shows variation in DC ESR over the operating temperature range.

Fig 5: Variation in DC ESR over the operating temperature range

From Figure 5, ESRDC at -40C varies from 1.8x to 6.7x ESRDC at room temperature depending on

the part. ESRDC at 65C is ~75% of ESRDC at room temperature. The variation in ESR with

temperature is due to the change in the mobility of ions in solution in the electrolyte and the characteristics of the activated carbon used in that part.

0%

20%

40%

60%

80%

100%

120%

-40 -20 0 20 40 60

Cap

ac

ita

nc

e n

orm

ali

se

d t

o c

ap

ac

ita

nc

e a

t ro

om

tem

pe

ratu

re

Temperature(C)

Variation in DC Capacitance with temperature

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Peak Current

Peak current is limited by Vrated/(ESR + RL) where RL is the load resistance including parasitic resistance such as PCB traces. The current then decays and is given by :

[Vrated/(ESR + RL)].e-t/[(ESR+RL).C]

where t = time in seconds. At high peak current, the supercapacitor discharges rapidly so that self heating due to the high current is negligible. Table 1 Shows short circuit current for a range of supercapacitors initially charged to 2.7V at the instant the short circuit is applied and after 100ms. It also shows the temperature increase recorded due to the short circuit.

Table 1:

Capacitance (F)

Instantaneous peak current

(A)

Current after 100ms (A)

Temperature

rise (C)

25 58 44 2

15 40 26 2

10 40 26 3

5 20 15 1.5

3.3 20 13 2.8

2 15 10 1.5

1 15 7 1

In all cases the temperature rise is not significant. A one-time peak current pulse is only limited by the ESRDC + Load resistance, not by any thermal limitations.

The voltage drop when a constant current pulse of duration is applied =

VINIT – VFINAL= I.ESRDC + I./C

Where: I = constant current

= duration of constant current

VINIT = the initial voltage when the current pulse is first applied VFINAL = the supercap voltage at the end of the pulse

Re-arranging terms, the maximum current that can be sustained for a time , when the

supercapacitor is initially charged to rated voltage, VR, and discharged to VMIN, the minimum voltage that supports the given application =

𝐼𝑀𝐴𝑋 =𝑉𝑅−𝑉𝑀𝐼𝑁

𝐸𝑆𝑅𝐷𝐶+𝜏

𝐶

For constant power where I increases as V decreases to keep V x I = constant, there is no closed form solution. Use the Fixed Power worksheet in the file BackupPower_VoltageDecay simulator on the CAP-XX website to determine the min voltage after applying a constant power for a given time.

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Maximum Continuous Current

Continuous current flow into/out of the supercapacitor will cause self-heating, which limits the maximum continuous current the supercapacitor can handle. This is measured by a current square wave with 50% duty cycle, charging the supercapacitor to rated voltage at a constant current, and then discharging the supercapacitor to half rated voltage at the same constant current value. For a square wave with 50% duty cycle, the RMS current is the same as the current amplitude. Fig 6 shows the increase in temperature as a function of RMS current for various GY2R7 series supercapacitors.

Fig 6: Self heating with RMS current for various supercapacitors

Supercapacitors with C > 25F will have a lesser temperature increase than the curve for the 25F supercapacitor in Fig 6. From Fig 6, the maximum RMS current in an application can be

calculated. For example, if the ambient temperature is 40C, and the maximum operating

temperature for the supercapacitor is 65C, then the maximum RMS current for a 10F

supercapacitor should be limited to 3.6A, which causes a 25C temperature increase.

Effective capacitance (Ceff) Effective capacitance is the capacitance seen for short pulse widths. Due to the supercapacitor’s frequency response, for shorter pulse widths there will be less capacitance available than the DC capacitance. In Fig 7, consider the voltage drop due to capacitance after 10ms = 2.662V – 2.654V = 8mV. Therefore Ceff(10ms) = Discharge_Current x 10ms/Voltage drop(10ms) = 1.05A x 0.01s/0.008V = 1.3F. The voltage drop due to capacitance after 100ms = 2.662V – 2.636V = 26mV, hence Ceff(100ms) = 1.05A x 0.1s/0.026V = 4.0F. Fig 8 shows Ceff as a % of DC capacitance for the GY series of supercapacitors.

0

10

20

30

40

50

60

0 2 4 6 8 10 12

Te

mp

era

ture

ris

e (

C)

RMS Current(A)

Self heating due to constant RMS current

25F

15F

10F

5F3.3F

2F

1F

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Fig 7: Discharge pulse illustrating the concept of Ceff

Fig 8: Typical effective capacitance for GY 2.7V series supercapacitors

For any given pulse width, T, with a constant discharge current IDISCH, the voltage drop is given by:

Vdrop = IDISCH x ESR + IDISCH x T/Ceff(T)

Where Ceff(T) = DC capacitance x % at time T read from Fig 8.

Shorter pulses need less capacitance to support them, so the supercapacitors can support short pulses despite their slow frequency response.

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

2.6

2.62

2.64

2.66

2.68

2.7

-0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15

Cu

rre

nt

(A)

Vo

lta

ge

(V

)

Time (s)

1A, 100ms Discharge of GY12R701030S106R

Voltage

Discharge_Current

2.696V

2.662V

VESR

2.654V

2.636V

Slope = Discharge_Current/Ceff(10ms)

Discharge_Current = 1.05A

Slope = Discharge_Current/Ceff(100ms)

Rounded leading edge of the capacitance discharge due to the freq response of the supercapacitor

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0.0001 0.001 0.01 0.1 1 10 100

Pe

rce

nta

ge

of

DC

ca

pa

cit

an

ce

(%)

Time(s)

Normalised Effective Capacitance

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Balancing options

In many applications a voltage > 2.7V but ≤ 5.5V is required. For these applications 2 supercapacitor cells are connected in series in dual cell modules such as the CAP-XX GY2 series which is rated to 5.5V. These cells should have a balancing circuit to ensure that the cell voltages remain approximately equal or the cell with the lower C will have a higher voltage across it, causing it to age faster than its companion cell, hence losing even more C until it goes over voltage. This is a reason why a balancing circuit should aim to maintain the voltage across each cell equal, rather than just prevent over-voltage. As an example, if the dual cell module was at 5.0V and there was over-voltage protection circuits that prevented each cell from exceeding 2.7V, then module could have one cell at 2.7V and the other at 2.3V. The cell at 2.7V will age faster than the cell at 2.3V and will age faster than if both cells were held at 2.5V shortening module life. In the GY2 series modules there is a PCB connecting the 2 cells. This PCB can have one of two balancing options:

1. Option “R” as the last character in the GY2 series part number. A pair of balancing resistors are fitted, one resistor across each cell. The balancing resistors increase leakage current drawn by the module. Unless otherwise specified, 100KΩ resistors are fitted, increasing leakage current by 27.5µA at 5.5V.

2. Option “A” as the last character in the GY2 series part number. An op amp maintains the midpoint voltage = ½ the supercapacitor module terminal voltage. This solution maintains the midpoint voltage very accurately, responds more quickly as the supercapacitor charges and discharges and only adds ~1µA to leakage current.

If the application uses a supercapacitor charging IC that has an integrated supercapacitor midpoint balancing circuit, or there is a balancing circuit on the PCB, then order 2 x GY1 cells and place them in series. This makes the midpoint available to your balancing circuit. The dimensions of 2 GY1 cells placed next to each other are the same as a shrink wrapped GY2 series cell, refer to section 13, Dimensions.

Storage

CAP-XX recommends storing supercapacitors in their original packaging in an air conditioned room,

preferably at < 30C and < 50% relative humidity. CAP-XX supercapacitors can be stored at any

temperature not exceeding their maximum operating temperature but storage at continuous high temperature and humidity is not recommended and will cause premature ageing. Do not store supercapacitors in the following environments:

• High temperature / high humidity

• Direct sunlight

• In direct contact with water, salt, oil or other chemicals

• In direct contact with corrosive materials, acids, alkalis or toxic gases

• Dusty environment

• In environments subjected to shock and vibration

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Soldering

When soldering it is important to not over-heat the supercapacitor to not adversely affect its performance. CAP-XX recommends that only the leads come in contact with solder and not the supercapacitor body.

Hand Soldering:

Heat transfers from the leads into to the supercapacitor body, so the soldering iron temperature

should be < 350C soldering time should be kept to the minimum possible and be less than 4

seconds.

Wave Soldering

The PCB should be pre-heated only from the bottom and for < 60 secs with temperature ≤

100C on the top side of the board for PCBs ≥ 0.8mm thick. The table below lists solder

temperatures

Reflow Soldering

Infrared or conveyor oven soldering techniques providing the supercapacitor body is not subject to excessive temperatures. Do not use a standard reflow oven.

Transportation

All the supercapacitor cells in this datasheet store < 0.3Wh energy. The energy in watt-hours is calculated as: ½ x Capacitance x Vrated2/3600. The largest cell in this range is 100F, so stored energy = ½ x 100 x 2.72 /3600 = 0.101Wh. Under regulation UN3499 there is no restriction on shipping these supercapacitors. Their shipping description is “Electrical Capacitors” with harmonized shipping code 8532.29.0040.