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Note: This is a summary document. A complete document is available under NDA. For more information contact www.atmel.com/touchscreen.
Features• maXTouch™ Touchscreen
– True 12-bit multi-touch with independent XY tracking for up to 10 concurrent touches in real time with touch size reporting
– Up to 4.3 inch diagonal screen size supported with 10 mm “pinch” separation– Up to 10.1 inch support with correspondingly wider “pinch”
• Number of Channels– Up to 224 (subject to other configuration limitations)– Electrode grid configurations up to 20 X by 10 Y lines supported (subject to 30
total pins and a maximum of 14 Y lines)• maXTouch Touch Key Support
– Up to 32 channels can be allocated as fixed keys (subject to other configurations)• Zero Additional Part Count
– 16 X by 14 Y matrix (224 channels) implementable with power bypass capacitors only• Signal Processing
– Advanced digital filtering using both hardware engine and firmware– Self-calibration– Auto drift compensation– Adjacent Key Suppression® (AKS™) technology– Grip and face suppression– Reports one-touch and two-touch gestures– Down-scaling and clipping support to match LCD resolution– Ultra-fast start-up and calibration for best user experience– Supports axis flipping and axis switch-over for portrait and landscape modes
• Scan Speed– Maximum single touch >250Hz, subject to configuration– Configurable to allow power/speed optimization– Programmable timeout for automatic transition from active to idle states
• Response Times– Initial latency <10 ms for first touch from idle, subject to configuration
• Sensors– Works with PET or glass sensors– Works with all proprietary sensor patterns recommended by Atmel®
– Works with passive stylus• Panel Thickness
– Glass up to 3 mm, screen size dependent– Plastic up to 1.5 mm, screen size dependent
• Interface– I2C-compatible slave mode 400 kHz
• Dual-rail Power– Interface 1.8V to 3.3V nominal, analog 2.7V to 3.3V nominal
• Power Consumption– Idle 80Hz: <1.8 mW, subject to configuration– One Touch Active 80Hz: 3.9 mW, subject to configuration– Sleep: 4.5 µW
• Package– 49-ball UFBGA 5 x 5 x 0.6 mm, 0.65 ball pitch– 49-ball VFBGA 5 x 5 x 1 mm, 0.65 ball pitch– 48-pin QFN 6 x 6 x 0.6 mm, 0.4 mm pin pitch
maXTouch™ 224-channel Touchscreen Sensor IC
mXT224
Summary
9530BS–AT42–10/09
29530BS–AT42–10/09
mXT224
1. Pinout and Schematic
1.1 Pinout Configuration
1.1.1 49-ball UFBGA/VFBGA
1.1.2 48-pin QFN
A
7 6 5 4 3 2 17654321
B
C
D
E
F
G
A
B
C
D
E
F
G
Top View Bottom View
QT602240mXT224
AVDD
Y10
Y11
Y12
Y2 Y1
Y3
Y4
Y5
Y6
Y7
Y8
Y9
48 47 46 45 44 43 42 41 37383940
GND
Y13
GND
X15
X14
X8
X9
X10
X11
X12
X13
1
2
3
4
5
6
7
8
9
10
11
12
31
32
33
34
35
36
GND
AVDD
Y0
GND
X5
X7
X6
X4
X3
X2
X1
X0
30
29
28
27
26
25
VD
D
RE
SE
T
N/C
SD
A
SC
L
CH
G
VD
D
GP
IO2/S
CK
GP
IO0/S
YN
C
GP
IO1
GP
IO3/M
OS
I
AD
DR
_SE
L
13 14 15 16 17 18 19 20 24232221
mXT224
39530BS–AT42–10/09
mXT224
1.2 Pinout Descriptions
1.2.1 49-ball UFBGA/VFBGA
Table 1-1. Pin Listing
Ball Name Type Comments If Unused, Connect To...
A1 AVDD P Analog power –
A2 Y12 I/O Y line connection or X line in extended mode Leave open
A3 Y10 I/O Y line connection or X line in extended mode Leave open
A4 Y8 I Y line connection Leave open
A5 Y6 I Y line connection Leave open
A6 Y4 I Y line connection Leave open
A7 Y2 I Y line connection Leave open
B1 X8 O X matrix drive line Leave open
B2 GND P Ground –
B3 Y11 I/O Y line connection or X line in extended mode Leave open
B4 Y9 I Y line connection Leave open
B5 Y5 I Y line connection Leave open
B6 Y1 I Y line connection Leave open
B7 Y0 I Y line connection Leave open
C1 X10 O X matrix drive line Leave open
C2 X9 O X matrix drive line Leave open
C3 Y13 I/O Y line connection or X line in extended mode Leave open
C4 Y7 I Y line connection Leave open
C5 Y3 I Y line connection Leave open
C6 GND P Ground –
C7 AVDD P Analog power –
D1 X12 O X matrix drive line Leave open
D2 X13 O X matrix drive line Leave open
D3 X11 O X matrix drive line Leave open
D4 GND P Ground –
D5 X7 O X matrix drive line Leave open
D6 X5 O X matrix drive line Leave open
D7 X6 O X matrix drive line Leave open
E1 X14 O X matrix drive line Leave open
E2 X15 O X matrix drive line Leave open
E3 RESET I Reset low; has internal 30 k to 60 k pull-up resistor Leave open or Vdd
E4 GPIO1 I/O General purpose I/O Input: GNDOutput: leave open
49530BS–AT42–10/09
mXT224
E5 X1 O X matrix drive line Leave open
E6 X3 O X matrix drive line Leave open
E7 X4 O X matrix drive line Leave open
F1 VDD P Digital power –
F2 GND P Ground –
F3 SCL OD Serial Interface Clock –
F4GPIO3/MOSI
I/OGeneral purpose I/O /Debug data
Input: GNDOutput: leave open
F5 GND P Ground –
F6 CHG OD State change interrupt –
F7 X2 O X matrix drive line Leave open
G1 N/C – No connection Leave open
G2 SDA OD Serial Interface Data –
G3 GPIO0/SYNC
I/O General purpose I/OExternal synchronization
Input: GNDOutput: leave open
G4GPIO2/
SCKI/O
General purpose I/O /Debug clock
Input: GNDOutput: leave open
G5 VDD P Digital power –
G6 ADDR_SEL I I2C-compatible address select –
G7 X0 O X matrix drive line Leave open
I Input onlyO Output only, push-pullP Ground or power
I/O Input and outputOD Open drain output
Table 1-1. Pin Listing (Continued)
Ball Name Type Comments If Unused, Connect To...
59530BS–AT42–10/09
mXT224
1.2.2 48-pin QFN
Table 1-2. Pin Listing
Pin Name Type Comments If Unused, Connect To...
1 Y13 I/O Y line connection or X line in extended mode Leave open
2 GND P Ground –
3 AVDD P Analog power –
4 X8 O X matrix drive line Leave open
5 X9 O X matrix drive line Leave open
6 X10 O X matrix drive line Leave open
7 X11 O X matrix drive line Leave open
8 X12 O X matrix drive line Leave open
9 X13 O X matrix drive line Leave open
10 X14 O X matrix drive line Leave open
11 X15 O X matrix drive line Leave open
12 GND P Ground –
13 VDD P Digital power –
14 RESET I Reset low; has internal 30 k to 60 k pull-up resistor Leave open or Vdd
15 N/C – No connection Leave open
16 SDA OD Serial Interface Data –
17 SCL OD Serial Interface Clock –
18GPIO0/SYNC
I/OGeneral purpose I/OExternal synchronization
Input: GNDOutput: leave open
19 GPIO1 I/O General purpose I/OInput: GND
Output: leave open
20 VDD P Digital power –
21GPIO2/
SCK I/OGeneral purpose I/O /Debug clock
Input: GNDOutput: leave open
22 GPIO3/MOSI
I/O General purpose I/O /Debug data
Input: GNDOutput: leave open
23 ADDR_SEL I I2C-compatible address select –
24 CHG OD State change interrupt –
25 GND P Ground –
26 X0 O X matrix drive line Leave open
27 X1 O X matrix drive line Leave open
28 X2 O X matrix drive line Leave open
29 X3 O X matrix drive line Leave open
30 X4 O X matrix drive line Leave open
31 X5 O X matrix drive line Leave open
32 X6 O X matrix drive line Leave open
69530BS–AT42–10/09
mXT224
33 X7 O X matrix drive line Leave open
34 AVDD P Analog power –
35 GND P Ground –
36 Y0 I Y line connection Leave open
37 Y1 I Y line connection Leave open
38 Y2 I Y line connection Leave open
39 Y3 I Y line connection Leave open
40 Y4 I Y line connection Leave open
41 Y5 I Y line connection Leave open
42 Y6 I Y line connection Leave open
43 Y7 I Y line connection Leave open
44 Y8 I Y line connection Leave open
45 Y9 I Y line connection Leave open
46 Y10 I/O Y line connection or X line in extended mode Leave open
47 Y11 I/O Y line connection or X line in extended mode Leave open
48 Y12 I/O Y line connection or X line in extended mode Leave open
I Input onlyO Output only, push-pullP Ground or power
I/O Input and outputOD Open drain output
Table 1-2. Pin Listing (Continued)
Pin Name Type Comments If Unused, Connect To...
79530BS–AT42–10/09
mXT224
1.3 Schematic
1.3.1 49-ball UFBGA/VFBGA
N/CG1
Rc
GND
GND
GND
GND
GND
AV
DD
AV
DD
Rp Rp
VDD
RESET
SCL SCL
SDA SDA
GPIO1
GPIO2/SCK
GPIO3/MOSI
GPIO0/SYNC
I C-COMPATIBLE2
ADDR_SELI C-COMPATIBLE2
ADDRESS SELECT
CHG CHG
QT602240
VDD
MA
TR
IXX
DR
IVE
MA
TR
IXY
SC
AN
IN
X15
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
X19/Y10
G2
F3
E3
F6
G6
B2
C6
D4
F2
F5
E4
G4
F4
G3
B7
B6
A7
C5
A6
B5
A5
C4
A4
B4
A3
VD
D
VD
D
RegulatedVDD
100 nF 1 F!
F1
G5
RegulatedAVDD
100 nF 1 F!
A1
C7
X18/Y11
X17/Y12
X16/Y13
B3
A2
C3
G7
E5
F7
E6
E7
D6
D7
D5
B1
C2
C1
D3
E1
D1
E2
D2
* NOTE: Y10 to Y13 scan lines may beused as additional X drive lines inextended mode (a 100 mustbe added to each additional line).
" resistor
MA
TR
IXY
OR
X*
NOTE: Bypass capacitors must be X7R orX5R and placed <5 mm away from chip.
mXT224
89530BS–AT42–10/09
mXT224
1.3.2 48-pin QFN
N/C15
Rc
GND
GND
GND
GND
AV
DD
AV
DD
Rp Rp
VDD
RESET
SCL SCL
SDA SDA
GPIO1
GPIO2/SCK
GPIO3/MOSI
GPIO0/SYNC
I C-COMPATIBLE2
ADDR_SELI C-COMPATIBLE2
ADDRESS SELECT
CHG CHG
QT602240
VDD
MA
TR
IXX
DR
IVE
MA
TR
IXY
SC
AN
IN
X15
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
X19/Y10
16
17
14
24
23
2
12
25
35
19
21
22
18
36
37
38
39
40
41
42
43
44
45
46
VD
D
VD
D
RegulatedVDD
100 nF 1 F!
13
20
RegulatedAVDD
100 nF 1 F!
3 34
X18/Y11
X17/Y12
X16/Y13
47
48
1
26
27
28
29
30
31
32
33
4
5
6
7
10
8
11
9
NOTE: Bypass capacitors must be X7R orX5R and placed <5 mm away from chip.
* NOTE: Y10 to Y13 scan lines may beused as additional X drive lines inextended mode (a 100 mustbe added to each additional line).
" resistor
MA
TR
IXY
OR
X*
mXT224
99530BS–AT42–10/09
mXT224
2. Overview of the mXT224
2.1 IntroductionThe mXT224 (AT42QT602240) uses a unique charge-transfer acquisition engine to implementthe QMatrix™ capacitive sensing method patented by Atmel®. This allows the measurement ofup to 224 mutual capacitance nodes in under 1 ms. Coupled with a state-of-the-art XMEGA™
CPU, the entire touchscreen sensing solution can measure, classify and track a single fingertouch every 4 ms if required.
The acquisition engine uses an optimal measurement approach to ensure almost completeimmunity from parasitic capacitance on the receiver inputs (Y lines). The engine includessufficient dynamic range to cope with touchscreen mutual capacitances spanning 0.5 pF to 5 pF,allowing great flexibility for use with Atmel’s proprietary ITO pattern designs. One and two layerITO sensors are possible using glass or PET substrates.
The main AVR® XMEGA CPU has, under its control, two powerful, yet low power,microsequencer coprocessors. These combine to allow the signal acquisition, preprocessing,postprocessing and housekeeping to be partitioned in an efficient and flexible way. This givesample scope for sensing algorithms, touch tracking or advanced shape-based filtering. Anin-circuit reflash can be performed over the chip’s hardware-driven two-wire interface(I2C-compatible).
Overall, the mXT224 represents a step improvement over competing technologies, providing anear optimal mix of low power, small size and low part count, while offering unrivalled truemultitouch performance.
109530BS–AT42–10/09
mXT224
Revision History
Revision Number History
Revision AS – September 2009 Initial release for chip revision 1.4
Revision BS – October 2009 QFN package details added
119530BS–AT42–10/09
mXT224
Notes
9530BS–AT42–10/09
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© 2009 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR®, Adjacent Key Suppression® and others areregistered trademarks, maXTouch™, AKS™, QMatrix™, XMEGA™ and others are trademarks of Atmel Corporation or its subsidiaries. Other termsand product names may be registered trademarks or trademarks of others.