Data Types · Std_logic type is the data type defined in the std_logic_1164 package of the IEEE library. It defines a number of the states for a digital signal which helps in simulation

Data Types

Feb 2012 © Ruchi Rastogi Bani 1

VHDL supports a variety of data types and operators.

Users can define their own data types and operators in user defined packages.

There are three basic classes to define data objects in VHDL.

◦ signal - represents interconnections that connect components and ports.

◦ variable - used for local storage within a process. ◦ constant - a fixed value The data object could be a scalar or an array (one-

dimensional as well as multi-dimensional)


Lexical Elements 1. Identifier 2. Delimiters Object Classes 1. Signals 2. Variables 3. Constant 4. Alias

Types and Subtypes 1. Bit Type 2. Boolean Type 3. Character Type 4. Integer Type 5. Real Type 6. Physical Type 7. Std_logic Type Operators and Operator

Precedence 1. Logical 2. Relational 3. Shift

Identifiers are names that identify various VHDL

objects, procedures, functions, processes, etc.

Eight rules to follow ,

1. Can only contain alphabet, number and underscores.

2. Can be of any length as long as entire identifier is

appears within a line.

3. Identifiers will not be distinguishable if differing only

by upper case and lower case.

4. Can not have same name as the keyword.


5. Must begin with letter.

6. Underscore should not be at start, end and side by side.

7. Underscore should be used to increase the readability.

8. No space is allowed within a basic identifier.

Ex:

Intg-5 “-” is illegal

Zero_to_3 Legal

Valid User-defined identifiers:

COUNT, cout, C_out, A_B_C

Invalid User defined Identifiers:

2AB, H$B, LOOP, _ABC, DECODE_, A__B


Delimiters are symbols that have special meaning

within VHDL.

Ex: & ‘ * + - < > = ;

Compound delimiter refers to a sequence of two

delimiters.

Ex: <= := == /=



Lexical Elements 1. Identifier 2. Delimiters Object Classes 1. Signals 2. Variables 3. Constant

Types and Subtypes 1. Bit Type 2. Boolean Type 3. Character Type 4. Integer Type 5. Real Type 6. Physical Type 7. Std_logic Type Operators and Operator

Precedence 1. Logical 2. Relational 3. Shift

Used to represent value of a digital system

Values allowed are ‘0’ and ‘1’

Bit vector is expressed as a string of bit literals

enclosed in double quotes

Ex: ‘1’ , ‘0’, “1011”, X”7CEF” ( hex ), O”5673” ( octal )

Ex: signal valid : bit


Represents true or false value

Values allowed are ◦ true(TRUE,True) ◦ false(FALSE,False) Ex: signal busactive : boolean; ... busactive <= true; ... if (busactive and valid = ‘1’) then data_out <= din; valid_out <= ‘1’; end if;


The package STANDARD predefines a set of

character literals.

Character literals are enclosed in single quotes

Ex: ‘a’ , ‘A’, ‘1’ , ‘!’

An array of character literals is enclosed in double

quotes

Ex: “Warning : timing violation”


Defines a value with integers

Values are called integer literals

They can be either positive or negative

Exponents have to be integers

Ex: 3, -1, 47E23 , -4E-2, 345


architecture int_datatype of datatype is

begin

process

variable a : integer;

begin

a := 1; -- ok

a := -1; -- ok

a := 1.0; -- error

end process

end int_datatype;

Defines a value with real numbers

They can be either positive or negative

Values are called real literal

Exponents have to be integers

Ex: 3.23, -1.78946, 4.78E23 , -4.23E-2, 0.345


architecture real_datatype of datatype is

begin

signal a : real;

begin

a <= 1.0; -- ok

a <= 1; -- error

a <= -1.0E10; -- ok

a <= 1.5E-20; -- ok

a <= -1.0E10; -- ok

a <= 5.3 ns; -- error

end real_datatype;

Used to represent physical quantities like distance, current, time etc

Values are physical literals

The only predefined physical type time is defined in package STANDARD

Ex: signal tpd : time := 100 ns ;

The predefined function “now” returns the current simulation time

The range of a physical type is always in terms of its base unit

User can define their own physical types


type current is range -2147484638 to 2147484637

units

nA; -- Base Unit nano ampere

uA = 1000 nA; -- micro ampere

mA = 1000 uA; -- milli ampere

A = 1000 mA; -- ampere

end units;

Std_logic type is the data type defined in the std_logic_1164 package of the IEEE library.

It defines a number of the states for a digital signal which helps in simulation and debugging.

It is enumerated type and is defined as,

type std_logic is (‘U’,‘X’,‘0’,‘1’,‘Z’,‘W’,‘L’,‘H’,‘-’);

where

‘U’ - Uninitialized

‘X’ - Forcing Unknown

‘0’ - Forcing 0

‘1’ - Forcing 1

‘Z’ - High Impedance

‘W’ - Weak Unknown

‘L’ - Weak 0

‘H’ - Weak 1

‘-’ - Don't Care


Subtype is a type with a range constraint

Subtypes are compatible with their base type

Ex:

o subtype Count16 is integer range 0 to 16;

o subtype digit is integer range 0 to 9;

o subtype nanosec is time range 0 ns to 1 us;


An enumeration type defines a set of user defined

values consisting of identifiers and character

literals

The enumerated literals are listed in the

ascending order

Actual numeric value can be assigned to the

literals during compile time

Enumerated types allows us to use symbolic

values instead of numeric values

The boolean, bit, character etc. are some of the

predefined enumerated


Syntax:

Type enumerated_name is (enumerated literal1, literal2….);

Ex:

type color is (Red, Blue, Green);

type boolean is (false, true);

type Instruction is (add, sub, div, mul, load, store, or, and, not);

type stateMachine is (Idle, load, start, stop, store);


There are two composite type 1. Array : contains many elements of same type. 2. Records : contains elements of different type.

Arrays can be uni or multi dimensional. Array Declaration Syntax

type array_name is array (index range) of element_type; examples: type byte is array (7 downto 0) of std_logic; -- unconstrained array type word is array (integer range <>) of std_logic;


Declaration example

signal A : std_logic_vector(3 downto 0) := “1011”;

signal B : std_logic_vector(0 to 3) := “1011”;

signal C : std_logic_vector(6 downto 0);

A(3) A(2) A(1) A(0)

1 0 1 1

B(0) B(1) B(2) B(3)


A <= (‘1’, ‘0’, others => ‘1’); --aggregation A <= “1011”; A <= “10” & ”11”; --concatenation A <= ( ‘1’, ‘0’, ‘1’, ‘1’); A <= “101” & ‘1’; A <= ‘1’ & ’0’ & ’1’ & ’1’; C <= A & B; A <= C( 5 downto 2 ); --slicing A(2 downto 1) <= C(6 downto 5); A <= (others => ‘0’); A <= (1 => ‘0’, others => ‘1’ ); A <= (2 | 0 => ‘1’ , others => ‘0’); A <= (0 to 3 => ‘0’);


type array_name is array (index_range, index_range) of element_type;

eg:

type memory is array(3 downto 0, 7 downto 0) of bit;

-- 4 X 8 memory

For synthesis tools that do not accept multidimensional arrays , one can declare

two uni-dimensional arrays .

eg:

type byte is array(7 downto 0) of std_logic;

type mem is array(3 downto 0) of byte;

Initialization and reference

constant ROM: mem := (“10101010”, ”10101010”,

”10101010”, ”10101010”);

rom_bit <= ROM(3, 4); one_more_bit <= ROM(3)(0);


Declaration example:

type my_type is record is_valid : boolean; value : std_logic_vector(7 downto 0); when_updated : time; end record; signal my_element : my_type; assignment example:

my_element <= (is_valid => true; value => “00110011”; when_updated => now ); one more way of assignment:

my_element.value <= “10111011”;


Syntax

signal signal_name : signal_type [range_constraint] [:= int. value]

It connects design entities together and communicate

changes in value within a design.

Signals can be declared in,

1. entity - can be seen by all the architecture

2. arch -local to the architecture

3. package -globally available to the user of the package

4. as parameter in subprograms like functions & procedure.


A signal has three properties,

1. Type and Type attributes

2. Value

3. Time

Assignment is done by using “<=“ symbol.

Ex: c <= ‘1’;

Signal assignment is concurrent outside the process and sequential

inside process.

Signal updates can have a delay specified in their assignment

statements.

Ex: clk <= not clk after 10 ns;


Syntax

variable variable_name : variable_type [ range ] [:= initial value ]; e.g. : variable index : integer range 0 to 15;

variable count : std_logic_vector( 3 downto 0 ) := “0000”;

Variables are assigned values using the ‘:=‘ symbol.

Variables are the identifiers within a process or a subprogram. Their

visibility is limited only to its process or subprogram.


Variable assignment occurs immediately.

Variables have only type and value attached to it.

They don’t have a past history unlike the signal.

Requires less memory and result in fast memory.


A constant is an object whose value may not change.

Syntax

constant constant_name : constant_type [:= value ] ;

e.g. : constant pi : real := 3.147592;

constant datawidth : natural := 32;

It is used in the place of the value to make the code more readable.

The constant has just type and a value associated with it.

Constants are used to define data parameters ( buswidth, time delay

etc.) and lookup tables ( ROM etc)



Precedence Operator Class Operators

Low

Hi

Logical And or Nand Nor Xor xnor

Relational = /= < <= > >=

Shift sll srl sla sra rol ror

Adding + - &

Sign + -

Multiplying * / mod rem

Miscellaneous ** abs not

Logical Operators

◦ Logical operations on variables and signals of type std_logic, Bit and Boolean

◦ Can not be applied to any user defined data types.

◦ ex: y <= a and b;

Relational Operators

◦ Used in expression when it is necessary to compare the values of objects.

◦ Value returned by such expression is Boolean.

◦ May be applied to any built-in and user-defined scalar data object.

Adding Operators

◦ Concatenation produces a new one-dimensional array using two, one-dimensional array of the same data type.


Lexical Elements

Data Types and subtypes

Object Classes

Operators


Documents

Data Types · Std_logic type is the data type defined in the std_logic_1164 package of the IEEE library. It defines a number of the states for a digital signal which helps in simulation