P f' () c: ~?~:;~:; () T' Mod u 1 e

Manual Part No. 13220-91087

REVISED

JAN··· () 4····B2

DATA TERMINAL TECHNICAL INFORMATION

HEWLETT~PACKARD

Printed in U.S.A.

P f' 0 c (~~:; ~:; 0 7' M () d u 1 e

Manual Part No. 13220-91087

I~EVISED

JAN··· () 4····0t?

NOTICE

The inforMation contained in this dOCUMent is subject to change w:i.ti"lou"t notic€~.

HEWl..ETT····Pt-.CI{ARD t'\AI{EB NO WARI~ANTY OF ANY I{IND WITH '~EGAI~l) TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard shall not be liable for errors contained herein or for incidental or con~)f:~quf.·!n·t:i.al dat ... aqE~s in c()nn~:~ction with th(·! fUl'nis;hinq, ~)E~l'for'Manc:~?,

or use of this Material.

This dOCUMent contains proprietary inforMation which is protected by cop Y 7' :i. q h t. All r' i <;.I h t ~:; i:\ " f..~ r' f:'~ ~:) f:! r' v E! d . N () P a " t 0 f t h :i. ~:; cI 0 c lJ M ~;! n t JII\ a y b f:! photocopied or reproduced without the prior written consent of Hewlett­Pac k (;. r' d C () i'\ pan y .

Cop yr' iqh t c j.9S;:-!. by HEWI...ETT--PACKARD COMPANY

NOTE: Thi~:; docuME!nt is par't of th(~ ~?'6;:~XX DATA TERMINAl... pr'oduct ~:) 0! r' :i. f:·! s T f..! C h n i cal I n for' Mat ion P i:\ c: k a (J f! (H P j. 3 ;:~ ;:? () ) .

i.O IN"l"RODUCTION

The 02620-60087 Processor PCA perforMs the terMinal logic functions for the 2622A terMinal. Its operation is based on the Z80A Microprocessor and the National SeMiconductor 8367 CRT Controller (CRTC).

The control and I/O section of the Processor PCA provides control ~;> i q n a 1 ~:> , :i. n put / 0 u t put and d i~ tap roc (~s~:;:i. n(J fun c t j. 0 n~:; . The MeM 0 r' y section provides 16K bytes of dynaMic RAM for display MeMory, scratch pad MeMory and data buffers, and space for up to six 4K or 8K byte RUMs of which 32K are used for COMplete terMinal operation (8K of ROM optional with integral printer). The video control section provides all tiMing signals for driving the sweep circuitry and video logic as well as perforMing direct MeMory access CDMA) of display data. A detailed description of the operation of each of these sections follows :i. n ~:;ec t ion 3. 0 .

2.0 OPERATING PARAMETERS.

A SUMMary of operating paraMeters for the Processor Module is contained in tables 1.0 through 4.0

Table 1.0 Physical ParaMeters

=============================================================================== Par' t S i z e (I... x W x D) 1 W(~ i q h t 1

1 NUI"',IHH' 1 NOMf:·~nclatul'~~ 1 +/ .... 0.1 Inche~; 1 (Pounds> 1 1=============1==============================1=======================1========1 1 I 1 1 1 1 1 1 1 1 1 02620-60087 1 Processor PCA 1 12.3 x 10.9 x O.S 1 1.4 1

1 1 1 1 I 1 1 1 1 1 1 1

===============================================================================

1 :'5;:~:~O Pl' ()Cf.~<':;~;()l' Mod u Ie'

Table 2.0 Reliability and EnvironMental InforMation

1 ~5220 .... f/1 0 H'7 / () ~5 Rev JAN-()4····f32

================:========~====================================================== I I I EnvironMental: HP Class B I I I Restrictions: Type tested at product level I I I I==~===========~============================================================== I I Failure Rate: 3.71 (percent per 1000 hours) I ===================~======~====================================================

Table 3.0 Power Supply RequireMents - Measured (At +/-5% Unless Otherwise Specified)

===~=============================~=============================================

I +16 Volt Supply +12 Volt Supply +5 Volt Supply I -12 Volt Supply

I ill 0 MA @ 200 MA @ 2.0 A I @ SO MA

I I NOT APPLICABLE I I I I I ::: ::;: :~: :::: :::::::: :::: :::::::::::: :::::::: :::: :::: :;:: :::: :::::::: :'~::::: :::: :::: :::: :::: :.:::::: :::: :::: :::: :::: :::: :::::-.:::::: :::: :::::::: :::: ::: I =:::::::::::: :::: :::: :::::::: :::: :::::::: :.~::::: :::::::::::: :::: :::: :::::::::::: :::::::::".:: ::::::::::: :::: :::: = :::: = :::: :::: :::::::: = I I I I I 115 volts ac I 220 volts ae I I I I I ~ A I @. A I I I I I NOT APPL.ICABL.E I NOT APPLICABLE I ===============================================================================

13~~2 () P f' 0 C £~ ~:; ~:) () f' M () d u 1 e

Table 4.0 Connector InforMation

:1. 3~~~:~ 0 ···9108'7/04 R (::~ v JAN··· () 4···B;?

===~==========~===~========~===================================================

Connector Signal 1 and P in No. 1 NaM(~

1==============1================ J1 1

Pin ···1

.... 2

.... ~5

.... 4

· .. ··7

.... 8

·-9

1 I I 1 I 1 1 1 1 \ 1 \ \ I t 1 I

.... :1. 0 I I

.... :1.1 I I

.... :1. ;,? t I

"-L3 t

-14

· .. ·16

.... 1·7

-1t3 -·19 "-20 .... 21 ·-22 .. -;~3 -24 "-25 -26

PRINTER

PWI~ ON/FAIL

WRITE

Ai

DATA ()

DATA 1

DATA 2

DATA :5

DATA 4

DATA S

DATA 6

DATA 7

GND

PINT

AO

+SV +SV +SV +SV GND GND GND GNU GND

Signal I Description I

=============================================\ ** PRINTER ** Negative True, Printer Strobe

Negative True,Power On/Failing

Negative True, Write signal

Negative True, Fun~tion select bit 1

LSB - Negative True, Data

MSB - Negative True, Data

Set printer contrast

Negative True, Printer Interrupt

Negative True, Function select bit 0

Vcc Power

Power Retul'n

1. ~5~~2() Pl'OC(~SS)Ol' Module

13220-91.08'7/0S Rev JAN-()4-B2

Table 4.0 Connector InforMation (Cont'd) ===============================================================================~ I Connector Signal I and Pin No. I NaMe

Signal Description

\==============1================ ============================================== I J;:.~ I I 1 I Pin -·1 +5V \ -.~:~

\ -3 +SV \ -4 +12V I -S GND I -6 GND I .. _ ... _. __ ._ ... _ .. __ .......... _ ...... _.

** POWER SUPPL.Y ** +SV Power N/C +5V Power +1;':'~V Power R€~t ur'n f 01' Power Ret urn for' P ow(~r

I -'7 PWR ON/FAIL Negative True, Power On/Failing \ -8 -1.2V -12V Power I -9 BATTERY Positive Battery TerMinal I -10 1 BATRET I Negative Battery TerMinal I ........................................ - ............ 'I ._.- .... '''' .- ..... - ..................... -•• - .-.- I .. -.- - .-...... - .-....... - ............. _.-.- ........... , ..... - .......... -.- .- .. - .... '''' .-... _.- .... _ .... - ..... - ..... _._.- - -' -.. _.- I I J~3 1 I I ..... __ .. _. __ .... __ . I I Pin -1 HLFBRT I I -2 I \ -3 RETURN I \ ........ _ ........... _._._. I I --4 FUL.L.BI~ T \ \ -5 RETURN I \ -6 RETURN \ I I I .... 'J iJ'f~:'ifi)rf I \ -8 I HORDR I I ..... - ........ , _ .......... - ........ - ........... -. :1 .......... - ............ - ............... - ............. - •. -

\ J4 \ I I I I \ I I )

Pin .... 1 .... 2 · .. ·3 ... -4 · .. ·s · .. ·6 .... ·7 -·B

· .. ·9 .... 1 ()

····1.1 .... 12

\(EYO KEYj . KEY2 KEY:~

I<EY4

KEYS KEY6

KEYACT GNI> BELL.. +Sv

** SWEEP ** Negative true, Half Bright Video N/C Return for half bright twisted pair

Negative true, Full Bright Video Return for Video twisted pair Return for Drive signals

Negative True, Vertical Drive Horizontal Drive

** KEYBOARD ** Key Data (LSB) KE~y Data Key Data Key Data Key Data N/C K(~~y Dc:l ta )(ey Data (MSS)

Key Active (Status of key selected) Pow(~r Return Bell Line +5v Power

================================~===============================================

j. ~5;.:!.2 0 Pr'oc(::~ssor' Module

Table 4.0 Connector InforMation (Cont'd)

1 ~5220'-91 08'7/06 Rev JAN-()4'-B2

~=============================================================================== Connector Signal Signal

and pin No. I NaM€~ I Des;cr'iption ==============1================1==============================================

JS ** DATA COMM ** Pin .... j. N/C

-.;~ +SV +SV Pod P ow€~r "'~3 +SV +SV Pod Power .... 4 GN!) P()w(~r R(~tul'n ~~S GNl> P OWf-~r' I~et urn "~6 GND P()w(~r Return .. ~'J DeDi Rat(:~ S~~lect (23) .. ··8 Nit .. ~9 RD R (~c f:d. V (·~d l)clti:\ (3) .. ··10 Nit · .. ·1 i (,(:' .,,,:> Clf~dr' To Send (5) .... 12 DM Di:l ta S(?t Rei:ld y (6)

"~13 N/C · .. ·14 Nit .... 1 S SG Si~}na 1 Gr' 0 und (7) -··16 NIt .... j. 'J N/C .... 18 OCR1 Rinq Ind:i.cator (~~2 ) · .. ·j.9 +1;~V +12V Pod Power .... ;? 0 --1;:!V '-1~~\) Pod Power --21 SD Tr';HlSMl. t t(~d Data (2) .. -;;!;,? RS r~eqllest To Send (4) .... ;:?~~ TR Ready (20) "-;?4 Nit "-25 N/C .... 26 NIt -~27 N/C .. ··;,?8 N/C .. -29 N/C -~3 () Nit "-31 N/C "-3;.~ GND Return .. ··33 SHIEL.l) Shi(-.~ld Ground ( 1 ) .... ~34 N/C

(n) denotes the RS-232 pin nUMber

================================================================================

1 ~3~!'~~0 Pl' ()c€-~~:;s()r' M()d u le

1:3220·-91. OB'7 10'7 Rev JAN···· 0 4'-(32

3.0 FUNCTIONAL DESCRIPTION

Refer t() bl()ck diagraM (fig. 1), scheMatic diagraMs (figs. 2,3), tiMing diagraMs (figs. 4-8), COMponent location diagraM (fig. 9) and parts list (fig. 10) located in the appendix. The following describes the ()peration of the three Major sections of the Processor peA) control and lID, MeMory, and video c()ntrol.

CONTROL. AND I/O SECTION

Clock

A 25.7715 MHz crystal is attached to the CRTC which oscillates at the video d()t frequency. This is buffered by the CRTC and again by a 74LS244 (US11) to beCOMe DRCX, buffered dot rate clock. This clock is then divided by seven by the 748163 (Ub11) to produce 3.6816 MHz, which is shaped by Q4 and its associated circuitry to produce a SYMMetrical clock for the ZaOA, which has a zero level < 0.4SV and a one level> 4.4V. This clock is also divided by two to produce a 1.8408 MHz clock which the datacoMM chip (U613) uses to produce baud rates.

lOOA

The laOA Microprocessor perforMS the Major control and data Manipula­tion functions of the processor peA. It provides addresses and control signals to read and write data frOM and to both MeMory and I/O ports. It also responds to two externally generated interrupts, NNMI and NINT, which, when enabled, interrupt current execution and cause the ZaOA to branch to its interrupt service routine. The ZBOA also responds to a bus request signal, NBUSREQ, allowing the CRTC control of the systeM b u ~:)es .

At power up (or reset) the ZaOA begins executing instructions frOM prograM MeMory beginning at address OOOOH. A routine is executed which initializes variables and devices according to inforMation contained in non-volatile MeM()ry (CMOS) and perforMS a self test of ROM and RAM. If an error is detected a series of beeps are issued to the keyboard which indicate the failing ROM or RAM. After inintialization the prograM enters a Major 10()P responding to inputs frOM the keyboard and datacoMM por'ts.

Three 74LS244's (U4'7,U57,U511) buffer the address and control lines frOM the Z80A. The 1 of a decoder, U76, is used to separate prograM MeMory into six blocks, each BK bytes long. The addressed ROM is en­abled during a MeMory read by the TNRD and TNMREQ signals ()r during an instructi()n fetch by the NMl signal. Since the tiMe to read the data in an instruction fetch is less than that for a MeM()ry read, the NM1 signal was used to provide an early enable of the ROM allowing it to respond within the required tiMe. ROMs with access tiMes of 350 ns frOM address or 300 ns frOM enable are required t() run the systeM at full speed. [PROMs or ROMs with 450 ns access tiMes frOM address May be used by installing JUMper WS and reMoving JUMper W6, which causes the ZaOA to wait one cycle l()nger during instructi()n fetches. The quad latch U610 and ass()ciated gating provides the required wait signal to th~:~ ZBOA.,

13220 Processor Module

13220-91087/08 Rev JAN-04-82

3.1.3 I/O Ports

CMUS

The Z80A is capable of addressing 2S6 different input/output ports. I/O addresses froM the ZaOA appear on address bits AO-A7 and the accuMulator contents appear on bits A8-A1S. I/O addresses 0-7FH are used to access locations in the nonvolatile CMOS RAM, U73, where configuration data is stored. Since the CMOS RAM is not fast enough to respond within the I/O cycle tiMe a wait state is generated (by U6l0) each tiMe the CMOS RAM is accessed. Diodes CR6-CR8 ensure that around S volts is always on t~e CMOS supply pin. EMMitter follower Circuit, Q3, Makes sure that during a power off the CMOS is always disabled before the l80A buses beCOMe undefined and reMains so until buses beCOMe defined at power on. During power off the battery Maintains CMOS contents. If power on configuration is to be fixed, the COMS RAM May be replaced by an HM7611 PROM (however it Must be realized that the standard read/COMpleMent/write test for the CMOS self test would show a CMOS error since the prOM cannot be written).

DATACOMM

The SY6SS1 Asynchronous COMMunications Interface Adapter perforMS the parallel to serial conversion, error detection and baud rate generation functions required for serial data COMMunication. It appears to the laOA as four read only and four write only ports with address bit TA2 selecting the read/write function. This is done to COMpensate for the unique tiMing of the 6500 series devices. The SY6551 is selected by the rising edge of SELDC which is inverted frOM U24, the 1 of 8 decoder. The addresses of the SY6SS1 (U613) are AO-A7H.

The status inputs of the SY6SSl produce undesirable results and therefore are forced to their active low states while the necessary status signals are routed through another port. RS-232 line driver, USi4, and receiver, U614, are ~sed to convert frOM TTL levels to RS-232 levels (+-12V) and vice versa. TranSMitted signals are: send data (SD), terMinal ready (TR), request to send (RS) and optional control driver 1 (OCD1). Received signals are: receive d~ta (RD), data Mode (DM), optional control receiver 1 (OCR1), and clea~ to send (eS).

The datacoMM subsysteM operates in an asynChronous, full-duplex, point­to-point environMent. Characters May be tranSMitted and received siMultaneously (full-duplex) with character flow occurring over randOM tiMe intervals (asynchronous). To achieve hardware synchronization each character is fraMed by a start bit and a stop bit (2 stop bits at 110 baud). The addition of the fraMing bits for tranSMitted characters and the detection of fraMing bits for the received characters are done by the SY65S1. The parity (for error detection) of the character is selectable (in the datacoMM configuration Menu) and is also generated and detected by the SY6SS1 which reports errors (parity, fraMing, and overrun) to the ZaOA by Means of a status register in the SY6SS1 which is read when a character is received. The data tranSMission and reception rates are set by the ZaOA in an internal reqister within the SY6SS1.

13220 Processor Module

13220-91087/09 Rev JAN-04-82

Rates are selectable (in the datacoMM configuration Menu) frOM 110 to 9600 baud.

The datacoMM status inputs and outputs provide the necessary control lines to connect the terMinal to a host COMputer via a ModeM, or to provide direct hardware handshaking between the terMinal and host. At power-on the TR and RS lines are activated to indicate that the terMinal is ready. Upon receipt of a ModeM disconnect escape sequence (esc f) the TR line is brought inactive for .about two seconds to disconnect the ModeM. The presence of a ModeM connection is detected by DM which causes the indicator "LED" (an asterisk '*') to be displayed on the bOttoM center of the display. The CS signal frOM the host when active allows the terMinal to tranSMit data and goes inactive to halt tranSMission (the terMinal May ignore CS depending on datacoMM configuration). The state of OCDl is controlled by a configuration strap with its default state being low (inactive). This line selects the ModeM rate for dual speed ModeMS. OCRl is Monitored in datacoMM self test to detect the presence of the loopback test hood. All ModeM status lines are active high (+12V).

Upon receipt of a character frOM datacoMM the SY6SS1 generates an interrupt signal (NINT) to the lBOA. This causes the ZaOA to branch to the datacoMM interrupt service routine which reads the SY6S51 status, clearing the interrupt, and if no errors are present, inputs th~ character and places it into the datacoMM buffer in RAM. Characters for which errors (parity, fraMing or overrun) are present cause a delete character to be placed in the buffer.

Teus PORTS

The reMaining I/O ports are buffered to the ZaOA data bus by the biderectional bus driver, U37. This was done because of data bus loading. The signal TNRD selects the direction of the driver which is enabled for all I/O accesses except CMOS RAM and datacOMM.

U25 forMS the keystatus port located at address 80H. The keystatus port returns the status of 8 keys at a tiMe, which keys are deterMined by th~ keyboard/display port (U26). Four bits of the key address (colUMn address) are supplied by U26 (located at address B8H) and three More frOM the eRTC scan line outputs (row address). As the row address (scan line count) frOM the CRTC change, keystates are clocked into the keystatus shift register (a high bit indicating key active) frOM which they are later read. The colUMn address is increMented (during an NMI) for each of the first sixteen display rows thereby scanning the entire range of keyboard addresses.

j.~3;~~?O

P l' () C ~~ s ~:; () f' r1 0 cI u 1 e L3220-91 OB'7 /10 Rev JAN-'O 4···82

The keyboard/display port also enables a counter (U114) which counts horizontal sync pulses down to a bell frequency. The bell signal is the n ~:; hap (~d b Y (~4 a n cI i t~:; a ,;) soc i ate d c: i l' cui t . T I'\(~ reM a i n i n g bit S 0 f the I«~~ y boa l' d / d i ~; P :I. e) y POl" t d E-~ t (;H' Min E~ w h e t h £o~ r £om han c £o~ Men t <.!; will b e enabled and latches the signal which deterMines the blinkrate of blinking characters.

The NNMI (non-Maskable interrupt) signal to the ZaOA is Masked externally by a D flip-flop (half of U612). Port addresses B8H to 8FH select the NENNMI signal of the port decoder, clocking the latch while address bit TAO is the data input. This Means that a write to port 88H clears the latch, disabling NMI, while a write to port 89H sets the latch f.·H\i:\bling NMI.

The systeM status port, U36, located at address 90H allows the ZaOA to l' (.:~ a d t h E~ V (~H' tic alb 1 elf) k s i 9 n a 1 ( VB l. A N K) f 0 f' S Y n c: h l' 0 n i z i n g the s of twa l' e with the hardware. It also provides the inputs f~r the datacoMM status signals discussed above and also Monitors the integral printer s~atus.

The integral printer port at address 98H buffers data continuously to the printer bus, the data being latched in the printer when the NPRINTER signal is active. The processor writes data and COMMands to the printer via U16 and half of U1S. Printer control is specified by perforMing a write operation to the printer with address lines TAO and TA1 and data lines TDO-TD7 selecting the particular function. Printer status is read back frOM the printer on the upper half of U1S which is enabled for read operations frOM the printer port. The presence of the printer is detected by reading status frOM the printer and checking data bit TU1. TU1 will be low if the printer is not connected due to the pullup resistor R1. When the printer is connected to the processor Ji pin 11 is pulled low by the printer therby indicating connection.

Each character in the printer is forMed by 30 bytes of dot data, each pair of bytes being Made up of the dot data needed to forM the character if the character cell is scanned horizontally. The first byte in the pair indicates the state of every other dot while seven bits of the following byte indicate the state of the interstitial dots for the saMe horizontal scan. Thus fifteen pairs of.bytes correspond to fifteen horizontal scans of the character. In this way any character font in a 1S by 1S cell May be created. The printer buffers the data and translates the horizontal dot inforMation into vertical dots for printing. Each 30 bytes of dot data are followed by a print COMMand to print the character. The printer is also able to print in expanded and cOMpressed Modes.

The reMaining TBUS port located at ASH latches SOMe signals to the video section and one for the datacoMM section. The NMODEM signal is inverted to provide the clock for the latch (U3S).

13;:~~~ 0 Pr'ocf.~~:;~:;or Module

13~?20·M·91 OB7 /1.1 R (~v J AN .. - () 4·-S;:!.

3.2 MEMORY SECTION

~3. 2.1

The Z80A is capable of addressing 65536 (64K) bytes of MeMory data. The MeMory Map for this processor is'shown in the table below.

OOOOH

2000H

4000H

TABLE S.O TerMinal MeMory Map

NMI Service Routine S~~lf t€~st code

Function keys code l)at .. :lCOMM code Configuration code

Video intrinsics

U63 HK

16K

U6S ~~41<

6000H I Internal printer code I I U66 ~5:r:.!\( I ................ _. - ..................... M ..................... _ ..................... _ .............. M' ........ M ...... _ ..................... _. _. M ... M ......... _. _ ... M.

BOOOH I Not u~:;ed I (CRTC Map) I U67 I 40K I ......................................... - ............................ "" ............................ _ .............. -................................. _ .. M. .... .... .... .... ........ I

AOOOH I Not us(~d I I (CRTC Map) I I U68 I 4BK I ........................................ _. 'M' 'M'"'' ........ -' - ......................... - .................... _ .............................................................. _ .. I

CO () OH I DynaMic I~AM I I - buffers I I - display MeMory I I - stack I I - systeM variables I I I I ZDO : ZDt : ZD2 : ZD3 : ZD4 : IDS : ID6 : ID7 I I U41 : U42 : U43 : U44 : US1 : US2 : US3 : US4 I 64K

R€~a d· .. · on 1 y ·· .. M(-:~Mor y

As can be seen frOM the MeMory Map 4B K of address space has been allocated for read-onlY-MeMory (ROM). This MeMory contains the ZaOA prograMS which controls the terMinal operation. The ROM space is decoded into six 81< byte blocks by the 74LS138 decoder U76. A JUMper on address bit TA12 for each ROM allows the use of either BI< byte or 41< byte ROMs (or EPROMs). Note that BK bytes of address space is allocated for each ROM device even if it is only a 4K byte ROM (the upper 41< of that block is unusable).

l :·~;.:?;:!.o

P l' 0 C E~ S \;) 0 l' Mod u 1 e i :~220-9i OB'1 Ii,! R ~~ v J AN·M. 04···82

During an instruction (opcode) fetch the Z80A activates the NM1 signal to indicate that an instruction fetch cycle is in process. This signal is used to provide an early enable of the ROM being addressed during an opcode fetch therby allowing the use of ROMs with an access tiMe on 350 ns froM address or 300 ns froM enable (note that an opcode fetch is o~e clock cycle shorter than a MeMory read operation) without wait states. During a MeMory read frOM ROM the TNMREQ and TNRD signals go active G~nabling th(~ addl'f.~Ssf:~d ROM. Data is r'f.~quired valid app('OXiMatf.~ly 470 n ~:) fro M i:l d d l' (0 S s) the r e of 0 r' e n () wa its t ,1 t e s a r (-? r (~q u ire d for M (-? til 0 r y rea d s even when using 450 ns EPRUMs. Note that data is placed directly on thE' Z80t-1 dati-'l but:; without buP·fering.

RandoM-acceSS-MeMory

The RAM subsysteM has been designed around the MK4ll6-2 (or equivalent) 16K x 1 bit dynaMic RAMs. The MK4116-2 has a MiniMUM access tiMe of 150 ns and MiniMUM cycle tiMe of 320 ns. U41-44 and US1-S4 supply data bits TDO-TD7 respectively to provide the 16K bytes of RAM data storage.

Th(~ I~AM~;; ar'e acce~)~;(~d in thl'(;:O(-? ways: by the ZaOA for M~?MOr'y read or Wf':i. te clC:ce5se~) by the lBOA d U1' ing a l'efl'€-~sh c yc Ie and by the CI~TC during a DMA (direct-MeMory-access) cycle. Each of the three is discussed below. Refer to figure 6.0 for RAM tiMing.

ZUOA I~EAD/WI~ ITE

A Z80A access to RAM is initiated by lowering the TNMREQ signal at an address location between COOOH and FFFFH (RAM address range). Prior to TNMREQ going low the output of U77 would be high causing l's to be shifted through the shift register) U510, by DRCX. As TNMREQ goes low (TNRFSH is high) the output of U77 goes low also. As the clock occurs, O's are shifted through the shift register causing outputs QA-QD to go low in turn. This produces the RAM tiMing sequence as follows: NRAS­strobes in row address) MUX-changes RAM address inputs to colUMn address) NCAS-strobes in colUMn address and activates internal RAM circuitry to access the addressed cell. Data ouput on MDO-MD7 is vaild 100 ns frOM NCAS. When the Z80A is finish~d accessing the RAM the TNMREQ signal goes high and 1'5 are shifted through the shift register COMpleting the RAM cycle.

If the Z80A is perforMing d read operation the TNRD line is lowered along with TNMREQ (TNWR reMains high). The TNRD signal is gated with the output of U77 to enable the transparent latch, U62) during the read operation. When the NMUX signal goes high (as MUX goes low) the transparent latch beCOMes transparent) that is, the outputs follow the inputs) placing the RAM outputs on the ZBOA data bus. The latch outputs are enabled until TNRD and TNMREQ go high again.

For a write operation, the ZaOA lowers TNMREQ and places the output data on the data bus. ApproxiMately one Z80A clock later the TNWR line goes low strobing the data into the internal data latch in the RAM. The TNRD signal will be high disabling the transparent latch so RAM

13220 Processor Module

13220-91087/13 Rev JAN-04-82

outputs will never be on the l80A data bus. The cycle proceeds as for a read operation with TNMREQ going high, shifting 1'5 through the shift register to cOMplete the cycle.

zaOA REFRESH

The nature of dynaMic RAMs requires that each row Must be accessed every two Milliseconds to guarantee the contents of that row are held. The l8UA has a built-in refresh function to provide signals which perforM dynaMic RAM refresh without requiring extra processor overhead. The ZaOA Maintains a 7 bit MeMory refresh counter which is increMented following each instruction fetch. While the instruction is being decoded and executed the refresh counter is output on address bits TAU­TA7 while the TNRFSH and INMREQ signals are brought low, initiating the RAS-MUX-CAS sequence, refreshing that row. Since the TNRD and TNWR signals reMain high during the refresh cycle, the MeMory contents are unaltered and the transparent latch is not enabled so that the accessed byte does not appear on the bus.

eRTC DMA

Twice per video row, on scan lines 6 and 14 (if starting to count froM 0), the NBUSREQ signal to the ZaOA is activated to allow the eRTC to perforM DMA of enhanceMent and character data (see section 3.3 for More inforMation on the eRTC). The ZaOA responds to NBUSREQ at the end of the current Machine cycle by tristating its address and control lines and activating the NBUSAK line signalling that the bus is available and will reMain so until NBUSREQ is raised. The NBUSAK signal is inverted and buffered by U79 to provide both IBUSAK (active high) and TNBUSAK (active low, buffered). These signals are used to tristate the address and control buffers U47, US? and US11 and enable the video subsysteM for DMA action. TBUSAK enables the CRTC to place the lower 12 bits of the DMA address on the bus and enables the output of the transparent latch, U62, as well as enable the load signal to the shift register, USiO. TNBUSAK enables the upper four bits of the DMA address frOM U74 onto the bus and takes the recirculating line buffer, U38, out of the recirculate Mode (see section 3.3 for More inforMation on DMA addressing).

ApproxiMately four character tiMes before the start of the video row the line rate clock (LRC) output of the CRTC goes high enabling the load Signal to the shift register through the AND gate U71U. The load signal is derived frOM the character rate clock, LCGAX, which is delayed three dot tiMes through U410 in order to synchronize the RAM access to the video tiMing and guarantee sufficient address set up tiMe to the RAMs. 1he load signal causes RAS-CAS shift register, U510, to be parallel loaded on the next riSing edge of DRCX (dot rate clock). Upon loading, the shift register output QD is high and QA is low. THis condition forces the output of U77 to go low, causing a's to be shifted through the shift register. The next three occurances of DRCX produce

13220 Processor Module

13220-91087/14 Rev JAN-04-82

the NRAS-MUX-NCAS sequence, accessing the addressed byte. Data is available 100 ns froM NCAS, and, since NMUX is high, is placed directly on the Z80A data bus (U&2 is in transparent Mode), and therefore on the line buffer inputs. As the shift register output QD goes low the output of U77 is forced high and 1'5 are shifted through the shift register cOMpleting the RAM cycle. As MUX goes high again, NMUX goes low causing the data out frOM the RAM to be latched in the transparent latch, U62, where it is held until the next MeMory access. As LBCDEL (delayed line buffer clock) goes low the data is clocked into the line buffer U38. The CRTC increMents the address and the next load signal occurs 9 dot tiMes frOM the first, repeating the DMA cycle. In this way 80 sequential bytes of data are fetched frOM the RAM and loaded into the line buffer during the 80 active video character tiMes of the display.

Note: Although the shift register load signal is enabled four character tiMes before active video, the CRTC holds the starting address until active video and then increMents it during active video. In addition, the data is not clocked into the line buffer until the line buffer clock transitions low during active video.

On the last scan line of a character row, scan line 14, the CRTC lowers the LBRE (line buffer recirculate enable) output, taking line buffers U28 and U39 out of the recirculate Mode (where the output is shifted back into the input) thereby allowing data to be clocked into the inputs. During the DMA cycle of scan line 14, as characters are being output frOM line buffer U39 to the display, characters for the next row are fetched frOM MeMory and loaded into line buffer U39. At the saMe tiMe, as enhanceMent data is shifted out frOM U28, the data which was previously stored in the teMporary line buffer U38 (during the DMA cycle of scan line 6) is shifted into U28. In this way the display data for the next row of characters is loaded into the line buffers during the last scan line of the previous row as it is being displayed on the screen.

13;'?';~O Pr'oce~;~:;o~' Module

1 :5220-91 OB'l /1 S Re v J" AN-· 0 4·_·B2

VIDEO CONTROL SECTION

Ov~~rvi€o~w

The video control section generates the tiMing signals required to fetch character and enhanceMent data frOM MeMory and drive the analog sweep circuitry to display that inforMation on the CRT.

The display is divided into 26 rows of SO character cells each. Each character cell is a rectangle, 15 dots vertical by nine dots horizontal. Any character to be displayed is produced by selectively lighting the dots of the character cell which shape that character, leaving the others blank. Dots are left blank on either side and on the top and bottOM of the character cell to provide horizontal and vertical seperation between norMal characters. This is not true of characters which are continuous across the character boundary, such as line drawing characters (used to display forMS).

The analog sweep circuitry sweeps the electron beaM frOM left to right and frOM top to bOttOM across the display. As the beaM is swept horizontally it is turned on to produce a lighted dot and off to blank a dot position. As the beaM reaches the end of its scan a horizontal ~:;ync: ~:;i(lnal :i.s ~:;ent to the sweep c(~using the beaM to retf'aC(~

horizontally and begin sweeping again. During this tiMe the beaM is also being swept vertically. The COMbination of these two produces the display raster. As the beaM reaches the bottOM of the display a vertical sync signal is sent to the sweep causing the beaM to retrace frOM the bOttOM right to the top left corner. In this Manner the CRT display is written 60 tiMes per second (when configured at 60 Hz) or optionally SO tiMes per second (configured at SO Hz).

HOI~IZONTAL TIMING

After the 80th character position of a scan line the beaM is turned off (blanked) and reMains so as the horizontal retrace takes place. The beaM is enabled again as it reaches the position for the first character of the next scan. This blanking interval is called "horizonti:tl blanl<ing". This blanking (~llows tiM~? for th(o? t.)(~i~M to retracB 1 settle at the left side and begin tracing again. The portion oft h f~ ~~ can w h e f' (o? the b e (;\ M i~::, £~ n <":t b led i ~.) k now nat:; .. act :l v G~ v:l d eo" . T h ~? horizontal scan tiMe consists of the 80 character tiMes of active video plus 3S character tiMes of horizontal bl<":tnking for a total of 115 character tiMes per scan (1 character tiMe ~ 349 ns). This produces (;\ horizontal scan frequency of 24.9 KHz. The horizontal sync signal is activated 16 character tiMes before the last video character of the scan and is active for 7 character tiMes. It is produced in advance of the last character to COMpensate for the d f.~:I. a y il"l t h (o? ~:)W(o?(~P h 0 r i z 0 n tal c en t fn' in (1 c:i r cui t .

1.3~?';;'~0 P r' 0 c: f.~ ~:i ~) 0 f' Mod u I (~~

13220--9108'7/16 R (~ v JAN·- 0 4,-, 8 ~:.!

3.3.2

VERTICAL. TIMING

The 26 active video rows of the display each require 1S horizontal scans for a total of 390 active video scans. After the last scan line of the last row is displayed, a vertical blank signal is activated which disables the electron beaM during the vertical retrace tiMBo The beaM is enabled again on the first scan line of the first row. The duration of the vertical blank interval depends upon the occurance of the vertical sync signal which triggers the vertical retrace. This vertical sync tiMing depends in turn on the frequency with which the fraMe (one entire display) is refreshed. This fraMe rate May be configured to either SO or 60 Hz corresponding to the AC line frequencies in foreign countries or the U.S. to eliMinate display interference between the power supply and CRT. The following table describes the tiMing relationships between the vertical blank and vertical sync signals and the fraMe rate.

TABLE b.O FraMe TiMing

FraM(~ Rat(~

60 Hz I SO Hz

Delay after v. blank to v. sync (=1= scan lines) 0

v. sync width (I scan lines) 19 64

v. blank duration (I scan lines) 25 1.08

Total i scan lines per fraMe 415

Display MeMory addressing

Section 3.2.2 describes how the eRTC perforMS DMA to load the line buffers with character and enhanceMent data for display. Before it perforMS DMA, the CRTC Must be loaded with a starting address (called the row-start address). Each tiMe the CRTC is enabled it fetches 80 consecutive bytes of data starting frOM the row start address and places it into one of the recirculating line buffers.

The Z80A Maintains a table of 24 row start addresses in MeMory indicating the addresses of the first byte of character data for each of the character rows being displayed. Rows 2S and 26 contain the soft key labels and are always accessed frOM fixed locations. This table is actually a subset ~f a larger table which contains row-start addresses for all 48 display rows. The address of the first enhanceMent byte of a row is the first character byte address offset by 80.

13220 Processor Module

13220-91087/17 Rev JAN-04-82

3.3.3

Two scan lines prior to the NBUSREQ signal being activated a non­Maskable interrupt (NMI) is generated which causes the Z80A to branch to the NMI service routine after COMpleting the current instruction. Part of this service routine writes the row-start address for the next DMA into the rowstart register of the CRTC. The row-start address is written into the CRTC via the address bus itself. At the saMe tiMe, bits TA13 and TA12 are written into the 74LS17S U7S, which provides the upper bits of the RAM address for DMA. The ZaOA reads the row start address froM the table, adds the 80 byte offset for enhanceMent data DMA, Masks bits TA1S and TA14 to a 1 and 0 respectively and then writes a 02H to this address. By Masking bits TA1S and TA14 the address corresponds to a ROM location, which of course can't be written. These bits are decoded by part of U27 and U32, along with TNMREQ and TNWR to generate the register load signal (U412 pin 38) which latches the address into the eRTC and U7S for use during the next DMA cycle. The data bits ZDO and ZD1 select the register to be written to, in this case, the row-start register. The NMI service routine keeps count of the next row to be displayed in order to deterMine which row start address to send to the CRTC next. Since NMI can be disabled for an indefinate period (for exaMple during a RAM test) it is resynchronized every fraMe by reading the VBLANK signal through the systeM status port.

Character display

At any given tiMe the characters for the current row being displayed are held in the recirculating line buffer U39. The character codes output frOM this line buffer are resynchronized to the character clock through the octal latch, U310, frOM which they are sent to the character ROM, U311. This ROM contains the dot pattern for each scan line of each each possible character code. The standard character set uses the ASCII character code to represent the 128 possible characters in the set. The first 32 characters of the set are the control characters (escape, line feed, carriage return, etc.) while those reMaining are the alphanUMeric and punctuation characters. These 128 characters are represented in bits XO-X& with X7 being a O. These bits along with the scan line count beCOMe addresses for the dot data frOM the character ROM. Therefore, 11 address bits are required, Meaning that a 2K byte ROM May be used to contain the dot data for the standard character set. Bit X7 will then serve as an active low chip select.

By usinq a 4K byte character ROM, two COMplete character sets May be displayed. In this case bit X7 selects between the two character sets. Likewise an BK byte ROM can store four COMplete, 128 character, character sets. The scheMatic shows a signal frOM the enhanceMent data latch, U29 pin lS, which is inverted by U212, and sent to U311 pin 21. This signal is used to address the 8K byte character ROM on 4K boundaries. This COMbined with bit X7 frOM the character data latch allows selection of any of the four character sets. This upperMost address bit beCOMes a chip select for 2K or 4K character ROMs.

13220 Processor Module

13220-91087/18 Rev JAN-04-B2

As the character code and scan line count is issued to the character ROM an access tiMe delay is encountered before the dot data is available at the outputs. "he character ROM has an access tiMe of 300 ns, therefore one full character tiMe (349 ns) delay is introduced.

As the dot data beCOMes available out of the character ROM the lVSRX (load video shift register, buffered) signal is brought low which, on the rising edge of DRCX, parallel loads the data frOM the character ROM into the character shift registers U312 and U313 (and U314 as explained later). Since only seven dots per scan line are required for standard characters, seven dots are loaded frOM the character ROM (low output Means dot is lit) into the shift registers. The MSB (Most significant bit) output frOM the character ROM is latched by U1a (on LCGAX clock) and is used to enable the half-shift function (described below). The MSB output of U312 is connected to the serial input of U313 essentially forMing an 8 bit shift register. At the saMe tiMe that the seven dots are loaded into the shift register a 1 is loaded into the MSB.

The QD output of U313 goes to the character Multiplexor, U213. This Multiplexor selects one of several inputs to gate to the dot streaM. For a norMal scan (not half-shift) the Multiplexor select inputs will be 101 (C input is Most significant) selecting the DS input. As the dots are loaded into the shift register the first dot (which is high) appears on the DS input of the Multiplexor and is gated to the dot streaM. On each of the next 8 dot rate clocks (DRCX) dot data is shifted one bit position in the shift register and therefore to the DS Multiplexor input and to the dot streaM. Since the serial input of U312 is tied ~igh, a 1 (blank dot) is shifted into the shift register as the dot data is shifted out. Therefore at the end of the 9 dot clocks COMprising the horizontal scan for a standard character, the first and last dots are blanked (l's) with the 7 dots frOM the character ROM in between.

HALF-SHIFf

To avoid the "stairstep" appearance of characters with long diagonals, a feature known as "half-shift" is iMpleMented which allows and scan line of a character to be delayed by half a dot tiMe. This half­shifted scan line, placed between two norMal scan lines, fills in the diagonal as shown below.

X X

x X

x X

(no half-shift>

norMal half-shifted

norMal half-shifted

norMal half-shifted

x X

X X

X X

(with half-shift>

j.3;;!.;;!.() Pl' OCE-~S~:j.O(' ModulE'

1:5~!20-91 OB'7 119 Rev JAN .. -04 .... B2

In the ~:;tandard charact(~r set the MSH output of the char'actr~r ROM indicates that a scan line is to be halfshifted. This output is 1 C1 t c h ed (b y L.CGAX) in t 0 lJ 18 wh (~r' e it ish e Id f' 0 r the (7 dot~;) 0 f the character tiMe. The output of Uta is fed to the character Multiplexor select input A which, for half-shifted scan lines, selects the D4 input (U213 pin 1S). The QD output of the dot shift register, U313, is sent to the JK flip-flop, U413, clocked on the falling edge of DRCX, which perforMS the half-shift of the dot data. The output of this flip-flop goes to the D4 input of the character Multiplexor. The half-shift flip···flop i~:; pl'eSE-~t by l..VSRX at tl'H~ tit'te n~~w dots ar'e loaded :i.nto the ~:;hift r'(-?~J:i~;;t(~7'~:;.

CDPY BIT

SOMe alternate character sets such as line drawing set or large character set require all nine dots an a scan line to be active. This allows for continuous dots across a character boundary as required for drawing forMS, etc. on the display. In order to get nine dots out of eight outputs frOM the character ROM, a copy bit circuit is activated which copies the M5B output into the first two dots while the reMaining seven ROM outputs forM the reMaining seven dots.

The seven least significant ouputs frOM the character ROM are loaded into shift registers U312 and U313 as for standard characters. The MOst significant output is loaded into both the A and B inputs of shift register U314 at the saMe tiMe as the least significant seven bits. Thu"::;,. th€-~ MSB i<.:; "cop:i.E-~d" :i.n <':;hift reg:i.<.:;ter U3t4. The l'eMaining dots are brought frOM the QC output of U313 into the serial inputs of U314 thereby forMing a nine bit shift register with U312, U313, and U314. The QB output frOM U314 is then fed to the D7 and D6 inputs of the ch'::H'act0~l' Mult:i.plf.·~xo7' wh:i.c:h (-11'€'~ s(~lE-~ctf.~d whe-m thE-~ selfo:'ct inputs ar'e 11X. Note that the select A input is a don't care since half-shift cannot be used in these character sets.

The copy bit circuit 15 activated whenever the X'7 output of of the character latch U310 is active. ReMeMber that this bit is activated to select the second character set in a 4K character ROM or the second and f 0 lH' t h ~:; €-~ t ~.; ina n 0 K c: h cH' act EH' R (J M . The f i l' S t ~~ ;:.~ c: hal' act E-H' 0 fan y 0 f the four posible character sets are reserved for control characters and therefore copy bit is deactivated when these positions are accessed. '"his condition is decoded by bits XS or X6 being gated with X'7 (U34 and U1.12) to €,mablf.~ copy b:i.t only for the UppE-H' 96 chcH'actel'~:; of th(~ Sf.~t.

The result of this decoding is latched in the JK flip-flop, U413, which allows for the access tiMe of the character ROM. The flip-flop is clocked by the COMbination of LVSRX and DRCX which are gated together by U411. The output of the copy bit enable latch is then used to select the copy bit shift register output and gate it to the dot s t l' 0~a M .

j. ~5 ;.:~ ;:!. (} P 7' 0 C f..~ ~:; ~:; () ~' M Ii d u 1 (:"::0

1. :3;:?';~ 0 -(j t () B'7 I;:! () Rev J AN-· () 4····B;~

CUI<BOR

T h €:, q (-? n (~.~ in 8 t :i. 0 n () f t 11 e c U 7' r:; 0 r f 0 l' t h (o?, d i ~;; P 1 a y :i. s p ~~ l' f () r M (-,£I d b Y a cOMbination of hardware and <joftware. The eRTC activates its cursor output when the address of the character being fetched during a DMA c y c: 1 t·~ Mat c: h t:~ s t h 0~ c: () n t E' n t ~!; 0 f :i. t ~:; :i. n t f.~ (' n a 1 c \J l' SOl' add (' E~ 5 S (' f.-~ (.:) i s t (~~ (' . 1hi5 output is active for ali scan lines. The software Maintains and updates this register in the I:RTC corresponding to the position of the c u l' !:i () r () nth (o?, d:i. ~:; pIa y . I n 0 f' d (.? l' t () 1"', a 1< (-? t h (~~ C U l' 5 0 r' b:l. i n 1< t h (:? !:; () ·f twa r E~ i:\ 1. t (~~ l' nat f::O 1 Y w (' i t t:~ ~:; a IJ a 1 :i. d c lJ (" 5 0 l' add l' €.~ S !:) c\ n d t h (7~ nan i n IJ 1. a :i. d () n ~:.~ .

Th(::! CU1'!:;or' !:;:i.qnal> CUR> OU'!:put froM th(-:~ CRTC is gatf.~d w:i.th anothf::or' s:i.qnal, UL.Tli"IE) to pl'odlJC:(7~ d CU1'S;Ol' ~:;iqnal) NCUR> whic:h is activE~ on the 1. :3 t h !:; c: a n 1.:i. n E~ . l.l L TIM E :L~:> cI (~, cod f:~ d f r' 0 M the !!i C i:\ n l:i. n (-? c 0 u n t b Y U '3 <7 i:'\ n d U 4 1. i. . T h i ~:; f;; i q n a 1. i:\ 1 ~:; 0 <:~ n i:\ b 1. E-~ S t h f.-~ unci ~~ (' 1. :i n (7~ E~ f\ h c\ n c I;;~ , .... (~.! n t clu l' :i. n g t h t~ 1. ~~ 'l h !:i c: a n lin ~;~ .

In the norMal situation> where the cursor does not lie in an underline f i <-:-~ :I. d > t h E~ N C Lm s i q n e1 1. :i. !:) P l' I) P 0 q a 1; e cl t h l' U U 1 9 t 0 b ~\ COM e N C LJ R SO R w h i c h :i.~:; f(~~d to th(-'::o s(~l~?ct C input ()f th(~ char'act(~r Mult:i.p1(-?xor. This input q()<-:-~s, low to c':\c:tivatE~ the C:U1'S'H' which for nor'Mal chc':H'acter'<..:; (not copy b :i. t ) ~:; (-;~ 1 (-? C t s t h (-? D () (H' D :1. :i. n put s w h i c haT' e t:i e d 1 () W . T h :i.!!i c a u ~:i e~:i t h co? dot s t " €-~ c\ M t 0 b €-~ act:i V ~\ f 0 l' the 13 ~:) can l:i. n t:1 0 ·F the c: h i:\ l' iH: t €-H' P 0 sit :i. () n :l n w hie h t h (.;~ C U l' !; 0 T' 1 i (-:~ s . I n f~ f of' (-? C t t his 0 I~ , s t h E~ cur !:, 0 r wit h the character in the cell (a non'Mdestructive cursor). If the copy bit c :i. r" c u :i. t i !; act i v (~~ how (:? v (-:H' ~ the D ;:~ 0 f D ~5 i n put ~;; 0 f t h (o? C h a r a c: t EH'

M U 1 tip 1 ~~ x 0 r i:H' t:~ ~j. t:11 E~ c t £01 d . T 1\ E~ ~:; E~ i n put s, p l' 0 v ide t h ~~ i n v (-? r t (~~ d S EH' i (-:~ s 0 f dots frOM the copy bit shift register. In essence this inverts the 1.3th scan linB of the character when the cursor is active. This is n(-:~C(~S!:ic'H'y r'<~th(~l' than th(-:~ DR'c! cur!:ior used ab()vf.~ dUf-::O to th(-? fi~ct thi~t SOMe of the characters May ha~e all dots of the 13th scan line lit and th(::~ c:ur~)or' would n(o?v(~r' bf.~ !:;(7~(-?n.

l)(H STI~ETCH

Thf.~ dots al'(~ inver't(-?d by U~~L3~ the CI'\iH'iH:1;(-:H' Multiplexo1') to pr'ovide <~n active high dot streaM output. This dot streaM is then passed through (~j. and its a!a<..:;oc:i.ated cir'l::uitry which perfor'M~:; i~ "dot str'etch" function. This; dot stl'etch i~; u<.:,<-:~cI to pr'ovidt:~ an elongated ac:t:i.vf.~ d()t which has a More pleasant appearance when displayed. It essentially " f d t t f.-H\ !!, up" t h E~ d () t~, c: () ,v, p () s; :i. 1\ (;J i:\ c h a r' act t-:H' . The <.:; wit chi n q tiM e 0 f the transistor frOM saturation to cutoff is dependent upon the paraSitic collector to base capacitance and the external capacitor C2. This capacitance liMits the switching speed> essentially stretching the aMount of tiMe the transistor is active (in saturation). Capacitor C3 is included to cOM~ensate for paraSitic base to eMitter capacitance. Note that an inversion is int~oduced by this dot stretch circuit.

:t :.~ ;:.~ ? 0 Pl' ()c<:·~!:)so"{' Mod u l~:~

1. 3;:~;:! 0 -91 () 0'7 /;;~ 1 R~~ v J AN·-· 0 4·-·8~~

3.3.4

After being stretched, the dot streaM is gated through Ul10 where it picks up the underline enhanceMent and then is sent to the enhanceMent Multiplexor where the reMaining enhanceMents are added before sending the inforMation to the analog sweep circuitry.

EnhanceMent Display

A one-to-one correspondence exists between each byte of character data and each byte of enhanceMent data held in reCirculating line buffers U39 and U28 respectively. As a byte of character data is sent to the character ROM its corresponding enhanceMent byte is sent to the (:~\n han c: E~("'(7~n t ~:;(~~c t ion wh f.~r' (~ :i. t :i. ~:; d 0~C: 0 d f.~d iii n d 7' (-?c 0 ,..\b :i. n ed w:i. t h t h f.~ d (} t 5 t t, f:-~ i:\ M :i. nth f:~ ~:o n h i:\ n c t=~ M 0:0 n t M U 1 t i ~) 1 f~ X 0 l', U ~:? 1. 1. .

Of the eight available bits in the enhanceMent byte, only seven are u <.:~ (~:o d . F 0 U 7' 0 f t h f:-~ ~:; f.-~ > EN 0 ····E N ~3 > s; £.~ 1 f.~ c: t the b:l.:i. n 1< > i n v e f' s f.~ > U n d f..:O"{' 1. i n (~~ and halfhright attributes which May be selected in any COMbination. Bit EN 4 :i. s t h ~~ ~::. f.'~ t (~! n han c f.~ M (7:' n t b :i. t w h i c: h , w h ~~ n h i q h , c: a lJ s; £.~ £; ·t h ~:-~ cur r f.~ n t enhanceMent to be latched and held until another enhanceMent is set or until the end of the current row. Bit ENS is the end-of-line bit which causes the display to be frOM the current character to the end of the l' () W . I nth i ~:; way > t () C 1 f.-~ iH' the d i <.::. p 1. a y , end .... 0 f .. ··1 :i. rH? :i. s ~~ e tin the f :i. r' ~:~ t chi:) r'a c t <-:·~r' po s t ion () f (:~a c h r () w . H :i. t EN6 as d (-?SC r :i. b (~d a b () ve of 0 r MS t h (.~ M 0 S t s :i. q n :i. fie ant add r' ~~ s ~:~ bit f 0 l' a n B I( b Y t e c: h i:) f' act f.~ l' R () M .

As a character is latched into U31.0, six of the seven enhanceMent bits a l' (~:o 1 a .\: c h f.'~ d :i. n t () t h (~~ h (-:~ x 1 a t c h , U~?' (I . The s f.~ t E~ n han c: E~ M f.~ n t bit :i. s latched at the saMe tiMe (by LCGAX) into Ut8. At this tiMe EN6 is fed to the character ROM to provide the character ROM address selection for its correspondinq character. The attribute bits, ENO-EN3, output frOM U29 are then sent to the 74LS163, U210. In this Mode, with the count enable inputs P and T qrounded, it acts as a latch with a synchronous load and clear, This latch provides the additional character tiMe delay to COMpensate for the character ROM access tiMe. If the set f.H) h ":H·, C f:~ I"H:-:n t bit > EN 4, :i. ~:; I:) f.~ t, t h f.~ 0 lJ t P lJ t, U 1. Bpi n ~3, wi 11 q 0 1 () was the bit is latched. This activates the load input of U210 causing the attributes to be loaded on the next character clock (when the character ROM outputs are loaded into the shift reqister).

VIDEO (.:\ ITR IHUTES

The bli.nk dttribute output (U210 pin 14) is gated with the blinkrate ~:~:i.qnal {-'{'Of"'! thf.~ I/O ~:~(~~cti()n, which altE~rnatf~~:; hiqh and low to pr'oduce the active low NBLINK signal. When active the NBLINK signal allows () n :I. y t h f..~ CUT'~; 0 l' t 0 b (~~ d i ~:) p ".I. I:) y f.~ d , b ]. a n k :i. n ~~ t h f.~ c: hal' i:\ c: t f.~ l' . In t h i £) way, ·tl·,(~~ 1:11 :i.nl<:i.nq char'i:\c:t~:-~(·,·::; ar'f.! i~l t(~rnat(:~ly d:i.~:;plaYf.~d and bli!tnl(~?d. Thf:~

inverse bit siMply selects the inverted dot streaM (ALPHA) or cursor ~:;:i.qnal'::;, .

t ~:S ;:.~ ;~ 0 p (. () C f:~ ~:; ~:~ 0 (' j'yl n d u 1 E-!

j. 3;:?'~:! 0 -('}:I. () B'7 /;2;? R f:! V JAN ._. II 4 .... B;~

l h (:.! u n d (.;.!\'.' 1 i n (.~ ~:> :i. ~) n c':l 1 , U I... I N E , u n d (~i'" n 0 1" Mal con d :i. t ion ~:; ( w h (~n cur' ~; 0 r i ~:)

not active) siMply causes the dot streaM to be turned on during scan line :1.3. This is accoMplished by gating the UI...INE signal with ULTIME and u s :i. n q 't h (7! {' 0! S u 1 t ~:; t 0 f 0 ~' <:: (~! U t t () P :i. n B h i 9 h , thE! {' e b y act :i. vat in 9 t h Eo?

dot streaM. A probleM exists, however, when we want to position the c: \J r' ~:; () '{' i:\ t a c hal" act (:! l' P 0 ~:; i t i () n w h (~! 7' c! \J 1'1 d c! r' lin (-:! i ~:; a c: t i v~! . W (-:! can n 0

:I. () n q (~~ f' ,.., f:! 7' (::! ], y II D I~ II i n t IH~ C lH' S 0 f' i n tot h E-! dot ~:; t r' (~ i:\ M b (-:! c a u ~:; e i t 1 i e ~:; 0 n the saMe scan line as the underline and therefore would never be seen. What is done instead is that when both are active (NCUR is low and UlINE is high), neither the cursor nor underline appear on the display. This essentially disables the underline at the cursor position on the d i <:~ p :I. a y p (' () d u c :i. n <;) a b 1 ink in q h 0 1 (-:! :i. nth f:! un d (-:! r' 1 in e . The N C U I~ '::) i q n a 1 :i. s ~:~ (.:.! n 'l :i. n t 0 U ~. 1. (} pin 3 w h :i. c h, IrJ h E-! n act i v e , p f' E-! V (~n t s the u n d (-:! i'" lin e s i q n a 1 frOM being gnted into the dot streaM. At the saMe tiMe the ULINE signal is sent into U19 pin 1.3 disabling the NCURSOR siqnal which n () " M a J. ".I. Y q E-! n (~! T' a t f..! S t h €-~ c: U l' ~) () l' . T h lJ ~;, b () t h a 7' €-! dis a b 1 f:~ d .

T h (~~ :I. i:,\ S t i:\ ttl' :i. but E! ) hi:) 1 of b r' :i <;) h t , ~:; (.:~ 1. E-.' <: t s w h :i c h () f t h (~ v i cI (~ 0 in put son t h (~~ a n a :I. () q ~) W f..! (.:~ p b () a l' d w:i. 11 l" (.:.! C €-~ :i. v (~ the d () tin f () l" Mat j, 0 n . W hen the halfbriqht attribute is activated the dot inforMation is inhibited frOM th(-? NFUI...I...BRT output (whic:h (Jiv€-~s full intf:~n~;ity c:hal'ac:t~?r'~;» LJ1tc? pin b, by pulling Ut12 pin 4 low, and is enabled through U110 pin 8 which ~:)(::!I'\ d ~:) tI'\(~! act:i. V E! '.I. () W d () tin f () {' Ma t :i. () n () n NI-IAl..FHI~ T t () t h e-~ SWE~f:~p.

ENO"'ClF .... l.. I NE

Th(-:~ reMi:lininq (~~nhanCE~Mf:~nt bit, E.NS, pel"fOrMS the f.·~nd"-of'-line function. When set, this bit causes the display to be blanked frOM the current character position to the end of the row. This eliMinates the need to clear both character and enhanceMent data in order to c:lear the display. After being latched :in U29 the end-of'-line signal is gated tl'H' () ll<;) h LH 9 and U? "l 1: () :I. 0 W EH' t h (-:! c: 1 e-~ a l' in put () f lJ 21 () ( pin 1). T his causes the enhanceMents to be cleared at the next character c:lock (when (::hi:\l'ac:tEH' ROM output~:; ar'e loadE!d into the shift r'egi~;ter'..:;). At the saMe tiMe that U210 is cleared, the endof'-line Signal is latched into U17. The Q' output (U17 pin B) is sent back to the preset input to hold the flip-flop in the cleared state for the rest of the scan line. At the end of the scan line the NLRCX (inverted line rate clock) clears the flip-flop (clear overrides preset). At the saMe tiMe the Q' output, NEOlDEL, is qated through U1i1 to ac:tivate the BLANK signal. This signal blanks the display by deselecting the alpha input, only allowing the cursor siqnal to be gated to the sweep. The cursor signal is allowed since it is necessary to be able to position the cursor even in a blanked field. The Q output, U17 pin 9, is gated to the clear input of U21(} in order to hold the enhanceMent latch in the cleared ~:;tate.

13220 Processor Module

13220-91087/23 Rev JAN-04-82

The horizontal blank signal causes the dot streaM to be disabled (blanked) after the 80th character of a row and holds it in the blanked state until the first character of the next row. This signal is obtained by latching the LBCX (line buffer clock) signal in Uia pin 12 and adding a one character delay in U18 pin S. The LBCX signal is active high at the rising edge of lCGAX during the 80 active video characters. HBLANK is then gated through U27 to activate BLANK and disable NCUR. VBlANK and DISPOFF also blank the display in a siMilar fashion.

The last part of the video section to consider is the enhanceMent off circuit which allows the enhanceMent latches to be disabled. The ZaOA sets the ENHOFF signal, output froM U26, which is latched by the RECIRC signal into U17. The Q output (U17 pin S) is gated through U27 to clear U210 while the Q' output (Ui7 pin 6) clears U29. The RECIRC Signal goes low to take the line buffers out of the recirculate Mode as they are loaded during scan line 14. This Means that the ENHOFF bit is always latched at the start of a new row. The software can then change ENHOFF during an NMI service routine to disable enhanceMent display on the next row.

j, ~~ ~:~ ;.:~ 0 p (' () c f:'~ ~,; ~:) () (' f1 () d \J 1 fl.'

1 ~3;:! 20 - <'1 j. 0 B '7 / 2 4 I~ev JAN·_· 0 4--02

4.0 GLOSSARY OF SIGNAL NAMES

This section lists the signal naMes used on the scheMatic drawings, fiqur't:·~s t.n and ~:.~.O, along with i:\ bl'iE~f de~;cr'ipti()n of their us~?

Note: an 'N' prefix generally indicates an active low signal, otherwise the signal is active high) a 'T' prefix or an 'X' suffix indicate that the Signal is buffered.

t.a4 MHZ

3. bB 11HZ

60 HZ

t-,I...PHA

BArT+ or' BATT ....

BEL.L.

HI... ANI<

Hl..INI(Rt-,TE

CE

( '(:' ,,,,)

CTS

CUR

I>ISHI~(~

DISPOFF

DM

DRCX

The 1.84 MHz datacoMM chip clock

The 3.68 MHz l80A clock

Sets the video fraMe rate, low = SO Hz

video dot streaM after dot stretch

con n E~ c t :i. 0 n t () t h E-~ b c\ t tel' y + «() I' .... ) tel' .". MinaI for CMOS backup during power off

() U t p \J t s i 9 n a 1. t () d l' i vet IH:~ lo:~ y b (h:ll' d b t:~ 11

inhibits the ALPHA dot streaM frOM being sent to the sweep circuitry

alternates at the blinkrate for blinking character attribute

detects presence of loopback hood

c:l(?ar' .... to-·~:)~~nd ofl'OM host COMputer'

TTL level clear-to-send

c: lH' ~. 0 r' 0 u t put f r () M C F~ T C

inhibit DMA

blank entire display

detect ModeM connection

clot r'ate-~ clock

TTL. level detect ModeM connection

13220 Processor Module

ENO-EN?

ENHOFF

ENNMI

HBLANK

ICH

INVERSE

KEYO-KEY6

LBCDEL

LBCX

LCGADEL

LCGAX

LVSRX

MDO-MD7

MUX

NBLINK

NBUSREQ

NCAS

NCMOSREQ

NCUR

NURSOR

NENNMI

NEOLDEL.

NFULLBRT

NHALFBRT

enhanceMent data bits froM line buffer

inhibit enhanceMents

clock for NMI Mask latch

horizontal blank signal

TTL level detect datacoMM test hood

select inverse video attribute

keyboard row/coluMn scan outputs

delayed line buffer clock

line buffer clock

13220-91087/25 Rev JAN-04-82

delayed latch character generator address

latch character generator address

load video shift register

RAM data outputs

selects between row and clouMn address for dynaMic RAM

select blink attribute

request bus control for DMA

colUMn address strobe for RAM

enable CMOS for read/write

one line cursor signal

cursor active without underline

select NMI latch

end-of-line signal

norMal intensity video output

half-intensity video output

i. ~5;.:?';!' () Pro t:: E~ ~.) 5 0 l' i'"\ 0 d u 1 e

NHSYNC

NINT

NI<EYACT

NI<EYDISP

NKEYBTAT

NI...RCX

Nt1UX

NNMI

NPFAIL

NPRINTER

NI~AS

NRESETA

NRESETB

NSELDC

NBYB9TAT

DeDi

(JeRi

PINT

PULLUP

RD

RECII~C

RESET

R(" ,;)

91)

horizontal synchronization

key active (depressed) on keyboard

select (clock) keyboard/display latch

enable keystatus port

line-~ l'ate-~ clock

opcode fetch Machine cycle

select (cLock) ModeM/display latch

clock RAM output latch

non-Maskahle interrupt (video)

power fail signal frOM power supply

printer select signal

row address strobe for dynaMic RAMs

power-on reset, driver A

power-on reset, drivel" B

datacoMM port select

systeM status port select

optional control driver 1, datacoMM

optiorhll control r'ece:iv(~r i., datacoMM

printer i~terrupt status

COMMon pullup resistor

receive data, datacoMM

line buffer recirculate enable

printer reset Signal

request to send, datacoMM

send data, datacoMM

i. :3(~;!' 0 -9108'7/26 Rev JAN···· 04····82

1~3;:!';:!O

Pr'oc:t:~~:)~~or Module'

BEL DC

SHIEL.D

SMEM 0 -·SMEMS

Tr..O···TA1S

TBUBAK TDO·-TD'7

TNBUSAI<

TNM'~E(~

1 Nr~ 1)

TNI~FBH

rNWI~

TR

UL.INE

LH ... T IME

VBl..ANI(

VSYNC

datacoMM chip select

signal ground, datacoM~

shield (earth) ground, datacoMM

ROMO-ROMS chip enable

address bits 0-15

bus acknowledge, ZaOA tristate buffered data bus

active low bus acknowledge

zaOA MeMory request

MeMory or 1/0 read select

dynaMic RAM refresh active

MeMory or lID write select

terMinal ready, datacoMM

select underline attribute

active on scan line 13, indicates scan line for underline or cursor display vertical blank signal

vertical synchronization signal

1:3220-9108'7/27 Rev JAN-()4-82

character code address to character ROM

lallA data blJ~~

.....

-0 :;;0 o n r'1 (J) (J) o :;;0

aJ r o n ~

CJ -:D G) :;;0 :D :3

PROCESSOR

AND CONTROL

APDRESS BUS MEMORY

ROM/RAM

r----------·-----'l I/O DECODE : AND BUF'F"£R

)1\

1 TDATA BUS

. .. .. _. --" .-.-.,-- .~ .. -' ....

( PRJNlD ~ I/O

KErRET )

(KEXSCAN ,

( BELL

EROM HOST),

( TO HOST : DATACOMM

~---.-- - .i

Fl.(]ure 1

VIDEO SUBSYSTEM

Blocl< DiagraM JAN-04---B2

<[1/48,2140 VBLAI\I~

<C)IID NHSYNC

«I/Ie ORC.X

« 1//0 ",LR(X

VIDEO J3-B J3-7 J3-f,

"~I.

1J114"lS"~~+ +5\1~~O r r 1 KEYBOARD

J4-1 J4-2 J4-3

I

" /0 12.

NOTES: I. JUI"PE~ SHOWN IN STD CONFIG..

RI3 Ril

HSY Ne iJJ-l:!~,_+_--"I ~"I1C;»"'O=---+-+--'-l' j>='8--< .......... __ t'I(C!.:~""5:..:;ylK.=>:i I 17" LSI"

"SYNC. i-+ I 2 VSYNC. 3 /I 13 +5'1 ---./VW ...... --_--------,

vee.. 1-'!'\Q<=......+--~1"........,~ .. 5v '17 u2I+ ,--_______ +_H-------------,":· 15Iq~J31J)r-;----,-+---,"',Jjp--------, '17

UZ/+ R2b

~~7 - +5Y I, ..J K C.L.4'i-=-O __ +-_+---,!'o~CL. 51'1S"

t 14-1> )

IliA J>

~).3L_..!..N'!!.N'!!.M~l:~--{:.I1 IQ2IAC:»l>

+r---------~pYU~~ufP~~~I/~I~C==))

5 ~ J..~~;--EENIiNIii,M:""l:XT!!M~-<(JI]/~+~A==)) n~~5~~~--_~---~--------------+~-~-----------~ ~., U311. I _ U31'

(IT~=~~!.~~7~~.~-~~M~llLL.~,~8q~~----~---~---------------~_~+----_----------------~H----~e~ ~~io·~_~4~A~~!I!1 ,~ (1/4C :ilt>",-~D "'''''' I RSoB ... 7 AI 01 S e. ~e..

'~Z~D~I_~3q~RSA lC2~1L-+_----'_+_----1_------------------~ .......... --~~~----------------_++1_---~.~~ 02~1~'-~~~,~,c ~ D Le~~&~+_----_+----1_-------------------------~_+~-------------------_+~1_-~~~~~43 03 ,2 , b ~J

I'''' u .. l2.. L---<[ II tc. )

8367 U411, f'lTP3 ~M ~i (11/~41~~:»TJ~~~~~-_f~~A~IS~~~~~~~A~ CRTC LRC~I~3_+~I~~~2=---~N~L~R~'2X-~-----------T~---------++_~-______ -, ~~ U311 Qb

TAl .n AI v LSI'+ _ OTP2. Xl 2. Nt. Ii ~ 12 T .s-+ A2. D(C .... l~1t_11_----"..::13 U511 ... 7'---.............:t>:..::~:::,"_~".......... _______ I __________ ___, L500 LS175 ~ AT c..RO~ SIQ5 "/: 3~ A~ 18 I, [) J.=5'---j--'I-""V-";,~R"-~ ________________ _, I !~ AS 2 I 1213 UZ,2

~2 lvsR I. ~ 3 I ~e,,~ I.Suo.z b II.3l 1 ... r-121 "XS 22. 4 ..l K CL 1>7 * : ~~ ~ tc6~ 2'r L'2":: "'i1r,.' ~r-I 'I ~ ~ 10 51~ 4n 'fa 3~fJ ~~" f1 ~~ ~ ~ 5 ~ ;;tf3 :: ~ " 1~~ -f~~ L~~~~:~~=t====s~,~~~ .. ~ ..... ===......,+'\1~--H-l-------------------y L--+_~""_I3r:_U+::.'1:..-~)~4-t_t:::!E-:'-I~::(J5~ lelL 2Qjr-- I r'-"--ii~~~~:,~~~ l ~~U"3Q::-~~,,;:"~2 :::" ~~ I TAl. 2" AIO V&'Y4 2. 4 Iu~t--- L.Bc..X \l l I~ ~ ~

_TAil 2S A!I .. _ ""0 c.~p R.L 38, -L5"'~ h..... " 1/ ~I ;zr.:: " K~ .,.. a w ",- _~_ NI<ESETA 8 LSl75 Qii KpR A B c.W ~ (CII'-/~IAC:J!>----t--PT.,ge,u~SI\~\.'.L.?:"!iy71 ~ U2~ f 5174 I 9 ~~~ SOO ~UlII 13 D (jl+h '0 U413 1If<1"';'SI

TAI5 S .r--l _.----1 , Uta THMREG/ q ~" . soa 21 41 51 ", '--________ ++-__ -+-___ +-./--_-+--.-l TA,.,. :ouZ7~1 '--::-'L.=:ev.:=:=-'-_....:;~:-i,'I~6/ =ZQ3l>3'Q~ p~cx ~ _

CTl::ili=»---t---+--~,.,.,~8U~SA~l(.~~~n1~l.7 . +5V (L~l _-'~"'~:'7C.~l:--,-;.+·.prk, U410 10 LV5RX ~1.502.. Silz....: Q w+ ( II IS pL II( q I 2 H--"==---=~I~ 51> >G 4D '1-Q r/~~o~3~ pF

.1"1115 LSZ++s U14 ~ m I L'S175 15L..!l//ZI III 'I;l 3 LI~II 1 1 J 'f'W3 ...... ,+ , 1/ U75 L'::6ADEl '----< Ll!>cDEL Vc-:+----------~2.---C_::"\ j 1 /I Cl.... tJ

T /1 .:..:... '--H--":........:..c..:....::'-'------------' '---+--'====--------, ,~Xh=+-______ "''''''_'':3 I UII2. 13 Uti:" I·~ u+/3 TAI~ 3 "bJ ..g............ Q 1> ~4 S' '+ ,/ ~'--___ -+_ .....

. TAIl. T 7 ~ S trXS,.... ______ -L,c..1I::3;.-" 1.500 LSOO

11 ~ ~~ :71'

SOO '--_~--------;.....~..;...C...:...'RC.'-'-------_+_---___, IZ 13 Ls32.. l v - ! '--____ ul~L'U+~~~------+--+--U~LT-I~M~E.-------------------~4~-.. b ~, u

( 1/ IB

,0

+15VK3

410

((I

I

I

II I '--_______ ~------C~U~~~------+-_+------T~~~UIW ~~R ~~ ~UII~ I NL.RCX. "L.INE 51°13 ----- I

SID I2..JW</,1I N.:uRSOR MK41/G -2. (ax)

NReSET8 I/4-D )

( IIIB

( I r Ie ( I/iB

( 1/14

(1/ IA

TNWR

PULI...UP

TNRD

G /5

4 12. s

~

fl.I7 5

1'::::"""A::<lf+_-,J."A IY"""''--Ir---,!A::...3 ../Vw,--,rI.:....;:2.0,-,-:..::/3, TI\3 3 , 8

I,--,T.!:'-A9"-t~5'-W1" Zyt-'7--1I----"A=2.../VW'"'"R.:...,2..;..:2._'-'''-J I'T-,-,,-JA~2.+_-,"'-I2.8 U5b I'-'T-'lA""S+_.....!..Ii!..f.3A ~yl-'q'--ll----'-'II"-I ../Vw""R.:.:l::::3_'_0-J ('-LT~I\~ 1--""1°38 1"""'1':...,. .... -;,-' +_-,-If.:f4A 4y'j.!I=..Z ~---"A<;"4WI/'-:.;.R2:::1'--:..:' ~'-l

(.141 U42. u43 U+4 U51

~D4i-12V

Vtc. J.+5V

YBS t--SV

V55~ U5Z UB U54 I V

- 15 CAs-_TA4' 13~

15¢ 'L- ~ \iiR ~AS±-I>/W 1>111/ tlIN !)IN DIN Dill '/)IN DIN

Zr;41 I!D~ i!tl~ ~ e~ ZD~J zo!J i!'D;J 47(RZf

L8(.Q;:L

I 53.2 ENHOff= I liD

1 1r./R2.

r-+-------, I LS74 +

LS 1..1 S U41 :r--~3+r-+--+-+-.....:~"-I,..IQ~~ 2

4 I U~+ .--+------~

I T I LSI ..

U212 LSoO '---I----L-__ ~13if .;OO.i ..... j2-t-....:. ... .r,:::;.,. NfU/..L8RT

I SO'l ~J)""'-+_+-=':...==---(>

,,_ r--C> J3-5 ~B HIIALI'~~~ J3-1

~o~ 8 """s ~ , UIII .. \ ~ ..

sao ,!....- BLINKRATE

a

I liD )

J3-4-

VIDEO 508

r-----""T.~HU32 8 NRIIS

----- IO~ ~~8~N~C~A~S~VV~ __ J

SOO ~7/RZ5

[tllS175 ~~ ~--------~--r-----------------;----------------------~-r~~:=;2 ~I~~~L-----~~~-~::A:X~ __ ~:"_:I~~~I!I:- NEOLncL

-1"

,e $00 LSOO ~ J3-3

VBLAN~ ........ 1.../IA /1 un ~ )

I DISPoFF 1/ +8 CLGl

"ft U7"1 L504

8 ,,-'UX

lie: R'4-1 -12. V ___ '_Rtc:Jl f--.5",'-D1I,N1 f ...... '_5 ___ _ 5 V

L...t>+5V

Z2PF~Z c.RI (7 ... L.......!. 5./IV

~7

1

10

NRI!5ETB

LSI75

HBLANJ(

18

-LS2.1

FiglH'f~ 2 p('o(::es~)()i"

JAN-04 .. · .. B~?

)

1/0 Sc:h~?Mat:l.c

1 ~5~~~:! () -.. 9 i 0 B7

J2.- q _ BATr+ :;. CR'f ....L.. 2.20 '12. vJ ~\2V

Jl-/O~~F ~~1"511 «)./IB,ID TBU!>At:..

u7Q

~ <I7..IIB,IDr-~5 .

L.504

iAI5 I!>. LS08 1,-~T~A'~4 ______ ~/~~yl.U710~

~ ~W5 Wb ~80A

I~r- I U48 L......L,O I

Ij -40~ ·U"~2. 11- sa--r------'" ~ jQ rL- 1. ~ 11"'1 WAIT

- !>~

11 ':'9.: 'EU"" " LSZ? ---=-3l> T 4~

5 ;;,/,10 "I rJ I 'IV- I LS175

NMI

DI~' l~ ________ ~ ~~Il D3~ II ~~A" 5,....eM~ I

f j!0i, I I'TAlh S 1'5D<>/O'-+5::.1<'€M=-:.=!>'--_+-I ________ __+---+-----__+--------i~__+---_, J)5~ ~ c. YI> p9 t~V 'X y

t~T 2D 24T cs vee

~M' ~A1U('7

lIZ ~~ ,"- ~""' ~f1J ~P13

IOU 2D U7IO ~M. ~A+ ~A4-5;a TIIRJl4~"" W>~ ~A5 w~ ~AS (Hit ~V\sI'1 IOJ( It:. ~ AIo bl ~ ~ "10 DI ~ ,~ 1'<"

tSV t5V (.3~)"{~ ~ ~7 /)~ ~ ~ "7 l:>zJ1L~ ~ A7

?,~~ ~~'Ru 1'"ti'<B z~ AS ~3 ~ I'Tlle B fie t>3~ ~ AS "'cJ,.L U4'l" ~3"t ~ ," L*~ ~Aq 1/4 ZI>+_ ~ "'I IN'" ~,-----. ~AIO 1>51'$ ZOS, ~AIO Jl5~ ~AIO

~/-f"r----' ~ All tl'I/~ zzx" ~ 1\11 llIuli.b ZD4> ~TAII la All

« :2/1" ~ ""T '.116 ..

'iV 24'1' va.

J~ ~C.I33 CR.7 1901·0050

Z2

vee

U73 18

" 'DI~ '1 ZOtP :WZ

DO o? il 2. D' I",Z",I23",,-_2::::'-1 PI'r/~I~ __ -'r~Z~Dt~--~Zl~ \:>0' 1Ll zt>S B bII 3 ZP2. In.;. 24

lX>2~ »f3 15 ZI>3

l>03f&-J

ZD7 25

e£l R30 ,tIVC2X

' II:.

2 C5¢> "h " L532. 6

1

II -

tt

5%551 TA~-TAI5 2//A,'tA

MCI4S~

CT~ ;0-- I r----'"" U~I t t-'----------------------..... o C.S

NOCO ~/~ ~ j-/_D ____________ CJ ocRI

WD5R 17 I D'SR II Q r:='3:..-------------_CJ<J DM

N~orl~1.---r_~--~~~ ~4~---------~-----~..... RD

R.EVS CONT. AT L~TT

(RS232jCCITT) J,,-II (cB/I~)

Jf> - IS (CE/125)

J',-I2.

J&- 9

(CC/I07)

(B8/10'f)

NCT" tl N'SI~

II "0 flIT jC~IO pF C.3:3- OlD (,,-I.) DATACDMM

\1 MC.1488

GilD

+5V--f> Jb-2 ,3

+IZV~ J"-I'I

-1'2.Y--c> J"-Zo NRE5ETA 1/4-D bOH/! 2/IA J>

NOTES:

J~- 7 (CHillI)

...)~ - 22. (CA/IOS)

~b- 23 (cO/I08.a)

Jb - Zf (8A/IO~)

J b - +,5,",15)52-(AB/IOa)

J" -33 (M/IOI)

'---++-+_--+----..... -1-------+----j~N:..M'"-'--' ~'~'d' All l>7~ ~'2. I AI,- D7~ C ,I~,S 1 AI2-

• j,J ~ ' .. /M .. "iJl '--t----+_f--+---f------..J *"" /3 <iN/) ~WI "ND t ~'f GNI>

O/~ID~ I I ~~=v __ '~_v _____ +_~_v __ ~_~ _____ t_S_v __ '_~ ____ ~~~1111 <I. 2/1]) 1: v , TA7 TA7

NIO

I. JllMPE"RS SHOWN IN STJ:) CON FIG.. 2. SPARES:

uZI4 rJ!1!t-, ~(7411) : (SO 4-)

(l/ In 4-A PULl-UP

+5V

IK R~ 'f;;--;;l

"'RESETA 7. T UIDII a:/OP:I.D QD

(' 114D J> I A e. c. 0 :3 .,. 5 "11

( ZlIA "t.t1.~I'\Hi

KEVBOARI:>

ISO

I2.lU7/1

100 • 1. R40 T470pI'

VC38 ( I /4 t> NRE5ET8

<[ :z.t4C

«tI4c'

( 2/1A

IK R31

511>3

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I ~A7 I~~ : ~~ U73 (NOT WADED)

: I HM 7611 I

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+5Y<J<J------+--r---ilC~ J2 -I J CI T lZl'F

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Figure 4 I/O TiMing DiagraM JAN-04-82 13220-91087

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FIGURE 5.0 Z80A ROM TIMING

Fi(]Ul'e S ROM TiMing DiagraM JAN-04-82 13220-91087

DKC.X: (uSI1· 7;

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FIGURE 6.0 RAM TIMING

RAM TiMing DiagraM JAN-04-82 13220-91087

3 5 0 7 8 9'

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..

Video Line Rate TiMing DiagraM JAN-04-B2 13220-91087

.£ 3 + b 7 9 2. 3 5

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NOTES:

1. UNLESS OTHERWISE SPECIFIED:

ALL RESISTANCE IN OHMS,

ALL RESISTORS I/SW ,1% V.W,5%

ALL CAPACITANCE IN MICROFARADS,

ALL 1(; S PART NUMBERS PREFiXED BY 1820-

ALL TRANSISTORS HP PN 1854- 0467

ALL DIODES HP PN 1901- 0040

~ MASK BEFORE LOADING,

3 MARK DATE CODE (OPER 33) INSTALL IN POST SOLDER LOADING FROM CIRCUIT SIDE (4 PLACES), PRESS ITEM 2 INTO P.C. BOARD FIRST, THEN INSTALL ITEM 3 INTO ITEM 2, SEE DETAIL 'A'.

S, DO NOT LOAD ITEMS DENOTED BY ASTERISK I, C6, C39- 41,C46,C48,CSO,C52, C54,C56,C58, C60, C64, C66, C68, cn, C7S, CSO,C82, CS6, C90, C93, C96, C98, CIOO,CI02,CI04,CI06, CIOS, CliO, C1I2, C1I4, CIIG,CIIS, CI20,CI22-124, CI26,CI2S, C130, C132, W3, WS, W1, W9, WII ,WI3, WIS, WI7,UI3,UI4.

6, LOAD IN PRETEST· U2S, U38, U39, U4S,U73, U412, U612

£7 CUT U49,S(COM'Of£NT SIDE) JUMPER U49.5TOU69.13

.:1::.s. VERIFY we WAS LOADED.

Fiqur(-? ('I COMponent Location DiagraM JAN-04-82 13220-91087

Replaceable Parts

Reference HP Part c Qty Description Mfr Mfr Part Number Designation Number 0 Code

026:~0-60007 9 PROCESSOR PCA - 2622A 284BO 026::'>0-600137

C2 0160-4787 8 2 CAPACITOR-FXD 22PF +-57. 100VDC CER 0+-30 28480 0160'-4787 C3 0160-4801 7 2 CAPACITOR-·FXD 100PF +-57. 100VDC CER ;>.134BO o HO-4801 C4 0'180-1'701 2 1 CAPACITOR-FXD 6.8UF+-207. 6VDC TA 56;'>'89 150D685XOO06A2 C5 0160-3335 0 10 CAPACITOR-·FXD 470PF +-107. 100VDC CER ;:>8480 0160·-:n35 C'7 0'180-2879 7 3 CAPACITOR-FXD 2211F+50-107. 25VDC At 2f.l480 0180-2879

C8 0160-4557 0 21 CAPACITOR-FXD .1UF +-207. 50VDC CER 16299 CAC04X7Rl04M050A C9 0'1bCl-4557 0 CAPAC ITOR -FXD .111F +-207. 50VDC CER 16299 CAC04X7Rl04M050A Cl0 0160-4557 0 CAPACITOR-FXD .1UF +-·20:Y. 50VDC CER 162'79 CAC04X7Rl04M050A Cl1 0'160-4557 0 CAPACITOR-FXD .1UF +-207. 50VDC CER 16299 CAC04X7Rl04M050A C12 0160-4557 0 CAPACITOR--FXD .1UF +-207. ::';OVDC CER 16299 CAC04X7Rl04M050A

C'13- 0'160-4557 0 CAPACITOR-FXD .111F +-207. 50VDC CER 16299 CAC04X7Rl04M050A C14 0160-4557 0 CAPACITOR-FXD .1UF +-207. 50VDC CER 16;~99 CAC04X7Rl04M050A Cl ~; 0'160-4557 0 CAPACITOR-FXD .1UF +-20% 50VDC CER 16299 CAC04X7R104M050A C16 0160-4557 0 CAPACITOR-FXD .1UF +-20% 50VDC CER 16;~'t9 CAC04X7Rl04M050A C'17 0'16(1-4557 0 CAPACITOR-FXD .1UF +-20% 50VDC CER 16299 CAC04X7Rl04M050A

C18 0160-4557 0 CAPACITDR-FXD .1UF +-·20i:: 50VDC CER 16~~99 CAC04X7Rl04M050A C19 0'160-4557 0 CAPACITOR-FXD .1UF +-20:Y. 50VDC CER 16299 CAC04X7Rl04M050A C20 0160-4557 0 CAPACITOR""FXD .1UF +-207. 50VDC CER 16('.99 CAC04X7R104M050A C::!l 0'160--4557 0 CAPAC ITOR -FXD .111F +-207. 50VDC CER 16::'.99 CAC04X7Rl04M050A C22 0160-45::';7 0 CAPACITOR·-FXD .1UF +-·20% 50VDC CER 16;~99 CAC04X7R104M050A

C;:'.3. 0'16(1-4557 0 CAPACITOR-FXD .111F +-20% 50VDC CER 16,'.99 CAC04X7Rl04M050A C24 0160-4787 8 CAPACITOR-·FXD 22PF +-5i:: 100VDC CER 0+-30 ('.1:1480 0160-4787 C;:?5 0180-2879 7 CAPACITOR-FXD 2;~UF+50-1 07. 25VDC AI... 2f.l4BO OHlO-2879 C26 0180-2879 7 CAPACITOR·"FXD 22UF+50-10i:: 25VDC AL ;:'.84BO 0180-2879 C::'.7 016(1-4557 CAPACITOR-FXD .1UF +-207. 50VDC CER 16299 CAC04X7R104M050A

C28 0160-4557 0 CAPACITOR-FXD .11.JF +-207. 50VDC CER 16299 CAC04X7R104M050A C::!9 0160-3335 0 CAPACITOR-FXD 470PF +-10X 100VDC CER 21'1480 0160-333:7; C30 0160-3335 0 CAPACITOR-·FXD 470PF +-10i:: 100VDC CEI~ ;.:.'84BO 0160-3:n5 C31 0'16C1"-3335 0 CAPAC ITOR -FXD 470PF +-10X 100VDC CER 2B480 0160-33~35 C32 0160-3335 0 CAPACITOR-FXD 470PF +-10i:: lOOVDC CER ;,'B4BO 0'lb0-3335

C~53 0'16(1-3335 0 CAPACITOR-FXD 470PF +-10i:: 100VDC CER 284BO 0160-3335 C34 0160-3335 0 CAPACITOR-·FXD 470PF +-10% 10 OVDC eER ;~B480 0160-3335 C35 0160-3335 0 CAPACITOR-:-FXD 470PF +-10i:: 100VDC CER 2.B4BO 0160-3335 C36 0160-3335 0 CAPACITOR--FXD 470PF +-10X 100VDC CEI~ 2El4BO 0160-3335 C~37 o 16C1-4tlOl 7 CAPACITOR-FXD 100PF +-5i:: 100VDC CER 2f:l480 0160·-4801

C3S 0160-3335 0 CAPACITOR-·FXD 470PF +-10X 100VDC CER 28480 0160-3335 C42: 0160-4554 7 52 CAPACITOR-FXD .01UF +-20X 50VDC CER 2B480 0160,-4554 C43 0160-4554 7 CAPACITOR""FXD .OlI.JF +-20i:: 50VDC CER 284BO o 160-4!'554 C44 0'16(1-4557 0 CAPACITOR-FXD .1UF +-207. 50VDC CER 16::~99 CAC04X7Rl04M050A C45 0160-4554 7 CAPACITOR--FXD .OlI.JF +-20X 50VDC CER ;:.'134BO o 160-4~:;:':;4

C47 0160-4554 7 CAPACITOR-FXD .01lJF +-20i:: 50VDC CER 2f:l480 0160-4554 C49 0160-4554 7 CAPACITOR-·FXD .OlUF +-20i:: 50VDC CER ;.:.~8480 0'lb0-45:':;4 C:':;l 0'160-4554 7 CAPACITOR-FXD .01lJF +-21l7. 50VDC CER 21'1480 0160-45~;4 C53. 1l161l-4554 7 CAPACITOR·_·FXD .01LJF +-20'Y. 50VDC CER ?El480 0160-4:7i54 C~5~j 0160-4554 7 CAPACITOR-FXD .01UF +-20'Y. 50VDC CER 2f.l480 0160,-4554

C57 0160-4554 7 CAPACITOR-"FXD .OlI.JF +-20X 50VDC CER 2'8480 o 160-4!':;54 C:7;9 0160-4554 7 CAPACITOR-FXD .01 UF +-20X 50VDC CER 213480 0160-4554 C61 0160-4554 7 CAPACITOR·_·FXD .01l.JF +-20i:: 50VDC CER ;~13480 0160-4~:j54 C62 o '16(1-4~554 7 CAPACITOR-FXD . IllUF +-20i:: 50VDC CER 2B480 0160'-4554 C63 0160-4554 7 CAPACITOR--FXD .011.JF +-20'Y. 50VDC CER ?B4BO 0160-4::';54

C65 0'160-4554 7 CAPACITOR-FXD .01UF +-20i:: 50VDC CER 2f.l480 016{}-4554 C67 0160-4554 7 CAPACITOR-"FXD .01UF +-20i:: 50VDC CER 2f.l48 0 0160-4:':;54 C69' 0160-4554 7 CAPACITOR-FXD .01lJF +-20:Y. 51lVDC CER 2B4f.l0 0160-4554 C70 0160-4554 7 CAPACITDR-·FXD .OlI.JF +-20i:: 50VDC CER 28480 0160-4:";54 C71 016C1-4554 7 CAPACITOR-FXD .01UF +-207. 50VDC CER 2B4BO 0160-45~j4

C73 0160-4554 7 CAPACITOR-·FXD .OlUF +-20i:: 50VDC CER 28480 0160-4:7;54 C74 0160-4:':;54 7 CAP ACITOR '-FXD .01UF +-20i:: 50VDC CER ~~~:1480 0160-45::';4 C75 0160-4554 7 CAPACITOR-·FXD .OlI.JF +-20i:: 50VDC CER (.'8480 o 160-4::'i54 C76 0'160-4554 7 CAPACITOR-FXD .01UF +-207. 51lVDC CER 2B4ElO 0160-4~;~j4 cn 0160-4554 7 CAPACITOR-·FXD .01l.JF +-207. 50VDC CER ?8480 0160-4:':;54

C79 0160-4554 7 CAPACITOR-FXD .0111F +-20i:: 50VDC CER 2B4ElO 0160,-4554 C81 0160-4554 7 CAPACITOR-FXD .OlI.JF +--20% 50VDC CER ;,'B481l 0160-45:";4 CEl3 o 160'-4!,)54 7 CAPACITOR-FXD .01UF +-207. 50VDC CER 20480 0160-4~;54 C84 0160-4554 7 CAPACITDR-·FXD .OlI.JF +-20i:: ::';OVDC CER ;:.'13480 0160-4::';54 C05 0160-4554 7 CAPACITOR-FXD .01lJF +-20i:: 50VDC CER 20480 0160·--45::;4

C87 016(1-4554 7 CAPACITOR-"FXD .011JF +-20i:: ::'iOVDC CER ?B480 o 160-4!";54 COS 0160-4554 7 CAPACITOR-FXD .01lJF +-20i:: 50VDC CER 204130 0'160-4554 1:89 0160-4554 7 CAPACITOR-"FXD .01UF +-20i:: 50VDC CER 28480 0160-4:':;54 C'rl 01 bO-4tj54 7 CAPACITOR-FXD .0111F +-20X 51lVDC CER 2!'l4BO 0160--4554 C92 0160-4554 7 CAPACITOR,,·FXD .OlUF +-20'Y. 50VDC CER ~>'B480 0160-4!";!':i4

Reference Designation

C94 (;95 C97 C99 CI0l

C103 CI05 CI07 CI09 Cl11

Cl13 C115 Cl19 C"121 C125

C"127 C129 C131 C133 C134

C176

CRl CR2 CR3 CR4 CR5

CR6 cr~7

CR8 CR9 CR10

CIH1 CR12

11 J2 n J4 J6

Ql Q:.:? (;13 (~4

R1 R;;? R3 R4 R5

R6 R7 RB R9 Rl0

Rll R12 R13 R"14 R15

R16 R17 R"18 R19 R:'?O

R21 R;:!.2 R23 R:'?4 R25

R:'?6 RZ7 R:'?8 R2'~

R ~3 0

R31 R32 R33 R::34 R35

HP Part Number

0160-4554 0'lb0--4554 0160-4554 0'1 bO'-4554 0160-4554

0"1 bO-4554 0160-4554 0"1 bO-4:':i54 0160-4554 0"160-4554

0160-4554 0"1 bO-4554 0160-4554 01 bO-4554 0160-4554

0160-,4554 0160-4554 ()"160'-4554 0160-4557 0160-4557

0160-4554

1 ';>02-0041 1901-0040 1';>01-0040 1901-0040 1901-,0040

1901-0040 1901-0050 1901-0040 1 ';>01-·0 040 1902-0976

1 ';>02-·0976 1902-0976

1;:'51-5500 1251-55~~1

1 ;:~51-5~:;20 1251-5499 1~:?'51-5546

1854-0019 H154-0467 11354-0467 HI53·-0036

0683-1035 0683-1025 06133-4715 0683-,4'715 06B3-4705

0683-4'715 0683-1025 0683-4'715 06B3-4715 0683···1025

0683-1025 0683-,1025 0683-1025 0683-,1025 0683-5615

0683-4705 06133-4705 0683-4705 0683-4705 0683--4705

06B3-4705 0683··4'705 06133-4705 0683'·-4'705 06B3-4705

0683-1025 06133-10:>'5 0683-,1025 0683-1015 0683-,1025

06B3-1025 0683,·-4'725 0683-1025 0683-,1025 06133-1025

c o

7 7 7 7 7

7 7 7 7 7

7 7 7 7 7

7 7 7 o o

7

4 1 1 1 1

1 3 1 1 4

4 4

9 4 3 5 3

3 5

1 9 o o 8

o 9 o o 9

9 9 9 9 1

8 8 8 8 8

B 8 8 B B

9 9 9 7 9

9 2 9 9 9

Qty

1 7

2

4 17

6

11

Replaceable Parts

Description

GAPACITOR···FXD ,llllF +-20" 50VDC CER CAPACITOR-FXD ,I11UF +-20% 50VDC CER CAPACITOR-·FXD ,lll1F +-20% 50VDC CER CAPACITOR-FXD ,111 UF +-20% 50VDC CER CAPACITOR--FXD ,llUF +-20% 50VDC CER

CAPACITOR-FXD ,l)lUF +-,20% 50VDC CER CAPACITOR···FXD ,HUF +-20% 50VDC CER CAPACITOR-F)('D ,II1UF +-20% 50VDC CER CAPACITDR·-FXD ,11 UF +-20" 50VDC CER CAPACITOR-FXD ,IIIUF +-20% 50VDC eER

CAPACITDR-FXD ,I11I.JF +-20" 50VDC CER CAPACITOR-FXD ,lilUF +-20" 50VDC CER CAPACITOR-FXD ,I11I.JF +-20% 50VDC CER CAPACITOR-FXD ,olUF +-20% 50VDC CER CAPACITOR-FXD ,IIIUF +-20% 50VDC CER

CAPACITOR-FXD ,IIIUF +-20% 50VDC CER CAPACITOR-·FXD ,II1UF +-20% :7iOVDC CER CAPACITOR-FXD ,II1UF +-20% 50VDC CER CAPACITOR-FXD ,lllF +-20" 50VDC CER CAPACITOR-FXD , UF +-20% 50VDC CER

CAPACITOR-·FXD ,I) 1I.JF +-,!O% 50VDC CER

DIODE-ZNR 5,llV 5% DO-35 PD=,4W DIODE-SWITCHING 30V 50MA 2NS DO-35 DIODE-SWITCHING 30V 50MA 2NS 00-35 DIODE-SWITCHING 30U 50MA 2NS DO-35 DIODE-SWITCHING 30V 50MA 2NS 00-35

DIODE-SWITCHING 30U 50MA 2NS DO-35 DIODE-SWITCHING 80V 200MA 2NS DO-35 DIODE-SWITCHING 30V 50MA 2NS DO-35 DIODE-SWITCHING 30V 50MA 2NS DO-35 DIODE-ZNR 14,5V PD=5W TC=+,088" IR=5UA

DIODE-ZNR 14,5V PD=5W TC=+,088% IR=SUA DIODE-ZNR 14,5V PD=5W TC=+,088" IR-5UA

CONNECTOR 26-PIN M POST TYPE CONNECTOR 9-PIN M POST TYPE CONNECTOR 7-PIN M POST TYPE CONNECTOR lb-PIN M POST TYPE CONNECTOR 34-PIN M POST TYPE

TRANSISTOR NPN ;1 TO-18 PD=360MW TRANSISTOR NPN 'N440 1 SI TO'-92 PD=310MW TRANSISTDR NPN 'N4401 SI TO-92 PD=3'l0i'1W TRANSISTOR PNP II PI>=310MW FT=250MHZ

RESISTOR 10K 5% ,25W FC TC=-400/+700 RESISTOR lK 5% 25W FC TC=-400/+600 RESISTDR 470 5% ,25W FC TC=-400/+600 RESISTOR 470 5% ,25W FC TC=-400/+600 RESISTOR 47 5% 25W FC TC=-400/+500

RESISTOR 470 5% ,25W FC TC=-400/+600 RESISTOR lK 5% 25W FC TC=-400/+600 RESISTOR 470 5% ,25W FC TC=-400/+600 RESISTOR 470 5% ,25W FC TC=-400/+600 RESISTOR lK 5% 25W FC TC=-400/+600

RESISTOR lK 5% 25W FC TC=-400/+600 RESISTOR lK 5% 25W FC TC=-400/+600 RESISTOR lK 5% 25W FC TC=-400/+600 RESISTOR lK 5% 25W FC TC=-400/+600 RESISTOR 560 5% ,25W FC TC=-400/+600

RESISTOR 47 5% RESISTOR 47 5% RESISTOR 47 5% RESIBTDR 47 5% RESISTOR 47 5%

RESISTOR 47 5% RESISTOR 47 5% RESISTDR 47 5" RESISTOR 47 5% RESISTOR 47 5%

25W FC TC=-400/+500 25W FC TC--400/+500 25W FC TC=-400/+500 25W FC TC=-400/+500 25W FC TC=-400/+500

25W FC TC=-400/+500 25W FC TC=-400/+500 25W FC TC=-400/+500 25W FC TC--400/+500 25W FC TC=-400/+500

RESISTOR lK 5% 25W FC TC=-400/+bOO RESISTOR lK 5% 25W FC TC=-400/+600 RESISTOR lK 5% 25W FC TC--400/+600 RESISTOR 100 5" ,25W FC TC=-400/+500 RESISTOR 1K 5% 25W FC TC=-400/+600

RESISTOR lK 5% 25W FC TC=-400/+bOO RESISTOR 4,7K 5~ ,25W FC TC=-400/+700 RESISTOR 1K 5% 25W FC TC=-400/+600 RESISTOR lK 5% 25W FC TC=-400/+600 RESISTOR lK 5% 25W FC TC=-400/+600

Mfr Code

284S0 213480 284S0 2f.l480 ~:'8480

2fj480 2134S0 21'1480 ::'>8480 28480

28480 213480 :~134S0

213480 ?84S0

2B480 ~J.8480

21'1480 16299 16299

28480

21'1480 :'.84S0 21:1480 284S0 2f.l480

?84S0 28480 ~'8480

21:1480 11961

11961 11961

;':'.84S0 ;,,8480 21'1480 ?84S0 ?84S0

;:~B4S0

0~3:7i08 0350S 21'1480

01121 01121 01121 01121 011 ?1

01121 o 11;:~ 1 01121 01121 01121

01121 01121 011<.'1 01121 01121

01121 01121 01.121 01121 01121

01121 01121 01121 01121 01121

01121 01121 01121 01121 01121

01121 01121 01121 01121 01121

Mfr Part Number

0160-4554 01bO·-4554 0160-4554 0160-4554 0160-4554

0160-4554 0160-4554 0160-4554 0160-4554 0160-4554

0160-4554 0160-4554 0160-4554 0160-4554 0160-4554

0160-4554 0160-4554 0160-4554 CAC04X7RI04M050A CAC04X7Rl04M050A

1902-0041 1'701-0040 1901-0040 '1901-0040 1901-0040

1901-0040 1901-0050 1';101-0040 1901-0040 l,5SEIHC

l,58E18C 1. :'::'5El BC

12:7il-5500 1 ;'.'51-5521 1251-5520 12~il-5499

1251-5546

1854-0019 2N4401 2N440 1 1853,-0036

CIlI035 CB1025 CB4715 CB4715 CB4705

CB4715 CBI025 CB4715 CIl4715 CBI025

CBI025 CB1025 CB10;,,5 CBI025 CB5615

CB4705 CB4705 CB4705 CB4705 CB4705

CB4705 CB4705 CB4705 CB4705 CB4705

CBI025 CBI025 CB1025 CBl 0 15 CB1025

CBI025 CB4725 CB1025 CB1025 CB10;?5

Replaceable Parts

Reference HP Part c Qty Description Mfr Mfr Part Number Designation Number 0 Code

R36 0683--2205 9 1 RESISTOR 22 5::C: ,25W Fe TC=-400/+500 01121 CB2205 R~57 0683--4715 0 RESISTOR 470 5::C: ,25W Fe TC=-400/+600 01121 CB4715 R38 0683--1515 2 ~~ RESISTOR 150 5::C: ,25W FC TC=--400/+600 01121 CB1515 1~~59 0683--1515 2 RESISTOR 150 5% .2SW FC TC=-400/+600 01121 CB1515 R40 0683--1015 7 RESISTOR 100 5::C: ,25W FC TC=--40 0/+5 00 01 H!l CBl 0 15

R44 0683-,1035 1 RESISTOR 10K 5:r. .2SW FC TC=-400/+700 01121 CB1035 R45 06B3--1025 9 RESISTOR lK !:i::C: ,25W FC TC=-400/+600 01121 CB1025 R46 0686-,2215 7 1 RESISTOR 2~~O 5:r. ,5W CC TC=0+529 01121 EB;;~215 R47 0683--1025 9 RESISTOR lK 5X .25W FC TC=--40 0/+600 01121 CB10?5 R48 0683--1035 1 RESISTOR 10K 5:r. .25W FC TC=-400/+700 01121 CB1035

R49 0683--1035 1 RESISTOR 10K 5X ,25W FC TC=-400/+700 01121 CB1035

U15 11320"-1917 1 2 IC BFR TTL lS LINE DRVR OCTl 01295 SN74lS240N U16 1820--1917 1 IC BFR TTL l.S L.INE DRVR DCTl 01295 SN74lS240N l.J17 11320-· 1112 8 2 IC FF TTL lS D····TYPE POS-EDGE-TRIG 01295 SN74LS74AN U18 1820--1195 7 4 IC FF TTL LS D-··TYPE POS-'EDGE-TR IG COM 01295 SN74lS175N Ll19 11'120-·1449 4 1 IC GATE TTL S OR QUAD 2-INP 01295 SN74S32N

U23 1820--0683 6 :3 IC INV TTL S HEX l-INP 012'75 SN74S04N U~~4 1f.120-·1216 3 2 IC DC DR TTL l.S 3-'TO-8-l I NE 3-INP 01295 SN74LS138N 1.)25 1820--1987 5 1 IC SHF-··RGTR TTL LS COM CLEAR STOR 8-'BIT 01295 SN'74lS299N U;,:6 11320-,1997 7 1 IC FF TTL LS D-TYPE POS-EDGE-TRIG PRL-IN 01295 SN74LS374N 1.)27 1820--1206 1 2 IC GATE TTL l.S NDR TPl 3-INP 01295 SN74lS27N

U;'!.8 11:120··2416 7 3 IC SHF-RGTR NMOS SERIAL-IN SERIAL-OUT 27014 MM~i035P 1.)29 1820-··1196 8 ~.? IC FT TTL LS D··-TYPE POS-'EDGE-TR IG COM 01295 SN74lS174N lr:~2 11320-,1367 5 1 IC GATE TTL S AND QUAD 2·_·INP 01295 SN74S08N U33 1820--11 44 6 2 Ie GATE TTL lS NOR QUAD 2-INP 01295 SN74lS02N U34 1020-,1208 3 1 IC GATE TTL l.S OR QUAD 2·-INP 01295 SN74lS32N

U35 1820--1196 8 IC FF TTL LS D-·TYPE POS-EDGE-TRIG COM o 1;:!.95 SN'74lS174N U36 1020-,2024 3 5 Ie DRVR TTL lS LINE DRVR OCTl 01295 SN74LS244N U37 1820--2075 4 1 IC MISC TTL l.S 01295 SN74lS245N U~58 1020--2416 7 IC SHF-RGTR NMOS SERIAL-IN SERIAL-OUT 27014 MM!5035P U39 1820--2416 7 IC SHF···RGTR NMOS SERIAL-IN SERIAL-OUT 27014 MM5035P

U41 5081,-2705 3 8 16K RAM 28480 5081-2705 U42 5081--2705 3 16K RAM 28480 5081-2705 U43 5081-,,2705 3 16K RAM 284f.IO 5081-2705 U44 :':iOBl--2705 3 16K RAM ~~8480 51l81-2705 U46 HJ20-·1438 1 2 IC MUXRlDATA-SEl TTL lS 2···TO-1-LINE QUAD 01295 SN74LS257AN

U47 11320--2024 3 Ie DRVR TTL I..S LINE DRVR DCTl 01295 SN74lS244N U48 11:120···2298 3 1 Ic-zaOA CPU 2841:10 1820-2298 U49 11320--,1197 '7 " Ie GATE TTL l.S NAND QUAD 2-INP 01295 SN74lS0 ON U~:i1 5081···2705 3 16K RAM 28480 5081-2705 U5;~ 50Bl--2705 3 16K RAM 28480 5081-2705

l.J~.'i3 5081···2705 3 16K RAM 28480 5081,-2705 U54 ~)OBl--2705 3 16K RAM 28480 :';i081-2705 U~.'i6 11:120--1438 1 IC MI.IXR/DATA-SEl TTL lS 2-TD-1-LINE QUAD 01295 SN'74LS257AN U!:'i7 1820--2024 3 IC DRVR TTL I ... S LINE DRVR DeTl 01295 SN'74L.S244N U~:j9 11320-·1195 7 Ie FF TTL L.S D··-TYPE POS'-EDGE-TR IG COM o 1 ~~95 SN74LS175N

l.J62 1820--2102 8 1 IC I..CH TTL L.S D-TYPE DCTl 01295 SN74lS373N l.I69 11:120-,,1206 1 IC GATE TTL LS NOR TPl 3-INP 01295 SN'74l.S27N l.J74 1820,-2024 3 IC DRVR TTL LS LINE DRVR DCTl 01295 SN74lS244N U'75 11:120--1195 7 IC FF TTL. LS D'-TYPE POS-EDGE-TRIG COM 01295 SN74LS175N U76 18~~0--1216 3 Ie DCDR TTL I..S 3-TO-13-'LINE 3-INP 01:':'95 SN'74LS138N

u'n 11'120--0691 6 1 Ie GATE TTL S AND·-OR·-INV 01295 SN74S64N U78 1 B:?,0·-0683 6 Ie INV TTL S I1EX 1-INP 01295 SN74S04N U79 HI20"'1199 1 1 Ie INV TTL L.S HEX 1-INP 01295 SN'74LS04N 1.)110 IB20-06B5 8 1 Ie GATE TTL S NAND TPL 3-·INP 01295 SN74S1 IlN U1I1 11:120···0681 4 2 Ie GATE TTL S NAND QUAD 2.···INP 01295 SN'74S00N

l.J 1 1 ;:~ 1B20-1197 9 Ie GATE TTL LS NAND I~UAD ::'.·-INP 01295 SN74lS00N l.J"l14 11:120···1989 7 1 IC CNTR TTL L.S BIN DUAL 4'-BIT 07263 74L.S393PC 1.)210 18:?O--1432 ,J 1 Ie CNTR TTL lS BIN SYNCHRD PDS-EDGE-·n IG o 1l.'95 SN'74l.S163AN U211 1I:120--1:H9 7 2 Ie MUXR/DATA-SEI.. TTL S 8·-·TD-l-LINE a'-INP 01295 SN74S151N 1.)21 ;:~ 1820-0683 6 IC INV TTL S HEX 1-INP 01295 SN74S04N

U;,!l ~; 11'120--1319 7 Ie MUXR/DATA-SEL TTL S 8'-TO'-1-LINE a"-INP 01295 SN'74S151N U21'/1 18;''.0'-0618 7 1 Ie BFR TTL NON·-INV HEX 0129:':; SN7417N U~H!I 11:120--,1730 6 1 IC FF TTL lS D··-TYPE POS'-EDGE-TR IG COM 01295 SN74LS273N U;31 ;:~ 1820-1303 9 4 IC SHF·-RGTR TTl. S R-S PRl.-IN PRl-OUT 01295 SN74S1 9~)N 1l~H3 11:120-,,1303 9 Ie SHF-RGTR TTL S R'-S PRl-IN PRl-OUT 01295 SN'74S195N

U:-I14 1B20'-1303 9 IC SHF-RGTR TTl. S R-S PRl-·IN PRl-OIJT 01295 f.,N74S195N l.J4H Hl20-··1076 3 1 Ie FF TTL S D-TYPE P()S-EDGE-TRIG CLEAR 01295 SN74S174N U4I1 1820·-1144 6 Ie GATE TTL LS NDR QUAD 2-INP 01295 SN74lS02N U41,~ 11:120--2373 5 1 Ie-NAT 8367 CRT C 284BO 1820',-2373 U4B 1820·-0629 0 1 IC FF TTL S J-K NEG-'EDGE -·TR I G 01295 SN74S11:.?N

U414 1820-141 (, 5 1 Ie SCHMITT-TRIG TTl.. LS INV HEX 1-INP 01295 SN74l..S14N 1.)510 1820·-1303 9 Ie SHF-·RGTR TTl. S R-S PRI..-·IN PRL-OI.IT 01295 SN74S195N U~.'ill 1 B20-··2024 3 IC DRVR TTL LS LINE DRVI~ oeTl 01295 SN'74lS244N 1J514 11320-0509 5 1 IC DRVR DTl LINE DRVR QUAD 04713 MC1488l U6H 1B20--1195 7 Ie FF TTL LS D'-TYPE POS-EDGE-TRIG COM 01295 SN74lS175N

Replaceable Parts

Reference HP Part c Qty Description Mfr Mfr Part Number Designation Number 0 Code

1.1611 1820-1453 0 IC CNTR TTL S f,IN SYNCHRO POS-EDGE'-TRIG 01295 BN74S163N 1.1612 H120-1112 8 IC FF TTL. LS D·· TYPE POS'-EDGE-TR IG 01295 SN'74LS74AN 1.1613 1820-2577 1 IC-SYP 6551 ACI A ~~8480 10;'.0-2577 1.1614 HI20-·0990 8 IC RCVR DTL NAND LINE QUAD 01295 SN'75189AJ 1.1710 1820-1201 6 IC GATE TTL l.S AND (~I.IAD 2·-INP 01295 SN74LSOBN

1.1'711 1820-0b81 4 IC GATE TTL S NAND QUAD 2··-INP 01295 SN"14S00N

W4 8159-0005 0 B RESISTOR-ZERO fJHMS 22 AWG LEAD DIA ?B480 8159-0005 1016 8159-0005 0 RESISTOR-ZERO OHMS 22 AWG LEAD DIA 213480 81~;9-0005

W8 8159-0005 0 RESISTOR-ZERO (IHMS 22 AWG LEAD DIA ?8480 8159-0005 10110 8159-0005 0 RESISTOR-ZERO OHMS 2~~ AWG LEAD DIA 2£1480 81~W'-0005

W12 8159-0005 0 RESISTOR-ZERO flHMS 22 AWG L.EAD DIA ;'.0480 8159-0005

10114 8159-0005 0 RESISTOR-ZERO (,HMS 22 AWG LEAD DIA 2134130 81:':;9-0005 W16 8159-0005 0 RESISTOR-ZERO flHMS 22 AWG LEAD DIA ;:.'8480 B159-0005 10118 8159-0005 RESISTOR-ZERO OHMS 22 AWG LEAD DIA 2B480 81~';9-0005

XU28 1200-0b39 8 3 SOCKET-IC 20-'C[lNT DIP DIP-'SLDR ;:.'8480 1200-0639 XU38 1;;!00-Ob39 8 SOCKET-IC 20-Cf1N"T DIP DIP·-Sl.DR 28480 1200-0b39 XU39 1200-0639 8 SOCKET-IC 20'-'CfINT DIP DIP-·Sl.DR ;:?8480 t<~00-06;39

XU41 1;?00-Ob07 0 8 SOCKET-IC 16-CflNT DIP DIP"-SLDR 213480 1200-0607 XU42 1200-0607 0 SOCKET-IC 16-"C('INT DIP DIP-'Sl.DR ;,,,8480 1;:~OO-0607

XU43 1;:~00-Ob07 0 SOCKET-IC 16-CCNT DIP DIP-SLDR 213480 1200-0607 XU44 1200-0607 0 SOCKET-IC 16-'CIINT DIP DIP--SLDR <.'8480 1;'?00-0607 X1.l48 1 ;:!00-0654 7 2 SOCKET-IC 40-CCINT DIP DIP-SLDR 213480 1200-0654 XU51 1200-0b07 0 SOCKET-IC 16-'C(lNT DIP DIP-SLDR 28480 H'OO-0607 X1.l52 1200-0b07 0 SOCKET-IC 16-CUNT DIP DIP-SLDR 213480 1200-0607

XU53 1200-0607 SOCKET-IC 16-'CIINT DIP DIP-Sl.DR ;~8480 1<?OO-0607 XU54 1 ~:~00-0607 SOCKET-IC 16-CUNT DIP DIP-SlDR 213480 1200-0607 XUb3 1200-0541 "1 SOCKET-IC 24-'CfINT DIP DtP-SLDR 28480 1200-0541 XUb4 1;;!00-0541 SOCKET·-IC 24-CCINT DIP DIP"-SLDR 28480 1200-0541 XU65 1200-0541 SOCKET-IC 24-'C[lNT DIP DIP-"Sl.DR 2B480 120 0-0~i41

XUb6 1~~00-0541 1 SOCKET-IC 24-C!lNT DIP DIP-SlDR 2f:1480 1200-0541 XU67 1200-0541 1 SOCKET-IC ;?4"·C[lNT DIP DIP-Sl.DR 28480 1200-()~i41

XUb8 1;;!00-0541 1 SOCKET-IC 24-CIINT DIP DIP-SLDR 28480 12.00-0541 XU73 1200-0612 7 SOCKET-IC 22-'C(INT DIP DIp .... Sl.DR 2f:1480 1200-()b12 XU311 1;?OO-0541 SOCKET-IC 24-C(lNT DIP DIP--SLDR 20480 1200-0541

XU412 1200-0654 7 SOCKET-IC 4()-,CONT DIP DIP-Sl.DR ?B480 1200-06:':i4 XU514 1;,!00-0638 7 2 SOCKET-IC 14-C!lNT DIP DIP-SlDR 28480 1200-0b38 XU613 1200-0567 1 SOCKET-IC ;:,>B-,CflNT DIP DIP-·Sl.DR ;~B480 1;:'>00-0567 XUb14 1 ;,!OO- 0638 7 SOCKET-IC 14-CflNT DIP DIP-SLDR 28480 1200-0638

Yl 0410-1224 3 CRYSTAL-QUARTZ 25.7715 MHZ HC-<.'5/U·_·HlDR ?B480 0410-1 ;?24

0~S60-0 124 3 9 CONNECTOR-SGl raNT PIN .04-IN-BSC-SZ RND 2EI480 0~360'-0124 1200-0546 6 1 SOCKET-XTAl 2-·LONT HC-25/U DIP-SlDR (~B480 H'OO-0:':i46 LS90-0104 3 4 FASTENER-SNAP-]N GROM PANEl .. THKNS 28480 1:WO·-Ol04 1390-0281 7 4 FASTENER-SNAP-1N PLGR PANEL THKNS ;:,>B48 0 1390-0;:'B1 1818-0695 5 1 IC CMOS 1024 (1 K) STAT RAM 450-NS 3--S 04713 MCM145101-1P

MFR NO.

SO~:;4S

00000 01121 01295 O:S~;OB

04713 0'7263 11961 16~~99

27014 20480 3L585 34371 56289

MAN U F ACT U R E R S

MANIJFACTURER NAME

NIPPON ELECTRIC CO ANY SATISFACTORY SUPPLIER ALLEN-BRADLEY CO TEXAS INSTR INC SEMICOND CMPNT DIV GE CO SEMICONDUCTOR PROD DEPT MOTOROLA SEMICONDUCTOR PRODUCTS FAIRCHILD SEMICONDUCTOR DIU SEMICON INC CORNING GLASS WKS COMPONENT DIV NATIONAL SEMICONDUCTOR CORP HEWLETT-PACKARD CO CORPORATE HQ RCA CORP SOLID STATE DIV HARRIS SEMICON DIV HARRIS-INTER TYPE SPRAGUE ELECTRIC CO

COD E LIS T AS OF 12/01/81 PAGE

ZIP ADDRESS CODE

TOKYO JP

MIl.WAUKEE WI 53204 DALLAS TX 75;;.~:'.~2

AUBURN NY 13201 PHOENIX AZ 85008 MOUNTAIN VIEW CA 94042 BURLINGTON MA 011303 RALEIGH Ne 27604 SANTA CLARA CA 95()~:;1

PALO ALTO CA 94304 SOMERVILLE NJ HEUJOURNE FL. 32901 NORTH ADAMS HA 01247