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DATA SHEET

Preliminary specificationFile under Integrated Circuits, IC02

February 1995

INTEGRATED CIRCUITS

Philips Semiconductors

SAA5290One page Economy Teletext/TVmicrocontroller

February 1995 2

Philips Semiconductors Preliminary specification

One page Economy Teletext/TVmicrocontroller

SAA5290

FEATURES

General

• Complete one page teletext decoder and TVmicrocontroller in a single 52-pin package

• Eastern European, Western European and Turkishlanguage variants covered in one device

• Double size, double width and double height charactercapability for On-Screen Display (OSD)

• Enhanced display features including meshing andshadowing

• Separate display and acquisition timing for increasedflexibility

• Minimum peripheral component count

• 525 line and 625 line display synchronization

• Standby mode through power-down of teletext andanalog hardware.

Microcontroller

• 16 kbytes masked ROM (16 kbytes EEPROM variant forproduct development)

• 256 bytes of on-chip RAM

• Six 6-bit Pulse Width Modulators (PWM) and one 14-bitprecision PWM

• 4-bit Digital-to-Analog Converter (DAC) and comparatorwith a 3-input multiplexer allowing implementation of 3Analog-to-Digital Converters (ADC) in software

• 2 high current (10 mA) open-drain outputs

• Interrupt logic 0 triggered on rising and falling edges,providing pulse-width measurement for remote controldecoding

• Master and slave bit-level I2C-bus hardware.

DESCRIPTION

The SAA5290 is a single-chip one page teletext decoderand television control microcontroller. The device willdecode 625-line based World System Teletexttransmissions and provides television control functionsand On-Screen Display (OSD) functions.

The teletext decoder hardware is a derivative of theSAA5254 (IVT1.1X), and the TV control functionalityprovided by an on-chip industrial standard 80C51microcontroller. A single-page static RAM is includedon-board providing a complete one page teletext decoderand OSD memory.

The SAA5290 is available as a mask-programmed ROMversion. An EEPROM version is also available for productdevelopment. Both versions are available in an SDIP52package.

ORDERING INFORMATION

Notes

1. nnn is a three-digit number referencing the microcontroller program ROM mask.

2. I is a digit number referring to the language variant of the SAA5290ZP/NV.

TYPE NUMBER MEMORYPACKAGE

NAME DESCRIPTION VERSION

SAA5290ZP/nnn(1) ROM SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1

SAA5290ZP/NVI(2) EEPROM SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1

February 1995 3



SAA5290

QUICK REFERENCE DATA

BLOCK DIAGRAM

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

VDD supply voltage 4.5 5.0 5.5 V

IDDM microcontroller supply current − 25 40 mA

IDDA analog supply current − 35 50 mA

IDDT teletext supply current − 20 30 mA

fxtal crystal frequency − 12 − MHz

Tamb operating ambient temperature −20 − +70 °C

Fig.1 Block diagram.

handbook, full pagewidth

MLC102

DATA SLICER

ACQUISITIONTIMING

TELETEXTACQUISITION

DISPLAY TIMING

DISPLAYPAGERAM

OSCILLATOR

80C51MICRO-

CONTROLLER

ANALOG-TO-DIGITAL

CONVERTER

PULSEWIDTH

MODULATOR

TIMER/CTRS/ I C2

data

address

16K x 8ROM

PORT 3

9 to 12, 305

256 x 8RAM

PORT 2

1 to 88

TEXTINTERFACE

PORT 1

45 to 528

PORT 0

14 to 218

P3.0 to P3.4/ADC0 to ADC2

P2.0 to P2.7PWM

P1.0 to P1.7 / INT0,INT1, T0, T1, SDA, SCL

P0.0 to P0.7VSSA

22

VSSD2VSSD1

2813

43RESET

40OSCGND

42OSCOUT

41OSCIN

SAA5290

37VSYNC

36HSYNC

27FRAME

RGBREF

34, 33, 32R, G, B

35

31

VDS29

COR

25 26

BLACK IREF

CVBS0CVBS1

23, 242

38 39 44

VDDMVDDTVDDA

3

February 1995 4



SAA5290

PINNING

SYMBOL PIN DESCRIPTION

P2.0/TPWM 1 PORT 2: 8-bit open-drain bidirectional port with alternative functions. P2.0/TPWM is theoutput for the 14-bit high precision PWM. P2.1/PWM0 to P2.6/PWM5 are the outputs forthe 6-bit PWMs 0 to 5.

P2.1/PWM0 2

P2.2/PWM1 3

P2.3/PWM2 4

P2.4/PWM3 5

P2.5/PWM4 6

P2.6/PWM5 7

P2.7 8

P3.0/ADC0 9 PORT 3: 5-bit open-drain bidirectional port with alternative functions. P3.0/ADC0 toP3.2/ADC2 are the inputs for the software ADC facility.P3.1/ADC1 10

P3.2/ADC2 11

P3.3 12

P3.4 30

VSSD1 13 digital ground 1 for teletext and microcontroller circuits.

P0.0 14 PORT 0: 8-bit open-drain bidirectional port. P0.5 and P0.6 have 10 mA current sinkingcapability at 0.5 V for direct drive of LEDs.P0.1 15

P0.2 16

P0.3 17

P0.4 18

P0.5 19

P0.6 20

P0.7 21

VSSA 22 analog ground.

CVBS0 23 Composite video input. A positive-going 1 V (peak-to-peak) input is required, connectedvia a 100 nF capacitor.CVBS1 24

BLACK 25 Video black level storage input. This pin should be connected to VSSA via a 100 nFcapacitor.

IREF 26 Reference current input for analog circuits, connected to VSSA via a 27 kΩ resistor.

FRAME 27 De-interlace output synchronized with the VSYNC pulse to produce a non-interlaceddisplay by adjustment of the vertical deflection currents.

VSSD2 28 Digital ground 2.

COR 29 Open-drain, active LOW output which allows selective contrast reduction of the TVpicture to enhance a mixed mode display.

RGBREF 31 DC input voltage to define the output HIGH level on the RGB pins.

B 32 Dot rate character output of the BLUE colour information.

G 33 Dot rate character output of the GREEN colour information.

R 34 Dot rate character output of the RED colour information.

VDS 35 Video/data switch push-pull output for dot rate fast blanking.

HSYNC 36 Horizontal sync dedicated input for a TTL-level version of the horizontal sync pulse. Thepolarity of this pulse is programmable by register bit TXT1.H POLARITY.

February 1995 5



SAA5290

VSYNC 37 Vertical sync dedicated input for a TTL-level version of the vertical sync pulse. Thepolarity of this pulse is programmable by register bit TXT1.V POLARITY.

VDDA 38 +5 V analog power supply.

VDDT 39 +5 V teletext power supply.

OSCGND 40 Crystal oscillator ground.

OSCIN 41 12 MHz crystal oscillator input.

OSCOUT 42 12 MHz crystal oscillator output.

RESET 43 If the reset input is HIGH for 2 machine cycles (24 oscillator periods) while the oscillatoris running, the SAA5290 is reset. This pin should be connected to VDDM via a 2.2 µFcapacitor.

VDDM 44 +5 V microcontroller power supply.

P1.0/INT1 45 PORT 1: 8-bit open-drain bidirectional port with alternative functions. P1.0/INT1 isexternal interrupt 1 which can be triggered on the rising and falling edge of the pulse.P1.1/T0 is the counter/timer 0. P1.2/INT0 is external interrupt 0. P1.3/T1 is thecounter/timer 1. P1.6/SCL is the serial clock input for I2C-bus. P1.7/SDA is the serialdata port for the I2C-bus.

P1.1/T0 46

P1.2/INT0 47

P1.3/T1 48

P1.6/SCL 49

P1.7/SDA 50

P1.4 51

P1.5 52

SYMBOL PIN DESCRIPTION

February 1995 6



SAA5290

Fig.2 Pin configuration.

handbook, halfpage1

2

3

4

5

6

7

8

9

10

11

12

13 40

39

38

37

36

35

34

33

32

31

30

29

28

27

14

15

16

17

18

19

20

22

23

24

25

26

21

42

41

43

44

45

46

47

48

49

50

51

52

MLC103

SAA5290

P2.0/TPWM

P2.1/PWM0

P2.2/PWM1

P2.3/PWM2

P2.4/PWM3

P2.5/PWM4

P2.6/PWM5

P2.7

P3.0/ADC0

P3.1/ADC1

P3.2/ADC2

P3.3

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

CVBS0

CVBS1

BLACK

IREF

SSD1V

DDMV

DDTV

DDAV

SSD2V

SSAV

P1.5

P1.4

P1.7/SDA

P1.6/SCL

P1.3/T1

P1.2/INT0

P1.1/T0

P1.0/INT1

RESET

OSCOUT

OSCIN

OSCGND

VSYNC

HSYNC

VDS

R

G

B

RGBREF

P3.4

COR

FRAME

February 1995 7



SAA5290

QUALITY AND RELIABILITY

This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer IntegratedCircuits SNW-FQ-611-Part E” (see “Quality Reference Handbook”, order number 9398 510 63011). The principalrequirements are shown in Tables 1 to 4.

Group A

Table 1 Acceptance tests per lot

Group B

Table 2 Processability tests (by package family)

Group C

Table 3 Reliability tests (by process family)

Table 4 Reliability tests (by device type)

Notes to Tables 1 to 4

1. ppm = fraction of defective devices, in parts per million.LTPD = Lot Tolerance Percent Defective.FPM = fraction of devices failing at test condition, in Failures Per Million.FITS = Failures In Time Standard.

TEST REQUIREMENTS(1)

Mechanical cumulative target: <80 ppm

Electrical cumulative target: <80 ppm

TEST REQUIREMENTS(1)

Solderability <7% LTPD

Mechanical <15% LTPD

Solder heat resistance <15% LTPD

TEST CONDITIONS REQUIREMENTS(1)

Operational life 168 hours at Tj = 150 °C <1500 FPM; equivalent to<100 FITS at Tj = 70 °C

Humidity life temperature, humidity, bias1000 hours, 85 °C, 85% RH(or equivalent test)

<2000 FPM

Temperature cycling performance Tstg(min) to Tstg(max) <2000 FPM

TEST CONDITIONS REQUIREMENTS(1)

ESD and latch-up ESD Human body model2000 V, 100 pF, 1.5 kΩ

<15% LTPD

ESD Machine model200 V, 200 pF, 0 Ω

<15% LTPD

latch-up 100 mA, 1.5 × VDD(absolute maximum)

<15% LTPD

February 1995 8



SAA5290

LIMITING VALUESIn accordance with Absolute Maximum Rating System (IEC 134).

Notes

1. This maximum value has an absolute maximum of 6.5 V independent of VDD.

2. Except in standby mode.

CHARACTERISTICSVDD = 5 V ± 10%; VSS = 0 V; Tamb = −20 to +70 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage (all supplies) −0.3 +6.5 V

VI input voltage (any input) note 1 −0.3 VDD + 0.5 V

VO output voltage (any output) note 1 −0.3 VDD + 0.5 V

IO output current (each output) − ±10 mA

IIOK DC input or output diode current − ±20 mA

∆VSS difference between VSSD, VSSA and OSCGND − ±0.1 V

∆VDD difference between VDDM, VDDT and VDDA note 2 − ±0.1 V

Tamb operating ambient temperature −20 +70 °CTstg storage temperature −55 +125 °C

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDD supply voltage (VDD to VSS) 4.5 5.0 5.5 V

IDDM microcontroller supply current − 25 40 mA

IDDA analog supply current − 35 50 mA

IDDT teletext supply current − 20 30 mA

Digital inputs

RESET

VIL LOW level input voltage −0.3 − 0.2VDD − 0.1 V

VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V

ILI input leakage current VI = 0 to VDD −10 − +10 µA

CI input capacitance − − 4 pF

HSYNC AND VSYNC

Vthf switching threshold falling 0.2VDD − − V

Vthr switching threshold rising − − 0.8VDD V

VHYS hysteresis voltage − 0.33VDD − V


February 1995 9



SAA5290

Digital outputs

R, G AND B (note 1)

VOL LOW level output voltage IOL = 2 mA 0 − 0.2 V

VOH HIGH level output voltage IOH = −2 mA VRGBREF− 0.3

VRGBREF VRGBREF+ 0.4

V

|ZO| output impedance − − 150 ΩCL load capacitance − − 50 pF

IO DC output current − − −4 mA

tr output rise time between 10% and 90%;CL = 50 pF

− − 20 ns

tf output fall time between 90% and 10%;CL = 50 pF

− − 20 ns

COR (OPEN-DRAIN OUTPUT)

VOH HIGH level pull-up outputvoltage

− − VDD V


IOL LOW level output current − − 2 mA

CL load capacitance − − 25 pF

VDS

VOL LOW level output voltage IOL = 1.6 mA 0 − 0.2 V

VOH HIGH level output voltage IOH = −1.6 mA VDD − 0.3 − VDD + 0.4 V


tr output rise time between 10% and 90%;CL = 50 pF

− − 20 ns

tf output fall time between 90% and 10%;CL = 50 pF

− − 20 ns

R, G, B AND VDS

tskew skew delay between any twopins

− − 20 ns

FRAME

VOH HIGH level output voltage IOL = 8 mA 0 − 0.5 V

VOL LOW level output voltage IOL = −8 mA VDD − 0.5 − VDD V

IOL LOW level output current −8 − +8 mA



February 1995 10



SAA5290

Digital input/outputs

P0.0 TO P0.4, P0.7, P1.0 TO P1.5, P2.0 TO P2.7 AND P3.0 TO P3.5


VIH HIGH level input voltage 0.2VDD + 0.9 − VDD + 0.3 V


VOL LOW level output voltage IOL = 3.2 mA 0 − 0.45 V


P0.5 AND P0.6


VIH HIGH level input voltage 0.2VDD + 0.9 − VDD + 0.3 V




P1.6 AND P1.7

VIL LOW level input voltage −0.3 − +1.5 V

VIH HIGH level input voltage 3.0 − VDD + 0.3 V




tf output fall time between 3 and 1 V − − 200 ns

Analog inputs

CVBS0 AND CVBS1

Vsync sync voltage amplitude 0.1 0.3 0.6 V

Vvid(p-p) video input voltage amplitude(peak-to-peak value)

0.7 1.0 1.4 V

Zsource source impedance − − 250 ΩVIH HIGH level input voltage 3.0 − VDD + 0.3 V

|ZI| input impedance 2.5 5.0 − kΩCI input capacitance − − 10 pF

IREF

Rgnd resistor to ground − 27 − kΩ

RGBREF (note 1)

VI input voltage −0.3 − VDD V

II DC input current − − 12 mA


February 1995 11



SAA5290

Notes

1. All RGB current is sourced from the RGBREF pin. The maximum effective series resistance between RGBREF andthe R, G and B pins is 150 Ω.

2. Crystal order number 4322 143 05561.

ADC0, ADC1 AND ADC2

VIL LOW level input voltage −0.3 − VDD V

Analog input/output

BLACK

Cblack storage capacitor to ground − 100 − nF

Vblack black level voltage for nominalsync amplitude

1.8 2.15 2.5 V

ILI input leakage current −10 − +10 µA

Crystal oscillator

OSCIN


VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V


OSCOUT

fosc crystal oscillator frequency − 12 − MHz

CO output capacitance − − 10 pF

CRYSTAL SPECIFICATION (note 2)

fxtal nominal frequency − 12 − MHz

CL load capacitance − 32 − pF

C1 series capacitance Tamb = 25 °C − 18.5 − fF

C0 parallel capacitance Tamb = 25 °C − 4.9 − pF

Rr resonance resistance Tamb = 25 °C − 35 − ΩTxtal temperature range −20 +25 +70 °CXj adjustment tolerance Tamb = 25 °C − − ±50 × 10−6

Xd drift − − ±30 × 10−6


February 1995 12



SAA5290

Table 5 Characteristics for the I2C-bus interface

Notes

1. This parameter is determined by the user software. It must comply with the I2C-bus specification.

2. This value gives the auto-clock pulse length which meets the I2C-bus specification for the special crystal frequency.Alternatively, the SCL pulse must be timed by software.

3. The rise time is determined by the external bus line capacitance and pull-up resistor. It must be less than 1 µs.

4. The maximum capacitance on bus lines SDA and SCL is 400 pF.

SYMBOL PARAMETER INPUT OUTPUT I 2C-BUS SPECIFICATION

SCL timing

tHD;STA START condition hold time ≥4.0 µs note 1 ≥4.0 µs

tLOW SCL LOW time ≥4.7 µs note 1 ≥4.7 µs

tHIGH SCL HIGH time ≥4.0 µs ≥4.0 µs; note 2 ≥4.0 µs

trC SCL rise time ≤1.0 µs note 3 ≤1.0 µs

tfC SCL fall time ≤0.3 µs ≤0.3 µs; note 4 ≤0.3 µs

SDA timing

tSU;DAT1 data set-up time ≥250 ns note 1 ≥250 ns

tHD;DAT data hold time ≥0 ns note 1 ≥0 ns

tSU;STA repeated START set-up time ≥4.7 µs note 1 ≥4.7 µs

tSU;STO STOP condition set-up time ≥4.0 µs note 1 ≥4.0 µs

tBUF bus free time ≥4.7 µs note 1 ≥4.7 µs

trD SDA rise time ≤1.0 µs note 3 ≤1.0 µs

tfD SDA fall time ≤0.3 µs ≤0.3 µs; note 4 ≤0.3 µs

dth

t rD

t fD t rC t fC

t HD;STA tLOW tHIGH tSU;DAT1 tHD;DATtSU;DAT2

tSU;DAT3

0.7VDD

0.3VDD

tSU;STO

tBUF

tSU;STA

SDA(input / output)

SCL(input / output)

START condition

repeated START condition

STOP condition

START or repeated START condition

0.7VDD

0.3VDD

MLC104

Fig.3 I2C-bus interface timing.

February 1995 13



SAA5290

FUNCTIONAL DESCRIPTION

Introduction

The SAA5290 is an integrated teletext decoder andmicrocontroller. The teletext decoder is derived from theSAA5254 single page teletext decoder IC, with a numberof enhancements to increase its suitability for on-screendisplay applications. The microcontroller is a derivative ofthe industry standard 80C51 microcontroller. A blockdiagram of the SAA5290 is given in Fig.1.

Microcontroller

The functionality of the microcontroller used on theSAA5290 is described here with reference to the industrystandard 80C51 microcontroller. A full description of itsfunctionality can be found in the handbook 80C51-based8-bit microcontrollers IC20. Using the 80C51 as areference, the changes made for the SAA5290 fall into twocategories, features not supported by the SAA5290 andfeatures found on the SAA5290 but not supported by the80C51.

80C51 features not supported by the SAA5290

INTERRUPT PRIORITY

The IP SFR is not implemented and all interrupts aretreated with the same priority level. The SAA5290 retainsthe normal prioritization of interrupts within a level.

Table 6 Interrupts and their vector addresses

EVENT PROGRAM MEMORY ADDRESS

Reset 000H

External INT0 003H

Timer 0 00BH

External INT1 013H

Timer 1 01BH

I2C-bus 053H

OFF-CHIP MEMORY

The SAA5290 does not support the use of off-chipprogram memory or off-chip data memory. This meansthat the SAA5290 does not have any of EA, RD, WR, ALEor PSEN pins. The 4 MOVX instructions which move datato and from external RAM should not be used.

IDLE AND POWER-DOWN MODES

Idle and power-down modes are not supported by theSAA5290. As a consequence, the respective bits in PCONare not available.

UART FUNCTION

The 80C51 UART is not available in the SAA5290. As aconsequence the SCON and SBUF SFRs are removedand the ES bit in the IE SFR is unavailable.

Additional features for the SAA5290

The following features are provided by the SAA5290 inaddition to the standard 80C51 features.

INTERRUPTS

The external INT1 interrupt is modified to generate aninterrupt on both the rising and falling edges of the INT1pin, when EX1 bit is set. This facility allows for softwarepulse width measurement for handling of a remote control.

BIT LEVEL I2C-BUS INTERFACE

The bit-level serial I/O supports the I2C-bus. P1.6/SCL andP1.7/SDA are the serial I/O pins. These two pins meet theI2C-bus specification concerning the input levels andoutput drive capability. Consequently, these pins have anopen-drain output configuration. All the four followingmodes of the I2C-bus are supported.

• Master transmitter

• Master receiver

• Slave transmitter

February 1995 14



SAA5290

• Slave receiver.

The advantages of the bit-level I2C-bus hardware,compared with a full software I2C-bus implementation are:

• The hardware can generate the SCL pulse

• Testing a single bit (RBF or WBF respectively) issufficient as a check for error-free transmission.

The bit-level I2C-bus hardware operates on serial bit leveland performs the following functions:

• Filtering the incoming serial data and clock signals

• Recognizing the START condition

• Generating a serial interrupt request SI after reception ofa START condition and the first falling edge of the serialclock

• Recognizing the STOP condition

• Recognizing a serial clock pulse on the SCL line

• Latching a serial bit on the SDA line (SDI)

• Stretching the SCL LOW period of the serial clock tosuspend the transfer of the next serial data bit

• Setting Read Bit Finished (RBF) when the SCL clockpulse has finished and Write Bit Finished (WBF) if thereis no arbitration loss detected (i.e. SDA = logic 0 whileSDO = logic 1)

• Setting a serial clock LOW-to-HIGH detected (CLH) flag

• Setting a Bus Busy (BB) flag on a START condition andclearing this flag on a STOP condition

• Releasing the SCL line and clearing the CLH, RBF andWBF flags to resume transfer to the next serial data bit

• Generating an automatic clock if the single bit dataregister S1BIT is used in master mode.

The following functions must be done in software:

• Handling the I2C-bus START interrupts

• Converting serial data to parallel data when receiving

• Converting parallel data to serial data when transmitting

• Comparing the received slave address with its ownaddress

• Interpreting the acknowledge information

• Guarding the I2C-bus status if RBF or WBF = logic 0.

Additionally, if acting as master:

• Generating START and STOP conditions

• Handling bus arbitration

• Generating serial clock pulses if S1BIT is not used.

Three SFRs support the function of the bit-level I2C-bushardware, they are S1INT, S1BIT and S1SCS.

LED SUPPORT

Port pins P0.5 and P0.6 have a 10 mA current sinkingcapability to enable LEDs to be driven directly.

PWM DACS

The SAA5290 has six 6-bit PWM DACs and one14-bitPWM DAC. These allow direct control of other parts of thetelevision.

The low resolution 6 bit DACs are controlled by theircorresponding SFR (PWM0 to PWM5) and are connectedas alternative outputs of Port P2. The port bitcorresponding to the PWM should be set to logic 1 forcorrect operation of the PWM.

Table 7 Special Function Registers PWM0 to PWM5

If the PWE bit for a particular port is set to logic 1, the PWMis active and controls its assigned port pin. If the PWE bitis set to logic 0 the corresponding port pin is controlled bythe bit in the corresponding port register for that port.

The output of the PWM is a pulse of period 21.33 µs witha duty cycle determined by the binary value, PV5 to PV0,multiplied by 0.33 µs. The 14 bit PWM is controlled withSFR registers TDACL and TDACH.

Table 8 Special Function Register TDACL

Table 9 Special Function Register TDACH

If the PWE bit is set to logic 1, the TPWM is active andcontrols Port P2.0. If the PWE bit is set to logic 0 the portpin is controlled by the bit in the corresponding portregister for P2.0.

The output of the TPWM is a pulse of period 42.66 µs witha duty cycle determined by the binary value, TD13 to TD7,multiplied by 0.33 µs.

D7 D6 D5 D4 D3 D2 D1 D0

PWE − PV5 PV4 PV3 PV2 PV1 PV0

D7 D6 D5 D4 D3 D2 D1 D0

TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0

D7 D6 D5 D4 D3 D2 D1 D0

PWE − TD13 TD12 TD11 TD10 TD9 TD8

February 1995 15



SAA5290

The 7 least significant bits, TD6 to TD0, extend the HIGHtime of a proportion of the pulses by 0.33 µs. If the LSB isset then 1 in 128 cycles is extended, if bit 1 is set then1 in 64 cycles is extended, and so on.

SOFTWARE ADC

Up to 3 successive approximation ADCs can beimplemented in software by making use of the on-board4-bit DAC and multiplexed voltage comparator. Thesoftware ADC uses 3 analog inputs which are multiplexedwith P3.0 to P3.2.

The control of the ADC is achieved using the SAD SFR.SAD.5 and SAD.6 select one of the three inputs to pass tothe comparator. The other input comes from the DACwhose input is set by SAD bits 0 to 3. The output of thecomparator is SAD bit 7 and is valid by the next instructionafter starting the comparison by setting SAD.ST to logic 1.

Microcontroller interfacing

The 80C51 CPU communicates with the peripheralfunctions using Special Function Registers (SFRs) whichare addressed as RAM locations. The registers in theteletext decoder appear as normal SFRs in themicrocontroller memory map, but are written to using aserial bus. This bus is controlled by dedicated hardwarewhich uses a simple handshake system for softwaresynchronization. The SFR memory map is given inTable 10.

February 1995 16



SAA5290

Tabl

e 10

SA

A52

90 S

peci

al F

unct

ion

Reg

iste

r m

ap (

note

1)

SY

MB

OL

DE

SC

R.

DIR

EC

T A

DD

R.

(HE

X)

BIT

AD

DR

ES

S, S

YM

BO

L O

R A

LTE

RN

ATIV

E P

OR

T F

UN

CT

ION

RE

SE

TVA

LUE

(HE

X)

MS

BLS

B

AC

C(2

)A

ccum

ulat

orE

0HE

7E

6E

5E

4E

3E

2E

1E

000

H

B(2

)B

regi

ster

F0H

F7

F6

F5

F4

F3

F2

F1

F0

00H

DP

TR

:D

ata

Poi

nter

(2by

tes)

:

DP

HH

igh

byte

83H

−−

−−

−−

−−

00H

DP

LLo

w b

yte

82H

−−

−−

−−

−−

00H

IE(2

)(3)

Inte

rrup

tE

nabl

eA

8HA

FA

EA

DA

CA

BA

AA

9A

8X0

H

EA

ES

1∗

∗E

T1

EX

1E

T0

EX

0

P0(

2)P

ort0

80H

8786

8584

8382

8180

FF

H

P1(

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February 1995 17



SAA5290S

1IN

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February 1995 18



SAA5290

Not

es

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he s

tar

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(3)

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D6

D5

D4

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NC

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DE

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OR

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ION

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MS

BLS

B

February 1995 19



SAA5290

Table 11 SFR description

REGISTER FUNCTION

IE - Interrupt Enable

EA Disable all interrupts (logic 0) or use individual enable bits (logic 1).

ES1 I2C-bus interrupt enable (logic 1).

ET1 Enable Timer 1 overflow interrupt (logic 1).

EX1 Enable external interrupt 1 (logic 1).

ET0 Enable Timer 0 overflow interrupt (logic 1).

EX0 Enable external interrupt 0 (logic 1).

PCON - Power Control

GF0 General purpose flag bit 0.

GF1 General purpose flag bit 1.

PWM0 to PWM5 - 6-bit Pulse Width Modulator control registers

PWE Activate this 6-bit PWM and take over port pin (logic 1).

PV0 to PV5 Value to output by this 6-bit PWM.

SAD - Software ADC control

VHI Analog input voltage greater than DAC output voltage (logic 1).

CH0 and CH1 See Table 12.

ST Initiate voltage comparison (logic 1). This is automatically reset.

SAD0 to SAD3 4-bit DAC input value. The DAC output of this value is compared with analog input voltage.

S1BIT - Serial I 2C-bus data (READ)

SDI I2C-bus data bit latched-in from SDA on the last rising edge of SCL.

S1BIT - Serial I 2C-bus data (WRITE)

SDO I2C-bus data bit output.

S1INT - Serial I 2C-bus interrupt

SI I2C-bus interrupt flag.

S1SCS - Serial I 2C-bus control (READ)

SDI Serial data input at SDA.

SCI Serial clock input at SCL.

CLH Clock LOW-to-HIGH transition flag.

BB Bus busy flag.

RBF Read bit finished flag.

WBF Write bit finished flag.

STR Clock stretching enable (logic 1).

ENS Enable serial I/O (logic 1).

February 1995 20



SAA5290

S1SCS - Serial I 2C-bus control (WRITE)

SDO Serial data output at SDA.

SCO Serial clock output at SCL.

CLH Clock LOW-to-HIGH transition.

STR Clock stretching enable (logic 1).

ENS Enable serial I/O (logic 1).

TDACH - 14-bit PWM MSB register

PWE Activate this 14-bit PWM and take over port pin (logic 1).

TD8 to TD13 6 LSBs of this value to be output by the 14-bit PWM.

TDACL - 14-bit PWM LSB register

TD0 to TD7 8 LSBs of this value to be output by the 14-bit PWM.

TXT0 - Teletext register 0 (WRITE only)

X24 POSITION Store packet 24 in extension packet memory (logic 0) or page memory (logic 1).

AUTO FRAME Frame output switched off automatically if any video displayed (logic 1).

DISABLE HDR ROLL Do not write rolling headers and time into memory (logic 1).

STATUS ROW ONLY Display only memory row (logic 1).

DISABLE FRAME Frame output always LOW (logic 1).


8-BIT Data in packets 0 to 24 written into memory without error checking (logic 1).

ACQ OFF Prevent teletext acquisition section writing to memory (logic 1).

X26 Disable automatic processing of packet 26 data (logic 1).

FULL FIELD Accept teletext on TV lines 2 to 22 only (logic 0) or on any line (logic 1).

FIELD POLARITY VSYNC in first half of the line (logic 0) or second half of the line (logic 1) at start of even field.

H POLARITY HSYNC input positive-going (logic 0) or negative-going (logic 1).

V POLARITY VSYNC input positive-going (logic 0) or negative-going (logic 1).


SC0 to SC2 Start column at which page request data written into TXT3 SFR is placed.


PRD0 to PRD4 Page request data.


B MESH ENABLE Enable meshing of area with black background (logic 1).

C MESH ENABLE Enable meshing of area with other background colours (logic 1).

TRANS ENABLE Black background colour is transparent i.e. video is displayed (logic 1).

SHADOW ENABLE Enable south-east shadowing (logic 1).

EAST/WEST Western European languages displayed (logic 0) or Eastern European languages displayed(logic 1).

REGISTER FUNCTION

February 1995 21



SAA5290


BKGND OUT Background colour displayed outside teletext boxes (logic 1).

BKGND IN Background colour displayed inside teletext boxes (logic 1).

COR OUT COR output active outside teletext boxes (logic 1).

COR IN COR output active inside teletext boxes (logic 1).

TEXT OUT Text displayed outside teletext boxes (logic 1).

TEXT IN Text displayed inside teletext boxes (logic 1).

PICTURE ON OUT Video picture displayed outside teletext boxes (logic 1).

PICTURE ON IN Video picture displayed inside teletext boxes (logic 1).


− This register has the same meaning as TXT5 but is only invoked if either newsflash (C5) or thesubtitle (C6) bit in Row 25 of the basic page memory is set.


STATUS ROW TOP Display Row 24 below (logic 0) or above (logic 1) teletext page.

CURSOR ON Display cursor at location pointed to by TXT9 and TXT10 (logic 1).

CONCEAL/REVEAL Display characters in areas with the conceal attribute set (logic 1).

TOP/BOTTOM Display Rows 0 to 11 (logic 0) or 12 to 23 (logic 1) when the double height bit is set.

SNG/DBL HEIGHT Display each character at twice normal height (logic 1).

BOX ON 24 Enable teletext boxes in memory Row 24 (logic 1).

BOX ON 1-23 Enable teletext boxes in memory Rows 1 to 23 (logic 1).

BOX ON 0 Enable teletext boxes in memory Row 0 (logic 1).


CVBS0/CVBS1 CVBS0 input (logic 0) or CVBS1 (logic 1) inputs used for teletext.


CLEAR MEMORY Write 20H into every location in teletext memory (logic 1).

A0 Access basic page memory (logic 0) or extension packet memory (logic 1) with TXT11 SFR.

R0 to R4 Memory row to be accessed with TXT11 SFR.


C0 to C5 Memory column to be accessed with TXT11 SFR.

TXT11 - Teletext register 11

D0 to D7 data byte written to, or read from, teletext memory.

REGISTER FUNCTION

February 1995 22



SAA5290

Table 12 CH1 and CH0 selection

TXT12 - Teletext register 12 (READ only)

625/525 SYNC A 625 line CVBS signal (logic 0), or a 525 line CVBS signal (logic 1) is being input.

ROM VER R0 to R4 Mask programmable to identify character set version.

TXT ON Teletext power has been applied to the device (logic 1).

VIDEO QUALITY CVBS input can be locked on by the teletext decoder (logic 1).

TXT13 - Teletext register 13 (READ only)

TXT I/FACE BUSY Text interface busy and no access for either READ or WRITE is allowed to SFRsTXT0 to TXT11 (logic 1). This register bit performs the software handshake to the teletextcontrol registers.

CH1 CH0 INPUT PIN

0 0 none

0 1 ADC0

1 0 ADC1

1 1 ADC2

REGISTER FUNCTION

February 1995 23



SAA5290

TELETEXT DECODER FUNCTIONAL DESCRIPTION

Data slicer

The data slicer extracts the digital teletext data from theincoming analog waveform. This is performed by samplingthe CVBS waveform and processing the samples toextract the teletext data and clock.

Acquisition timing

The acquisition timing is generated from a logic levelpositive-going composite sync signal ‘VCS’. This signal isgenerated by the sync separator circuit which adaptivelyslices the sync pulses at 50% of their height. It is able to dothis over a wide range of sync amplitudes by using thesame basic principle used on VIP1 (SAA5230) and VIP2(SAA5231).

Figure 4 is a block diagram showing the principles ofoperation. It relies upon the fact that the ratio of the syncwidth to the line time is approximately 13 : 1. In order toslice the sync pulse at the correct 50% level two currentsare generated.

One is constant and is proportional to the differencebetween the black level of the video and the slicing level.The other is produced only when the video is below theslicing level, and is also proportional to the differencebetween the slicing level and the input, but has amagnitude13 times greater.

The black level is determined by a sync-gated peakdetector. The video is negatively peak detected into anexternal capacitor (BLACK, pin 25), but not during thesync pulse VCS. The two currents are integrated on theCVBS input coupling capacitor and the net effect is to alterthe mean input voltage until the (fixed) slicing level iscorrect.

The acquisition clocking and timing are locked to the VCSsignal using a digital phased-locked-loop. The phase errorin the acquisition phase-locked-loop is detected by asignal quality circuit which disables acquisition if poorsignal quality is detected.

Fig.4 Sync separator block diagram.


MLC105

VDD

Vref

Vref

Vref

CVBS

(= slicing level)

FILTER

FILTER

gated negative peak detector

BLACK

VCS

1/3V (mA)i

1/39V (mA)i

February 1995 24



SAA5290

Teletext acquisition

The SAA5290 is able to acquire 625-line World SystemTeletext. Teletext is acquired under control of the on-board80C51 microcontroller. Pages are requested by writing aseries of bytes into the TXT3 SFR which corresponds tothe number of the page required. The bytes written intoTXT3 are put into a small RAM with an auto-incrementingaddress. The start address for the RAM is set using theSFR TXT2 register. Table 13 shows the contents of thepage request RAM.

If the ‘DO CARE’ bit for part of the page number is set tologic 0 then that part of the page number is ignored whenthe acquisition section is deciding whether a page beingreceived off air should be stored or not. For example if the‘DO CARE’ bits for the 4 subcode digits are all set tologic 0 then every subcode version of the page will becaptured.

When the ‘HOLD' bit is set to logic 0 the acquisition sectionwill not recognize any page as having the correct pagenumber and no pages will be captured.

Table 13 Register map for page requests (TXT3); note 1

Note

1. X = don't care.

STARTCOLUMN

PRD4 PRD3 PRD2 PRD1 PRD0

0 DO CARE

Magazine HOLD MAG2 MAG1 MAG0

1 DO CARE

Page tens PT3 PT2 PT1 PT0

2 DO CARE

Page units PU3 PU2 PU1 PU0

3 DO CARE

Hours tens X X HT1 HT0

4 DO CARE

Hours units HU3 HU2 HU1 HU0

5 DO CARE

Minutes tens X MT2 MT1 MT0

6 DO CARE

Minutes units MU3 MU2 MU1 MU0

Page memory organization

The acquired teletext packets each contain 40 bytes ofdata and one packet is stored in each row of the textmemory. The page memory organization is given in Fig.5.Rows 0 to 23 form the teletext page; Row 24 is availablefor status messages and FLOF/FASTEXT promptinformation.

February 1995 25



SAA5290

Fig.5 Basic page memory organization.


MLC106

7 charactersfor status

8 charactersusually rolling

(time)

fixed character written byhardware, alphanumerics white nor-mally, alphanumerics green when

looking for display page

61 7 8 3931 32

24 characters from page headerrolling when display page looked for

5to20

01234

ROW

2122232425

MAIN PAGE DISPLAY AREA

PACKET X / 22PACKET X / 23

PACKET X24 STORED HERE IF TXT0.7 = 110 14

10 bytes forreceived

page information

14 bytesfree for use

by microcontroller

ROW 0 (see Fig.5)

Row 0 is for the page header. The first seven characters(0 to 6) are free for status messages. Character 8 is analphanumeric white or green control character, writtenautomatically by SAA5290 to give a green rolling headerwhen a page is being looked for. The last eight charactersare for rolling time.

ROW 25 (see Fig.5)

The first 10 bytes of row 25 contain control data relating tothe received page as shown in Table 14. The remaining 14bytes are free for use by the microcontroller.

Extension packet memory organization

If TXT0.X24 POS bit is set to logic 0, then Packet 24 iswritten into Row 0 of the extension memory.

Packet X27/0 is written to Row 1 of the extension memory,with bytes 0 to 37 being Hamming checked automatically.

Packet 8/30 is written to Row 2 of the extension memory,with bytes 0 to 6 being 8/4 Hamming checked, bytes7 to 19 unchecked and bytes 20 to 39 odd parity checked.

Packet 26 processing

The SAA5290 contains on-board hardware processing ofPacket 26 data. If a character corresponding to that beingtransmitted is available in the character set then thecorrect character code is written into the display memory.

Fig.6 Organization of the extension memory.

handbook, halfpage

MLC107

PACKET X24 if TXT0.X24 POS = 0

PACKET X27 / 0

PACKETS 8 / 30 / 0 to 15

1

0

2

ROW

February 1995 26



SAA5290

Table 14 Row 25 received control data format

Table 15 Page number and sub-code for Table 14

ROW 25

D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0

D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0

D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0

D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0

D4 HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND 0

D5 0 0 0 0 0 0 0 0 0 PBLF

D6 0 0 0 0 0 0 0 0 0 0

D7 0 0 0 0 0 0 0 0 0 0

Column 0 1 2 3 4 5 6 7 8 9

BIT NAME DESCRIPTION

Page number

MAG magazine

PU page units

PT page tens

PBLF page being looked for

HAM.ER Hamming error in corresponding byte

Page sub-code

MU minutes units

MT minutes tens

HU hours units

HT hours tens

C4 to C14 transmitted control bits

February 1995 27



SAA5290

Display

The capabilities of the display are based on therequirements of level 1 teletext, with some enhancementsfor use with locally generated On-Screen Displays (OSD).

The display consists of 25 rows each of 40 characters,with the characters displayed being those fromRows 0 to 24 of the basic page memory. The pagememory stores 8-bit character codes which correspond to260 displayable characters and 44 control codes, normallydisplayed as spaces. Each character is defined by a matrix12 pixels high and 10 pixels deep. When displayed eachpixel is 0.5 µs wide and 1 TV line, in each field, high.

The SAA5290 signals the TV display circuits to display theRGB outputs of the SAA5290 rather than video picture bysetting VDS HIGH. The way in which this signal is switchedis controlled by the TXT5 and TXT6 SFRs. There are threecontrol functions: background on, text on and picture on.There are separate bits for each function for inside andoutside teletext boxes and if the newsflash or subtitle bitsare set. This allows the software to configure the type ofdisplay required. The effect of the combination of thesebits is given in Table 16. The COR bits in Register 5 andRegister 6 control when the output is pulled LOW. Thisoutput is intended to act on the TV display circuits toreduce the contrast of the video display.

The display character set is given in Fig.9. The characterset provided contains all the characters required to displayEastern and Western European languages. Register bitTXT4.EAST/ WEST sets whether Eastern or Westernlanguages are set with the C12 to C14 bits. In order tomake on-screen displays easy to use, the SAA5290contains additional display attributes in Column 11.

Control codes are categorized as ‘set at’ or ‘set after’.‘Set at’ means the code has effect at the current characterposition and ‘set after’ means they have effect from thefollowing character. Codes 11/0 to 11/7 are always‘set at’. Codes 11/11 to 11/15 are ‘set after’ when definingthe start of an OSD box and ‘set at’ when ending an OSDbox. Codes 11/12 to 11/15 force a box condition allowingon-screen display messages to be displayed withouthaving to erase the whole contents of the teletext page.

On-screen displays are only available in TV mode and notin text mode. In mixed text and TV mode the displayedscreen is not defined if an OSD box is encountered in thepage memory.

Table 16 Display mode

PICTURE ON TEXT ON BACKGROUND ON RESULT

0 0 X text mode, black screen

0 1 0 text mode, background always black

0 1 1 text mode

1 0 X TV mode

1 1 0 mixed mode and TV mode

1 1 1 text mode, TV picture outside text area

Display timing

The display circuitry is driven from the H/VSYNC inputs,and is independent of the input video signal. ConsequentlyHSYNC and VSYNC are always required to slavesynchronize the display.

The FRAME output of the SAA5290 is provided to facilitatede-interlacing the teletext display. The behaviour ofFRAME is controlled via the register bitsTXT0.DISABLE FRAME, TXT0.AUTO FRAME andTXT1.FIELD POLARITY. If the active edge of VSYNCoccurs in the first half of a TV line then the field is even, and

if the active edge of VSYNC is in the second half of a linethen the field is odd. The active edge is controlled withTXT1.V POLARITY. With TXT0.AUTO FRAME LOWFRAME is HIGH for an odd field and LOW for an evenfield. With TXT0.AUTO FRAME HIGH FRAME is onlyactive when text is being displayed, when video isdisplayed it is forced LOW. When TXT0.DISABLE FRAMEis HIGH FRAME is always LOW. IfTXT1.FIELD POLARITY is logic 1 then VSYNC is delayedby 32 µs before being applied to the display timing circuits.

February 1995 28



SAA5290

Clock generator

The oscillator circuit of the SAA5290 is a single-stageinverting amplifier in a Pierce oscillator configuration. Thecircuitry between OSCIN and OSCOUT is basically aninverter biased to the transfer point. A crystal must beused as the feedback element to complete the oscillator

circuitry. It is operated in parallel resonance. OSCIN is thehigh gain amplifier input and OSCOUT is the output. Todrive the SAA5290 externally OSCIN is driven from anexternal source and OSCOUT is left open-circuit.

Fig.7 Oscillator circuit.

(1) The values of C1 and C2 depend on the crystal specification:C1 = C2 = 2CL.

handbook, halfpage

MLC110

OSCOUT

OSCIN

OSCGND

C1(1)

C2(1)

Fig.8 Oscillator circuit driven from external source.

handbook, halfpage

MLC111

OSCOUT

OSCIN

OSCGNDnot connected

external clock

not connected

February 1995 29



SAA5290

CHARACTER SETS


MLC

108

norm

al

heig

ht

b3

b2

b1

b0b4

b5

b6

b7

01

22a

33a

45

66a

77a

89

Cco

lum

nr o w

B I T

S

0

0

0

0

0

0

0

1

0

1

0

0

0

1

0

1

1

0

0

0

1

0

0

1

A

1

0

1

0

1

1

0

0

0

1

1

0

0

0

1

1

0

0

1

0

0

1

1

1

E1

1

1

0

doub

le

wid

thho

ld

grap

hics

F1

1

1

1

doub

le

size

rele

ase

grap

hics

B1

0

1

1

star

t box

C1

1

0

0

blac

k ba

ck -

gr

ound

D1

1

0

1

doub

le

heig

ht

new

ba

ck -

gr

ound

A1

0

1

0

end

box

sepa

rate

d gr

aphi

cs

91

0

0

1

stea

dyco

ntig

uous

gr

aphi

cs

81

0

0

0

flash

conc

eal

disp

lay

70

1

1

1

alph

a -

num

eric

s w

hite

grap

hics

w

hite

60

1

1

0

alph

a -

num

eric

s cy

an

grap

hics

cy

an

50

1

0

1

alph

a -

num

eric

s m

agen

ta

grap

hics

m

agen

ta

40

1

0

0

alph

a -

num

eric

s bl

ue

grap

hics

bl

ue

30

0

1

1

alph

a -

num

eric

s ye

llow

grap

hics

ye

llow

20

0

1

0

alph

a -

num

eric

s gr

een

grap

hics

gr

een

00

0

0

0

alph

a -

num

eric

s bl

ack

grap

hics

bl

ack

10

0

0

1

alph

a -

num

eric

s re

d

grap

hics

re

d

B

1

0

1

1

DE

F

1

1

0

1

1

1

1

0

1

1

1

1

DE

F

1

1

0

1

1

1

1

0

1

1

1

1

doub

le

wid

th

OS

D

doub

le

size

O

SD

norm

al

size

O

SD

doub

le

heig

ht

OS

D

back

- gr

ound

w

hite

back

- gr

ound

cy

an

back

- gr

ound

m

agen

ta

back

- gr

ound

bl

ue

back

- gr

ound

ye

llow

back

- gr

ound

gr

een

back

- gr

ound

bl

ack

back

gr

ound

re

d

Fig

.9 S

AA

5290

Eur

opea

n ch

arac

ter

set.

February 1995 30



SAA5290

Fig.10 SAA5290 European national option characters.


MLC109

LANGUAGEC12 C13 C14

PHCB

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0FRENCH

ITALIAN

SWEDISH

GERMAN

ENGLISH

2 / 3 2 / 4 4 / 0 5 / B 5 / C 5 / D 5 / E 5 / F 6 / 0 7 / B 7 / C 7 / D 7 / E

CHARACTER POSITION (COLUMN / ROW)

SPANISH 1 0

E/W

0

1 1 1ENGLISH 0

0

0 0 1GERMAN 1

0 1 0ESTONIAN 1

0 1 1GERMAN 1

1 0 0GERMAN 1

0

0

0

0 1

1 10 0TURKISH

0 01 0

1 0 1

1 1 0

1 1

1

1

1 1RUMANIAN

CZECHOSLOVAKIA

SERBO-CROAT

POLISH

February 1995 31



SAA5290

APPLICATION INFORMATION


MLC

112

VD

D40

V

Vtu

ne

P2.

0/T

PW

M

P2.

1/P

WM

0

P2.

2/P

WM

1

P2.

3/P

WM

2

P2.

4/P

WM

3

P2.

5/P

WM

4

P2.

6/P

WM

5

P2.

7

P3.

0/A

DC

0

P3.

1/A

DC

1

P3.

2/A

DC

2

P3.

3

VS

SD

P0.

0

P0.

1

P0.

2

P0.

3

P0.

4

P0.

5

P0.

6

P0.

7

VS

SA

CV

BS

0

CV

BS

1

BLA

CK

IRE

F

brig

htne

ss

cont

rast

satu

ratio

n

hue

volu

me

(L)

volu

me

(R)

Vaf

cVD

D

27 k

Ω10

0nF

CV

BS

(S

CA

RT

)

CV

BS

(IF

)

100

nF

100

nF

VD

D

VD

D

P1.

5

P1.

4

P1.

7/S

DA

P1.

6/S

CL

P1.

3/T

1

P1.

2/IN

T0

P1.

1/T

0

P1.

0/IN

T1

RE

SE

T

OS

CO

UT

OS

CIN

VS

YN

C

HS

YN

C

VD

S R G B

P3.

4

CO

R

RG

BR

EF

FR

AM

E

VD

DM

OS

CG

ND

VD

DT

VD

DA

VS

SD

2SD

A

SC

L

RC

A0

SA

A52

90EE

PR

OM

PC

F85

82E

A1

A2

VD

D

VS

S

VD

D

VD

DV

DD

100

nF47 µ

FV

DD

4.7

kΩ

TV

cont

rol

sign

als

IRR

EC

EIV

ER

VD

D

VD

D

2.2

µF

12 M

Hz V

DD

VD

D

100

nF47 µF

field

flyb

ack

line

flyba

ck

to T

V's

disp

lay

circ

uits

VD

D

1 kΩ10 kΩ

3.3

kΩ10

0 nF

PH

2369

1 kΩ

Fig

.11

Typ

ical

app

licat

ion

diag

ram

.

February 1995 32



SAA5290

PACKAGE OUTLINE

Fig

.12

Pla

stic

shr

ink

dual

in-li

ne p

acka

ge; 5

2le

ads

(600

mil)

SD

IP52

, SO

T24

7-1.

Dim

ensi

ons

in m

m.

hand

book

, ful

l pag

ewid

th

1

27 26

1.3

max

14.1

13

.7

47.9

2 47

.02

4.57

m

ax5.

08

max

0.51

m

in

3.2

2.8

seating plane

0.18

M0.

53

max

1.77

8(2

5x)

1.73

m

ax

15.8

0 15

.24

0.32

max

15.2

4

17.1

5 15

.90

MS

A26

7

52

February 1995 33



SAA5290

SOLDERING

Plastic dual in-line packages

BY DIP OR WAVE

The maximum permissible temperature of the solder is260 °C; this temperature must not be in contact with thejoint for more than 5 s. The total contact time of successivesolder waves must not exceed 5 s.

The device may be mounted up to the seating plane, butthe temperature of the plastic body must not exceed the

specified storage maximum. If the printed-circuit board hasbeen pre-heated, forced cooling may be necessaryimmediately after soldering to keep the temperature withinthe permissible limit.

REPAIRING SOLDERED JOINTS

Apply the soldering iron below the seating plane (or notmore than 2 mm above it). If its temperature is below300 °C, it must not be in contact for more than 10 s; ifbetween 300 and 400 °C, for not more than 5 s.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of theseproducts can reasonably be expected to result in personal injury. Philips customers using or selling these products foruse in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from suchimproper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one ormore of the limiting values may cause permanent damage to the device. These are stress ratings only and operationof the device at these or at any other conditions above those given in the Characteristics sections of the specificationis not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use thecomponents in the I2C system provided the system conforms to the I2C specification defined byPhilips. This specification can be ordered using the code 9398 393 40011.

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

http://www.datasheetcatalog.com



Documents

DATA SHEET - radiocom.dn.uaradiocom.dn.ua/image/data/pdf/SAA5290ZP_PHI.pdf · DATA SHEET Preliminary speciﬁcation File under Integrated Circuits, IC02 February 1995 ... •Standby