DARPA Simulation and Synthesis of Quantum Circuits Igor L. Markov and John P. Hayes Advanced Computer Architecture Laboratory University of Michigan, EECS

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Simulation and SynthesisSimulation and Synthesisof Quantum Circuitsof Quantum Circuits

Igor L. Markov and John P. HayesIgor L. Markov and John P. HayesAdvanced Computer Architecture LaboratoryAdvanced Computer Architecture Laboratory

University of Michigan, EECSUniversity of Michigan, EECS

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Quantum Circuits Group @UMichQuantum Circuits Group @UMich

PIs: Prof. PIs: Prof. Igor MarkovIgor Markov & Prof. & Prof. John HayesJohn HayesPostdoc: Dr. Postdoc: Dr. Ketan PatelKetan Patel (circuit testing) (circuit testing)Graduate Student Researchers & FellowsGraduate Student Researchers & Fellows

George ViamontesGeorge Viamontes (simulation/QuIDDs) (simulation/QuIDDs)Manoj RajagopalanManoj Rajagopalan (simulation, synthesis by SA) (simulation, synthesis by SA)DoRon Motter DoRon Motter (circuit complexity) (circuit complexity)Smita KrishnaswamySmita Krishnaswamy (quantum clocks) (quantum clocks)Parmoon SeddighradParmoon Seddighrad (technology-specific opt.) (technology-specific opt.)

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High-level Assumptions and GoalsHigh-level Assumptions and Goals

Assumption: Assumption: physicists [will] have “promising” physicists [will] have “promising” technology prototypestechnology prototypes

Expectation: Expectation: at 20+ qubits, design complexity at 20+ qubits, design complexity becomes a serious issuebecomes a serious issue Even at 20 bits, optimal logic synthesis is difficultEven at 20 bits, optimal logic synthesis is difficult

Our job: Our job: improve the competitiveness of improve the competitiveness of prototypes and facilitate applicationsprototypes and facilitate applications Address specific design objectives and trade-offsAddress specific design objectives and trade-offs Discover scalable design/simulation techniquesDiscover scalable design/simulation techniques Connect design techniques with applicationsConnect design techniques with applications Id new types of q. circuits and new applicationsId new types of q. circuits and new applications

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Our ExpertiseOur Expertise

Computer ArchitectureComputer ArchitectureElectronic Design AutomationElectronic Design Automation / VLSI CAD / VLSI CAD

Automated Synthesis of Logic CircuitsAutomated Synthesis of Logic CircuitsFormal VerificationFormal VerificationCircuit LayoutCircuit LayoutCircuit TestingCircuit Testing

Design & analysis of algorithms/heuristicsDesign & analysis of algorithms/heuristics Including Algorithm EngineeringIncluding Algorithm Engineering

(implementation, evaluation, integration)(implementation, evaluation, integration)

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Design Productivity GapDesign Productivity Gap

NTRS / ITRS: Design Productivity GapNTRS / ITRS: Design Productivity Gapis roughly is roughly 49% a year49% a year vs vs 21% a year21% a year

Is “quantum D. P. G.” looming ?Is “quantum D. P. G.” looming ?

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Fundamental Optimizations Fundamental Optimizations

Research in Design AutomationResearch in Design Automationtargets targets core computational obstaclescore computational obstaclesE.g., scalability in terms of runtime & QORE.g., scalability in terms of runtime & QORValue in trying to solve “wrong” problemsValue in trying to solve “wrong” problems

Many optimization algorithmsMany optimization algorithmscan be easily “re-focused”can be easily “re-focused”Different objectives and constraintsDifferent objectives and constraintsExampleExample: Simulated Annealing : Simulated Annealing

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Research Themes (1)Research Themes (1)

““From classical to quantum”From classical to quantum” Use classical reversible circuits as [simple] test-bedUse classical reversible circuits as [simple] test-bed Leverage and generalize known design techniquesLeverage and generalize known design techniques

for classical circuitsfor classical circuits

Simulation-driven designSimulation-driven design Support for quantum circuit testingSupport for quantum circuit testing Ability to incrementally improve designsAbility to incrementally improve designs

based on results of simulations/testsbased on results of simulations/tests Ability to empirically evaluate quantum designsAbility to empirically evaluate quantum designs

and algorithms without easily-provable propertiesand algorithms without easily-provable properties

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Research Themes (2)Research Themes (2)

New types of quantum circuitsNew types of quantum circuits Case-by-case automatic synthesis Case-by-case automatic synthesis

versus asymptotic constructionsversus asymptotic constructions ““Real life” vs theory (cf. synthesis of classical random logic)Real life” vs theory (cf. synthesis of classical random logic)

Empirical performance versus provable resultsEmpirical performance versus provable results Separate design and simulation/test stagesSeparate design and simulation/test stages

Example: sequential versus combinationalExample: sequential versus combinational

New applicationsNew applications Enabled by automatic synthesisEnabled by automatic synthesis Leveraging new types of circuits, e.g., sequentialLeveraging new types of circuits, e.g., sequential

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Research Topics (1)Research Topics (1) Synthesis algorithms for Synthesis algorithms for classical logicclassical logic as as

subroutines for quantum circuit synthesissubroutines for quantum circuit synthesis Algebraic approaches to circuit synthesisAlgebraic approaches to circuit synthesis

E.g., abstract E.g., abstract andand computational group theory computational group theory Matrix factorizations: Matrix factorizations: QR, ILU, CSQR, ILU, CS and and KAKKAK Special-case synthesis, e.g., Grover oraclesSpecial-case synthesis, e.g., Grover oracles

Generic quantum circuit synthesis and reductionGeneric quantum circuit synthesis and reduction Dynamic programmingDynamic programming Annealing and other heuristicsAnnealing and other heuristics

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Research Topics (2)Research Topics (2)Automatic error correction during synthesisAutomatic error correction during synthesisEfficient simulation of quantum circuitsEfficient simulation of quantum circuits

Graph-theoretical algorithms based on common Graph-theoretical algorithms based on common arithmetic sub-expressions (QUIDDs)arithmetic sub-expressions (QUIDDs)

New types of quantum circuitsNew types of quantum circuitsQuantum clocks and other sequential circuitsQuantum clocks and other sequential circuits

New [and old] applicationsNew [and old] applicationsQuantum optimization algorithms (heuristics)Quantum optimization algorithms (heuristics)Memory-savvy versions of known algorithmsMemory-savvy versions of known algorithms

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Remaining Part Of The TalkRemaining Part Of The Talk

Synthesis of Reversible Logic CircuitsSynthesis of Reversible Logic Circuitsand Applications to Grover’s Searchand Applications to Grover’s Search

Synthesis of Quantum CircuitsSynthesis of Quantum Circuitsby Simulated Annealingby Simulated Annealing

High-performance SimulationHigh-performance Simulationof Quantum Circuits using QuIDDsof Quantum Circuits using QuIDDs

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Optimal Synthesis ofOptimal Synthesis ofReversible Logic CircuitsReversible Logic Circuits

Vivek V. Shende, Aditya K. Prasad,Vivek V. Shende, Aditya K. Prasad, Igor L. Markov and John P. Hayes Igor L. Markov and John P. Hayes

Advanced Computer Architecture LaboratoryAdvanced Computer Architecture Laboratory


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OutlineOutline

MotivationMotivationReal-world ApplicationsReal-world ApplicationsAsymptotically Zero-Energy circuitsAsymptotically Zero-Energy circuitsLinks to Quantum ComputationLinks to Quantum Computation

Background Background Theoretical ResultsTheoretical ResultsSynthesis of Optimal CircuitsSynthesis of Optimal CircuitsAn Application to Quantum ComputingAn Application to Quantum Computing

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Real-world ApplicationsReal-world Applications

Many Many inherently reversible applicationsinherently reversible applications Info. is re-coded, but none is lost or addedInfo. is re-coded, but none is lost or added

Digital signal processingDigital signal processingCryptography Cryptography CommunicationsCommunicationsComputer graphicsComputer graphicsNetwork congestion modelingNetwork congestion modeling

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Links to Quantum ComputationLinks to Quantum Computation

Quantum operations are all reversibleQuantum operations are all reversible Every (classical) reversible circuit may be Every (classical) reversible circuit may be

implementedimplemented in quantum technology, with overhead in quantum technology, with overhead ““Pseudo-classical” subroutinesPseudo-classical” subroutines of quantum algos of quantum algos

Can be implemented in classical reversible logic circuitsCan be implemented in classical reversible logic circuits

Grover’sGrover’ssearchsearch : :

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OutlineOutline

MotivationMotivationBackgroundBackground

ReversibilityReversibilityPermutationsPermutationsKnown FactsKnown Facts

Theoretical ResultsTheoretical ResultsSynthesis of Optimal CircuitsSynthesis of Optimal CircuitsAn Application to Quantum ComputingAn Application to Quantum Computing

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Reversibility in Logic GatesReversibility in Logic Gates Definition:Definition: reversible logic gate reversible logic gate

#input wires = #output wires#input wires = #output wires Permutes the set of input values Permutes the set of input values

Examples Examples InverterInverter 22-input, -input, 22-output SWAP (S) gate-output SWAP (S) gate

kk-CNOT gate-CNOT gate ((k+1k+1))-inputs and -inputs and ((k+1k+1))-outputs-outputs Values on the first Values on the first kk wires are unchanged wires are unchanged The last value is flipped if the first The last value is flipped if the first kk were all were all 11

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Reversibility in Logic CircuitsReversibility in Logic Circuits

Definition:Definition:A combinational logic circuit is A combinational logic circuit is reversiblereversible iff iff It contains only It contains only reversible gatesreversible gates It has no It has no fan-outfan-out It is It is acyclicacyclic as a directed multi-graph as a directed multi-graph

Theorem:Theorem:A reversible circuit mustA reversible circuit mustHave as many input wires as output wires Have as many input wires as output wires Permute the set of input valuesPermute the set of input values

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A Reversible Circuit and Truth TableA Reversible Circuit and Truth Table

xx yy zz x’x’ y’y’ z’z’

00 00 00 00 00 00

00 00 11 00 00 11

00 11 00 00 11 11

00 11 11 00 11 00

11 00 00 11 00 00

11 00 11 11 00 11

11 11 00 11 11 11

11 11 11 11 11 00

Equivalent to a single CNOT gate

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Circuit EquivalencesCircuit Equivalences

Circuit equivalences: useful in synthesisMore will be shown later

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Reversible Circuits & PermutationsReversible Circuits & Permutations

A reversible gate (or circuit) with A reversible gate (or circuit) with nn inputs inputs and and nn outputs has outputs has 22nn possible input values possible input values 22nn possible output values possible output values

The function it computes on this set must, The function it computes on this set must, by definition, be a permutationby definition, be a permutation

The set of such permutations is called SThe set of such permutations is called S22nn

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Basic Facts About PermutationsBasic Facts About Permutations

Permutations are multiplied by first Permutations are multiplied by first applying one, then the other applying one, then the other example: example: (1,2)◦(2,3) = (1,3,2)(1,2)◦(2,3) = (1,3,2)

A transposition A transposition permutes exactly two elementspermutes exactly two elementsdoes not change any othersdoes not change any others

Every permutation can be writtenEvery permutation can be writtenas a product of transpositionsas a product of transpositions

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Even PermutationsEven Permutations

Consider all possible decompositionsConsider all possible decompositionsof a permutation into transpositionsof a permutation into transpositions

Theorem:Theorem: The parity of the number The parity of the numberof transpositions is constantof transpositions is constant

Definition: Even permutationsDefinition: Even permutations are those for are those for which which the number of transpositions is eventhe number of transpositions is even

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Known FactsKnown Facts

Fact 1Fact 1: Consider a reversible circuit: Consider a reversible circuit n+1n+1 inputs and inputs and n+1n+1 outputs outputs Built from gates which have Built from gates which have

at most at most nn inputs and inputs and nn outputs outputs Must compute an even permutationMust compute an even permutation

Fact 2Fact 2: A universal gate library: A universal gate libraryCNOT, NOT, and TOFFOLI (“CNT”)CNOT, NOT, and TOFFOLI (“CNT”)Temporary storage may be requiredTemporary storage may be required

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Temporary StorageTemporary Storage

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OutlineOutline

MotivationMotivationBackground Background Theoretical ResultsTheoretical Results

Zero-storage CircuitsZero-storage CircuitsReversible De Morgan’s LawsReversible De Morgan’s Laws

Synthesis of Optimal CircuitsSynthesis of Optimal CircuitsAn Application to Quantum ComputingAn Application to Quantum Computing

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Minimizing Temporary StorageMinimizing Temporary Storage

Consider CNT circuitsConsider CNT circuitsTheorem:Theorem: even permutations computable even permutations computable

by circuits by circuits without temporary storagewithout temporary storageTheorem:Theorem: odd permutations computable odd permutations computable

with one line of temporary storagewith one line of temporary storageSame holds for NT and CNTS circuitsSame holds for NT and CNTS circuitsThe proof is constructive and The proof is constructive and

may be used as a synthesis heuristicmay be used as a synthesis heuristic

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Outline of ProofOutline of Proof

Explicitly construct a circuit to computeExplicitly construct a circuit to computean arbitrary pair of an arbitrary pair of disjointdisjoint transpositions transpositions (A, B) (C, D) is okay(A, B) (C, D) is okay; ; (A, B) (B, C) is not(A, B) (B, C) is not

Pick an even permutationPick an even permutationDecompose it into transpositionsDecompose it into transpositions

Will have an even number of transpositionsWill have an even number of transpositionsPair these up, Pair these up, guaranteeing disjointnessguaranteeing disjointnessApply construction to each pairApply construction to each pair

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Flowchart of ProofFlowchart of Proof

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Reversible De Morgan’s Laws (1)Reversible De Morgan’s Laws (1)

De Morgan’s Laws De Morgan’s Laws Can send inverters to inputs in Can send inverters to inputs in AND/OR/NOT circuitsAND/OR/NOT circuits

Reversible De Morgan’s LawsReversible De Morgan’s Laws Can send inverters to inputs in Can send inverters to inputs in CNT circuitsCNT circuits

Rules exist to move TOFFOLI and CNOT gatesRules exist to move TOFFOLI and CNOT gates HoweverHowever, , it is it is notnot always possible always possible

to push all CNOT gates to the inputsto push all CNOT gates to the inputs Oddly enough, Oddly enough, all CNOT gates can be pushed to the all CNOT gates can be pushed to the

“middle” of the circuit“middle” of the circuit

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OutlineOutline

MotivationMotivationBackground Background Theoretical ResultsTheoretical ResultsSynthesis of Optimal CircuitsSynthesis of Optimal Circuits

OptimalityOptimalityDFID Search AlgorithmDFID Search AlgorithmCircuit LibrariesCircuit Libraries

An Application to Quantum ComputingAn Application to Quantum Computing

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OptimalityOptimality

The cost of a circuit is its The cost of a circuit is its gate countgate countOther cost functions can be consideredOther cost functions can be considered

DefinitionDefinition:: optimal reversible circuit optimal reversible circuit no circuit with fewer gates computes no circuit with fewer gates computes

the same permutationthe same permutationTheoremTheorem: a sub-circuit of an optimal circuit : a sub-circuit of an optimal circuit

is optimalis optimalProofProof: otherwise, can improve the sub-circuit: otherwise, can improve the sub-circuit

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The Search ProcedureThe Search Procedure

Depth First Iterative DeepeningDepth First Iterative Deepening Search SearchChecks all possible circuits of cost 1, then all Checks all possible circuits of cost 1, then all

possible circuits of cost 2, etc…possible circuits of cost 2, etc…Avoids the memory blowup of Avoids the memory blowup of BFSBFS

Still finds optimal solutions (unlike Still finds optimal solutions (unlike DFSDFS))Checking circuits of cost less than Checking circuits of cost less than nn is is

much faster than processing cost-much faster than processing cost-nn circuits circuits

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Dynamic Prog + Circuit LibrariesDynamic Prog + Circuit Libraries

DFID search requires a subroutine to checkDFID search requires a subroutine to checkall circuits of cost all circuits of cost nn, for arbitrary , for arbitrary nnCalled iteratively for Called iteratively for 1…n1…n

Only need to check Only need to check locally optimal circuitslocally optimal circuits Build optimal circuit library bottom up by DPBuild optimal circuit library bottom up by DP

Index optimal circuits by computed permutationIndex optimal circuits by computed permutation In practice use hash_map datastruct from STLIn practice use hash_map datastruct from STL

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Synthesis AlgorithmSynthesis Algorithm

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Empirical Circuit SynthesisEmpirical Circuit Synthesis

Consider Consider allall reversible functions on 3 wires reversible functions on 3 wires((8! = 40,320 functions8! = 40,320 functions))

For each gate library fromFor each gate library fromN, C, T, NC, CT, NT, CNT, CNTSN, C, T, NC, CT, NT, CNT, CNTS Is it Is it universaluniversal??How many functions can it synthesize?How many functions can it synthesize?How long does it take to synthesize circuits?How long does it take to synthesize circuits?What are largest optimal circuits?What are largest optimal circuits?

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Optimal Circuit SizesOptimal Circuit SizesSize N C T NC CT NT CNT CNTS

12 0 0 0 0 0 47 0 011 0 0 0 0 0 1690 0 010 0 0 0 0 0 8363 0 0

9 0 0 0 0 0 12237 0 08 0 0 0 0 6 9339 577 327 0 0 0 14 386 5097 10253 6817

6 0 2 0 215 1688 2262 17049 17531

5 0 24 0 474 1784 870 8921 111944 0 60 5 393 845 296 2780 37523 1 51 9 187 261 88 625 8442 3 24 6 51 60 24 102 1351 3 6 3 9 9 6 12 150 1 1 1 1 1 1 1 1

Total 8 168 24 1344 5040 40320 40320 40320Time, s 1 1 1 30 215 97 40 15

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Largest Optimal CircuitsLargest Optimal Circuits

Note that purely quantum gatesNote that purely quantum gatescan enable smaller circuitscan enable smaller circuitsJohn A. Smolin, "John A. Smolin, "Five two-bit quantum gates Five two-bit quantum gates

are sufficient to implement the quantum Fredkin are sufficient to implement the quantum Fredkin gategate“, PRA 53(4), 1996, pp. 2855-2856“, PRA 53(4), 1996, pp. 2855-2856

Q. Circuit Synthesis via the Ring Normal FormQ. Circuit Synthesis via the Ring Normal Form(papers by Thomas Beth and Martin R(papers by Thomas Beth and Martin Rööttler)ttler)

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Why Circuit Libraries?Why Circuit Libraries?

Large speedupLarge speedup over straight DFID over straight DFIDCan be calculated from previous tableCan be calculated from previous tableCalculated values are very largeCalculated values are very large

In practice, the table In practice, the table cannot be generated cannot be generated in several hours in several hours without circuit librarieswithout circuit librariesWith libraries, the table takes With libraries, the table takes less than 10 minless than 10 min

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OutlineOutline

MotivationMotivationBackground Background Theoretical ResultsTheoretical ResultsSynthesis of Optimal CircuitsSynthesis of Optimal CircuitsAn Application to Quantum ComputingAn Application to Quantum Computing

Grover’s SearchGrover’s SearchPseudo-classical SynthesisPseudo-classical Synthesis

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Quantum CircuitsQuantum Circuits

Necessarily reversibleNecessarily reversibleBit-lines are now Bit-lines are now qubitsqubitsAll classical reversible gates still allowedAll classical reversible gates still allowed

Many other gates used as wellMany other gates used as wellCircuit equivalences for reversible gatesCircuit equivalences for reversible gates

are still valid !are still valid !

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Grover’s SearchGrover’s Search A quantum algorithm for associative searchA quantum algorithm for associative search

(input is not sorted)(input is not sorted) Search criterion: a classical one-output function Search criterion: a classical one-output function ff

Runs in time Runs in time O(√O(√NN)) classical algorithms require classical algorithms require ((N N )) time time

Requires a subroutine thatRequires a subroutine that changes the phasechanges the phase (sign) (sign) of all basis states of all basis states (bit-strings)(bit-strings)

that match the search criterion that match the search criterion ff

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Grover Oracle CircuitsGrover Oracle Circuits

To change the sign of a bit-stringTo change the sign of a bit-string Initialize a qubit to |0> - |1>Initialize a qubit to |0> - |1> Compute the classical one-output function Compute the classical one-output function ff XOR the qubit with XOR the qubit with ff Whenever Whenever f =1f =1, the sign (phase) will change, the sign (phase) will change

Thus, Thus, the design of Grover search circuitsthe design of Grover search circuitsfor a givenfor a given f f Is reduced to reversible synthesisIs reduced to reversible synthesis Can be Can be solved optimally by our methodssolved optimally by our methods

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Sample Grover CircuitSample Grover Circuit

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ROM-based CircuitsROM-based Circuits Desired circuits must alter phase of basis statesDesired circuits must alter phase of basis states

All bits except one All bits except one must be restored to input valuesmust be restored to input values Previous work studied ROM-based circuitsPrevious work studied ROM-based circuits

Constraint: ROM qubits can never changeConstraint: ROM qubits can never change B. Travaglione et al., 2001, B. Travaglione et al., 2001,

http://xxx.lanl.gov/abs/quant-ph/0109016http://xxx.lanl.gov/abs/quant-ph/0109016 Theorems + heuristic synthesis algorithmsTheorems + heuristic synthesis algorithms

Our work: synthesis of pseudo-classical circuits Our work: synthesis of pseudo-classical circuits 33 read-only “ROM” wires that can read-only “ROM” wires that can never changenever change 11 wire that can be changed during computation, wire that can be changed during computation,

but but must be restored by endmust be restored by end 11 wire on which function is computed wire on which function is computed

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Synthesis Algorithms ComparedSynthesis Algorithms Compared

Heuristic synthesis of ROM-based circuitsHeuristic synthesis of ROM-based circuitsProposed by Proposed by Travaglione et al, 2001Travaglione et al, 2001Based on XOR-sum decomposition (“Based on XOR-sum decomposition (“XORXOR”)”) Imposed a restriction: Imposed a restriction: at most one control bit at most one control bit

per gate can be on a ROM bitper gate can be on a ROM bit Optimal synthesis (as described earlier)Optimal synthesis (as described earlier)

with restriction from Travaglione (“with restriction from Travaglione (“OPT TOPT T”)”)without this restriction (“without this restriction (“OPTOPT”)”)

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Sizes of 3+2 ROM-circuits

Size 0 1 2 3 4 5 6 7 8 9 10 11 12

XOR 1 4 6 4 4 12 18 12 6 12 19 16 10

OPT T 1 4 6 4 4 12 21 24 29 33 44 46 22

OPT 1 7 21 35 36 28 28 36 35 21 7 1 0

Size 13 14 15 16 17 18 19 20 21 22 23 24 25 26

XOR 8 10 16 19 12 6 12 18 12 4 4 6 4 1

OPT T 5 1 0 0 0 0 0 0 0 0 0 0 0 0

OPT 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Discussion of Empirical ResultsDiscussion of Empirical Results

The XOR-SUM heuristic is sub-optimalThe XOR-SUM heuristic is sub-optimalAll methods able to synthesize all 256 fnsAll methods able to synthesize all 256 fns

““OPT TOPT T” can synthesize as many as “” can synthesize as many as “OPTOPT”:”: B. Travaglione et al., 2001B. Travaglione et al., 2001

““OPTOPT” results symmetrical about 5-6 gates” results symmetrical about 5-6 gatesFunction Function xx requires one fewer gate than requires one fewer gate than 256-x256-xExplanation yet to be foundExplanation yet to be found

““XORXOR” results symmetrical about 13 gates” results symmetrical about 13 gates

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ConclusionsConclusions

Classical reversible circuitsClassical reversible circuitsas special-case quantum circuitsas special-case quantum circuits

Existence theoremsExistence theoremsReversible De Morgan’s lawsReversible De Morgan’s laws

Future research on optimization heuristicsFuture research on optimization heuristicsAlgorithm for synthesis of optimal circuitsAlgorithm for synthesis of optimal circuits

Applicable to Grover’s search Applicable to Grover’s search See details in See details in quant-ph/0207011quant-ph/0207011

A more detailed version will posted by 09/22A more detailed version will posted by 09/22

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Quantum Circuit SynthesisQuantum Circuit Synthesisby Simulated Annealingby Simulated Annealing

Manoj Rajagopalan, Igor L. Markov,Manoj Rajagopalan, Igor L. Markov, and John P. Hayes and John P. Hayes



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The ProblemThe Problem

Synthesize a quantum circuitSynthesize a quantum circuitUsing gates from the given libraryUsing gates from the given libraryTo achieve a specified unitary matrixTo achieve a specified unitary matrix

((can also consider effects of measurementcan also consider effects of measurement))Very few qubits are consideredVery few qubits are considered

All matrices are still very smallAll matrices are still very smallYet, there can be many of gatesYet, there can be many of gates

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Synthesis TechniquesSynthesis Techniques

Exhaustive Search Exhaustive Search Matrix Factorization (QR, CS, ILU,KAK) Matrix Factorization (QR, CS, ILU,KAK)

[Cybenko2000][Cybenko2000] uses QR uses QRDynamic Programming + Branch & BoundDynamic Programming + Branch & Bound

[ShendePMH2002], quant-ph/0207001[ShendePMH2002], quant-ph/0207001Genetic AlgorithmsGenetic Algorithms

[WilliamsG1999, YabukiI2001][WilliamsG1999, YabukiI2001]Simulated Annealing: Simulated Annealing: this workthis work

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Simulated AnnealingSimulated Annealing Stochastic algorithmStochastic algorithm

form of local search for solving optimization problemsform of local search for solving optimization problems

AnnealingAnnealing: heating and gradual cooling to toughen : heating and gradual cooling to toughen (metal or glass) and reduce brittleness(metal or glass) and reduce brittleness

Simulated annealingSimulated annealing (combinatorial optimization)(combinatorial optimization)Objective function ~ energy of systemObjective function ~ energy of systemMinimized by simulating Brownian motion with Minimized by simulating Brownian motion with

decreasing temperaturedecreasing temperatureMoves randomly selected, good ones accepted,Moves randomly selected, good ones accepted,

and bad ones accepted in some casesand bad ones accepted in some casesProbability of accepting bad move = Probability of accepting bad move = e e (-(- costcost / / TT))

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Simulated Annealing for Q.S.Simulated Annealing for Q.S.

Represent circuit synthesis Represent circuit synthesis as an optimization problemas an optimization problemSolution spaceSolution space: :

Quantum circuits (circuit topology + gate types)Quantum circuits (circuit topology + gate types)ConstraintsConstraints: :

Output must match specification for given inputOutput must match specification for given inputGates from given libraryGates from given library

ObjectivesObjectives: : Minimize number of gatesMinimize number of gatesMinimize the error (in some norm)Minimize the error (in some norm)

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A Naive Annealer + ExtensionA Naive Annealer + Extension

Consider individual circuits, one at a timeConsider individual circuits, one at a timeEvaluate matrix product of all gatesEvaluate matrix product of all gates

Compute the errorCompute the errorBetter ideaBetter idea: incremental evaluation: incremental evaluation

Add/remove/change one gate at a timeAdd/remove/change one gate at a time Incrementally compute matrix productIncrementally compute matrix product

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Incremental PerturbationIncremental Perturbation

Perturb gates at Perturb gates at endsends of circuit of circuitEffect of adding and removing single gates Effect of adding and removing single gates

realized by realized by qubit-wisequbit-wise multiplicationmultiplicationAsymptotic improvement per moveAsymptotic improvement per move

Suppose we have Suppose we have NN gates gates Incremental evaluation: Incremental evaluation: O(1)O(1) time timeEvaluation from scratch: Evaluation from scratch: O(N)O(N) time time

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Simulated Annealing ProcedureSimulated Annealing Procedure

Initial solution: empty circuit (Id matrix)Initial solution: empty circuit (Id matrix)Choose initial temperature (…), final T = 0Choose initial temperature (…), final T = 0Adopt a temp. schedule (linear, geometric)Adopt a temp. schedule (linear, geometric)Single-qubit move and CNOT movesSingle-qubit move and CNOT moves

At either end of current circuit,At either end of current circuit,select (with equal probability) fromselect (with equal probability) fromNo change (No change (NOPNOP))Add a gate (Add a gate (ADDADD))Remove a gate (Remove a gate (REMREM))Replace a gate (Replace a gate (REPREP))

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Make a random moveMake a random move Evaluate errorEvaluate error of new circuit of new circuit

If error If error <10<10-6-6, , consider synthesis completeconsider synthesis complete Else evaluate costElse evaluate cost: weighted sum of error and #gates: weighted sum of error and #gates IfIf a move improves cost, then a move improves cost, then accept itaccept it ElseElse accept move with probabilityaccept move with probability exp exp (-(-costcost / / TT))

Must accept Must accept somesome bad moves to avoid local minima bad moves to avoid local minima T=0 means greedyT=0 means greedy Low-temperature annealing cannot climb hills wellLow-temperature annealing cannot climb hills well

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Reduce temp. according to scheduleReduce temp. according to scheduleRepeat move selection, acceptance…Repeat move selection, acceptance…Perform iterationsPerform iterations

until final temperature is reacheduntil final temperature is reached

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Implementation PlatformImplementation Platform

AMD Athlon 1.2 GHz processorAMD Athlon 1.2 GHz processorDebian LinuxDebian LinuxC++ (g++ v2.95.4 –O3)C++ (g++ v2.95.4 –O3)

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Quantum Gates Quantum Gates

2

12

1

21

21

H

01

10X

10

01Z

i0

01Z 2

1

ZXXZ

XHHZ

ZHHX

2

12

1

21

21

H

01

10X

10

01Z

i0

01Z 2

1

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Test 1: H-X-Z gate circuitsTest 1: H-X-Z gate circuits

Hadamard (H), Not (X) and Phase shift (Z)Hadamard (H), Not (X) and Phase shift (Z)Optimal one-qubit circuits typically require Optimal one-qubit circuits typically require

up to 3 gates per qubitup to 3 gates per qubitTargets for synthesis:Targets for synthesis:

randomly generated circuits with 5 qubitsrandomly generated circuits with 5 qubitsResults averagedResults averaged

over 100 independent startsover 100 independent starts

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H-X-Z circuit results (5 qubits)H-X-Z circuit results (5 qubits)

LibraryLibrary Min SizeMin Size

(# gates)(# gates)

Avg SizeAvg Size

(# gates)(# gates)

Avg TimeAvg Time

(s)(s)

Success Success raterate

H X ZH X Z 66 1717 0.600.60 100 %100 %

H X ZH X Z½½ 77 2727 5.535.53 82 %82 %

H ZH Z 88 2323 1.821.82 99 %99 %

H XH X 1010 5252 3.483.48 81 %81 %

H ZH Z½½ 1212 2929 4.234.23 81 %81 %

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H-X-Z circuit resultsH-X-Z circuit results

Reasonably small runtimesReasonably small runtimesNear-optimal (?) circuits foundNear-optimal (?) circuits found

We were not able to find better circuitsWe were not able to find better circuitsby paper & pencil calculationsby paper & pencil calculations

In principle, can change the gate libraryIn principle, can change the gate library

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Test 2: Teleportation circuitsTest 2: Teleportation circuits([WilliamsG1999] & [YabukiI2001]([WilliamsG1999] & [YabukiI2001]

R

L

S

T

S

Sender Receiver

Circuits with CNOT gates

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Quantum Gates Quantum Gates

2

12

1

21

21

R

10

0S

i

21

21

21

21

L

0100

1000

0010

0001

NOTC

R = Z H = H X

L = H Z = X H

R = L†

S = X Z½ X

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Synthesis of Sender-CircuitSynthesis of Sender-Circuit

GateGate

LibraryLibrary

Min SizeMin Size

(# gates)(# gates)

Avg SizeAvg Size

(# gates)(# gates)

Avg Avg Time (s)Time (s)

Success Success RateRate

L,CNOT,L,CNOT,RR

44 5353 11.2311.23 95 %95 %

CNOT,H,CNOT,H,XX

2020 125125 31.4331.43 51 %51 %

CNOT,H,CNOT,H,ZZ

88 162162 38.4638.46 45%45%

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Receiver Circuit SynthesisReceiver Circuit Synthesis

GateGate

LibraryLibrary

Min SizeMin Size

(# (# gates)gates)

Avg SizeAvg Size

(# gates)(# gates)

Avg Avg TimeTime

(s)(s)

Success Success RateRate

S,CNOT,TS,CNOT,T 44 55 0.050.05 100 %100 %(83% opt)(83% opt)

H,CNOT,ZH,CNOT,Z½½ 44 66 0.110.11 100 %100 %(68% opt)(68% opt)

H,CNOT,ZH,CNOT,Z½½

ZZ¼¼, X, X

33 55 0.220.22 100 %100 %(44% opt)(44% opt)

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Teleportation: Previous WorkTeleportation: Previous WorkWilliams and GrayWilliams and Gray (Genetic Algos)(Genetic Algos)

Both circuits with 4 gates, 100% success rateBoth circuits with 4 gates, 100% success rate Initial population size is 100 circuitsInitial population size is 100 circuitsRequires 4 generations - 2640 circuit Requires 4 generations - 2640 circuit

evaluations - on averageevaluations - on averageYabuki and IbaYabuki and Iba (Genetic Algos) (Genetic Algos)

Sender circuit - 4 gates, Receiver - 3 gatesSender circuit - 4 gates, Receiver - 3 gatesSimplify the problem by exploiting featuresSimplify the problem by exploiting featuresRequires 350 generations of 5000 candidates Requires 350 generations of 5000 candidates

on averageon average

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ConclusionsConclusions

Simulated annealingSimulated annealing Promising heuristic for synthesis of q. circuitsPromising heuristic for synthesis of q. circuitsBenefits from incremental evaluationBenefits from incremental evaluationReasonably fastReasonably fastCompetitive with Genetic Algorithms (better?) Competitive with Genetic Algorithms (better?)

FlexibilityFlexibilityGate libraries can be easily changedGate libraries can be easily changed

(e.g., over-specified)(e.g., over-specified)Various optim. objectives can be addressedVarious optim. objectives can be addressedDitto for constraintsDitto for constraints

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On-going WorkOn-going Work More focus on minimizing the number of gatesMore focus on minimizing the number of gates

So far, mostly tried to find a circuit quicklySo far, mostly tried to find a circuit quickly

Account for more physical phenomenaAccount for more physical phenomena Circuit equivalence up to global phaseCircuit equivalence up to global phase

Adaptive move-type selectionAdaptive move-type selection Based on how successful previous moves wereBased on how successful previous moves were

Temperature schedule, initial temperatureTemperature schedule, initial temperature More challenging synthesis problemsMore challenging synthesis problems

Add Toffoli gates (increased inter-qubit interaction)Add Toffoli gates (increased inter-qubit interaction) Continuous gate libraries (single-paramater gates)Continuous gate libraries (single-paramater gates)

DARPADARPA

ReferencesReferences1.1. G.Cybenko, “Reducing quantum computations to G.Cybenko, “Reducing quantum computations to

elementary unitary operations”, elementary unitary operations”, Comp. in Sci. and Comp. in Sci. and EnginEngin., pp.27-32, March/April 2001.., pp.27-32, March/April 2001.

2.2. V.V.Shende, A.K.Prasad, I.L.Markov, J.P.Hayes, V.V.Shende, A.K.Prasad, I.L.Markov, J.P.Hayes, “Reversible Logic Circuit Synthesis”, to appear in “Reversible Logic Circuit Synthesis”, to appear in Proc. Proc. ACM/IEEE Intl. Conf. Comp.-Aided DesignACM/IEEE Intl. Conf. Comp.-Aided Design, Nov. 2002, Nov. 2002

3.3. C.P.Williams, A.G.Gray “Automated design of quantum C.P.Williams, A.G.Gray “Automated design of quantum circuits”, In circuits”, In QCQC’98 LNCS 1509QCQC’98 LNCS 1509, pp. 113-125, , pp. 113-125, Springer-Verlag, 1999.Springer-Verlag, 1999.

4.4. T.Yabuki, H.Iba, “Genetic Algorithms for quantum circuit T.Yabuki, H.Iba, “Genetic Algorithms for quantum circuit design –Evolving a simpler teleportation circuit-”, In design –Evolving a simpler teleportation circuit-”, In Late Late Breaking Papers at the 2000 Genetic and Evolutionary Breaking Papers at the 2000 Genetic and Evolutionary Computation Conf.Computation Conf., Las Vegas, NV, pp. 425-430, 2000., Las Vegas, NV, pp. 425-430, 2000.

DARPADARPA

High-Performance Simulation of High-Performance Simulation of Quantum Computation using QuIDDsQuantum Computation using QuIDDs

George F. Viamontes, Manoj Rajagopalan, George F. Viamontes, Manoj Rajagopalan, Igor L. Markov, and John P. HayesIgor L. Markov, and John P. Hayes



DARPADARPA

ProblemProblem

Simulation of quantum computing on a Simulation of quantum computing on a classical computerclassical computerRequires Requires exponentiallyexponentially growing time and growing time and

memory resources using standard linear memory resources using standard linear algebraalgebra

GoalGoal: Improve classical simulation: Improve classical simulationSolutionSolution: Compress : Compress redundancyredundancy

in relevant matrices and vectorsin relevant matrices and vectors

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Redundancy in Quantum ComputingRedundancy in Quantum Computing

Matrix representation of quantum gates Matrix representation of quantum gates contain block patternscontain block patterns

The Tensor (Kronecker) Product The Tensor (Kronecker) Product Create state vectors and operatorsCreate state vectors and operators

involving multiple qubitsinvolving multiple qubitsPropagates block patternsPropagates block patterns

in vectors and matricesin vectors and matrices

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Example of PropagatedExample of Propagated Block Patterns Block Patterns

Only TWO distinct blocks!

2/12/12/12/1

2/12/12/12/1

2/12/12/12/1

2/12/12/12/1

2/12/1

2/12/1

2/12/1

2/12/1

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We could try Lempel-Ziv compression,We could try Lempel-Ziv compression,but manipulating compressed data is difficultbut manipulating compressed data is difficult

Try using compression based on structureTry using compression based on structurethat we understand, e.g., that we understand, e.g., Complex getMatrixElement(int row, int col, int qubits)Complex getMatrixElement(int row, int col, int qubits)

{{ return pow ( sqrt(2) , qubits ) return pow ( sqrt(2) , qubits ) *( innProdMod2 ( row, col ) ? 1 : -1 ); *( innProdMod2 ( row, col ) ? 1 : -1 );}}

Still difficult do manipulateStill difficult do manipulate Consider a Consider a decision treedecision tree based on row & col based on row & col

No exponential compression (?)No exponential compression (?)

Compressed RepresentationsCompressed RepresentationsThat Capture StructureThat Capture Structure

DARPADARPA

*BDDs: Data Structures*BDDs: Data Structures that Exploit Redundancy that Exploit Redundancy

Binary Decision Diagrams (BDDs)Binary Decision Diagrams (BDDs)exploit repeated sub-structureexploit repeated sub-structure Different variantsDifferent variants: ROBDDs, ZDDs, ADDs, FDDs, EVDDs,…: ROBDDs, ZDDs, ADDs, FDDs, EVDDs,… Common ideaCommon idea: bottom-up merging of nodes in decision trees: bottom-up merging of nodes in decision trees

Example: Example: f = a AND bf = a AND b

a

f

b

1 0

Assign value of 1 to variable x

Assign value of 0 to variable x

DARPADARPA

*BDDs: Data Structures*BDDs: Data Structures that Exploit Redundancy that Exploit Redundancy

BDDs have been usedBDDs have been usedto simulate classical logic circuitsto simulate classical logic circuits[Lee59, Bryant86][Lee59, Bryant86] A circuit can be “simulated” on all input values at onceA circuit can be “simulated” on all input values at once

BDDs BDDs made useful by fast operationsmade useful by fast operations Bryant’s main contribution: Bryant’s main contribution: ROBDDsROBDDs A fixed ordering of nodes + reduction rulesA fixed ordering of nodes + reduction rules

Potentially less compression, but faster algorithmsPotentially less compression, but faster algorithms Used in most *DD data structures, including QuIDDsUsed in most *DD data structures, including QuIDDs

Compare to “read-once branching programs” Compare to “read-once branching programs”

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Basic BDD Operations [Bryant1986]Basic BDD Operations [Bryant1986]

( ( |A||A| = number of nodes in BDD = number of nodes in BDD AA ) ) Most BDD operations are based on recursive Most BDD operations are based on recursive

procedures: procedures: ITEITE, , Apply, etcApply, etc Typically take two or three BDDs as argumentsTypically take two or three BDDs as arguments Apply(A,B)Apply(A,B) has space and time complexity has space and time complexity ApplyApply is an algorithmic form of Boole’s Expansion is an algorithmic form of Boole’s Expansion

Different types of *DDs optimize operationsDifferent types of *DDs optimize operationsfor specific contexts and reduction rulesfor specific contexts and reduction rules, e.g.,, e.g., EVDDs (edge-valued), ZDDs (zero-suppressed), etcEVDDs (edge-valued), ZDDs (zero-suppressed), etc

|)||(| BAO

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Linear Algebra via BDDsLinear Algebra via BDDs

Variants of BDDs have been used Variants of BDDs have been used to represent matrices and vectorsto represent matrices and vectors Algebraic Decision Diagrams (ADDs) treat Algebraic Decision Diagrams (ADDs) treat variable variable

nodes as matrix indicesnodes as matrix indices [Bahar93] [Bahar93] ADDs compress repeated block patterns in ADDs compress repeated block patterns in

matrices and vectorsmatrices and vectors Linear Algebraic operations can be performedLinear Algebraic operations can be performed

as ADD traversals (i.e., w/o decompression)as ADD traversals (i.e., w/o decompression) From general to specific:From general to specific:

MTBDDs MTBDDs ADDs ADDs QuIDDs QuIDDs

DARPADARPA

Quantum Information Quantum Information Decision DiagramsDecision Diagrams

Quantum Information Decision Diagrams Quantum Information Decision Diagrams ((QuIDDsQuIDDs)) An application of ADDsAn application of ADDs

to the quantum computing domainto the quantum computing domain

Similar structure to ADDsSimilar structure to ADDs Three types of nodesThree types of nodes

Row, Column, TerminalRow, Column, Terminal

Use modified ADD operationsUse modified ADD operations

DARPADARPA

QuIDD StructureQuIDD Structure

BDD BDD variable orderingvariable orderingDefines the order in which different node Defines the order in which different node

types appeartypes appearQuIDD variable ordering interleaves row QuIDD variable ordering interleaves row

and column variablesand column variablesTerminal nodes are always lastTerminal nodes are always last

TCRCRCR nn 1100

DARPADARPA

Quantum Circuit Simulation Issues Quantum Circuit Simulation Issues Specific to QuIDDsSpecific to QuIDDs

Use state-vector representationUse state-vector representation In principle, QuIDDs can also modelIn principle, QuIDDs can also model

the density-matrix representationthe density-matrix representation

Avoid matrix-matrix mult. (for efficiency)Avoid matrix-matrix mult. (for efficiency)Tensor products and matrix-vector Tensor products and matrix-vector

multiplications are performedmultiplications are performedAre very efficient Are very efficient

DARPADARPA

QuIDD VectorsQuIDD Vectors

Use column and terminal variablesUse column and terminal variablesRepresent qubit state vectorsRepresent qubit state vectorsSome examplesSome examples::

f

0C

1C

2/1

1 0

1

0

0

0

f

2/1

2/1

2/1

2/100

01

10

11

00

01

10

11

TT

DARPADARPA

QuIDD MatricesQuIDD Matrices

Use row, column, and terminal variablesUse row, column, and terminal variablesRepresent gates / unitary matricesRepresent gates / unitary matrices

There is There is no requirement for unitary matricesno requirement for unitary matrices,,Constant factors can be stored separatelyConstant factors can be stored separately

DARPADARPA

Example: 2-Qubit Hadamard QuIDDExample: 2-Qubit Hadamard QuIDDf

0R

0C

2/1 2/1

1R

1C

1R

1C

2/12/12/12/1

2/12/12/12/1

2/12/12/12/1

2/12/12/12/1 00

01

10

11

1001 1100

DARPADARPA

Based on the Based on the ApplyApply algorithm [Bryant1984,ClarkeEtAl1996] algorithm [Bryant1984,ClarkeEtAl1996] Construct new QuIDDs by traversingConstruct new QuIDDs by traversing

two QuIDD operands two QuIDD operands Perform “op” at terminals (op can be *, +, etc.)Perform “op” at terminals (op can be *, +, etc.) The variable ordering directs the traversalThe variable ordering directs the traversal General Form: General Form: f f opop g g where where f f and and gg are QuIDDs, and are QuIDDs, and xx

and and yy are variables in are variables in ff and and gg, respectively, respectively

QuIDD OperationsQuIDD Operations

ix

ii yx gopfii yx

gopf

iy

iyi gopxiyi gopx

ix

ix yopfi ix

yopfi

ii yx ii yx ii yx

DARPADARPA

To compute To compute AA B BEvery element of a matrix Every element of a matrix AA

is multiplied by the is multiplied by the entireentire matrix matrix BBQuIDD implementation: uses QuIDD implementation: uses ApplyApply

Operands are Operands are A A andand B B Variables of operandVariables of operand B B are shifted are shifted ““op” is defined to be multiplicationop” is defined to be multiplication

Tensor ProductTensor Product

DARPADARPA

A modified form of the A modified form of the ApplyApply function function Dot-product can be done on QuIDDs Dot-product can be done on QuIDDs without without

decompressiondecompression ““Skipped” nodes are countedSkipped” nodes are countedA factor of 2A factor of 2#skipped#skipped is multiplied by dot-products is multiplied by dot-products

QuIDD ImplementationQuIDD Implementation Modified ADD matrix multiply algorithm [Bahar93]Modified ADD matrix multiply algorithm [Bahar93]Support complex number terminalsSupport complex number terminalsAccount for row/column variable orderingAccount for row/column variable ordering

Matrix MultiplicationMatrix Multiplication

DARPADARPA

Other OperationsOther Operations

Matrix additionMatrix additionCall to Call to Apply Apply with “op” set to additionwith “op” set to addition

Scalar operationsScalar operationsA special one-operand version of A special one-operand version of ApplyApply

Qubit measurementQubit measurementA combination of matrix multiplications,A combination of matrix multiplications,

tensor products, and scalar operationstensor products, and scalar operations

DARPADARPA

Simulation of Grover’s AlgorithmSimulation of Grover’s Algorithm

QuIDDProQuIDDPro was tested by running was tested by running instances of Grover’s Algorithminstances of Grover’s Algorithm

Results indicate Results indicate linearlinear memory usage in memory usage in many casesmany casesAny circuit with an oracle whose Any circuit with an oracle whose QuIDD formQuIDD form

is polynomial in # of qubitsis polynomial in # of qubits

DARPADARPA

Sample Circuit RepresentationSample Circuit Representation

H

H

H

Oracle

H

H

Conditional Phase Shift

H

H

H

|0>

|0>

|1>

.

.

.

.

.

.

.

.

.

DARPADARPA

# iterations computed [BoyerEtAl96]# iterations computed [BoyerEtAl96]# iterations =# iterations = WhereWhere MM=# of solutions=# of solutions, , 22qq=# of elements in data set=# of elements in data setExponential runtime on a quantum computerExponential runtime on a quantum computer

When When M M is small, is small, the number of iterationsthe number of iterationsis exponentialis exponential in the number of qubits in the number of qubits

Simulation of Grover’s AlgorithmSimulation of Grover’s Algorithm

4/qM 2/

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Projected Grover IterationsProjected Grover Iterations

SANITY CHECK:SANITY CHECK: Make sure that the number of Make sure that the number of iterations predicted by Boyer et al. results in the iterations predicted by Boyer et al. results in the highest probability of measuring the item(s) to be highest probability of measuring the item(s) to be searchedsearched

DARPADARPA

Experiment versus PredictionsExperiment versus Predictions

DARPADARPA

Simulation Results forSimulation Results forGrover’s AlgorithmGrover’s Algorithm

Linear growth of QuIDDs in Grover’s algoLinear growth of QuIDDs in Grover’s algo Number of nodes in QuIDDs shownNumber of nodes in QuIDDs shown

DARPADARPA

Grover’s Algorithm: Grover’s Algorithm: Results using Results using Oracle 1Oracle 1

Oracle 1 “searches”Oracle 1 “searches”for one element in the data setfor one element in the data set

Oracle polynomial in sizeOracle polynomial in sizeLinearLinear memory asymptotics memory asymptoticsRun-times are extremely low vs MatlabRun-times are extremely low vs Matlab

DARPADARPA

Grover’s Algorithm: Grover’s Algorithm: Results using Results using Oracle 1Oracle 1 Linear growth

with QuIDDPro

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Grover’s Algorithm: Grover’s Algorithm: Results using Results using Mod-1024 OracleMod-1024 Oracle

Finds elements in the data set whose 10 Finds elements in the data set whose 10 least significant bits are 1least significant bits are 1

Useful in demonstrating asymptoticsUseful in demonstrating asymptoticsMemory Memory andand runtime are governed runtime are governed

purely by the size of the systempurely by the size of the system

DARPADARPA

Grover’s Algorithm: Grover’s Algorithm: Results using Mod-1024 OracleResults using Mod-1024 Oracle

For data up to For data up to n=25n=25 qubits, qubits,linear least-squares regressionlinear least-squares regressionshows that memory (MB) growsshows that memory (MB) grows as as 7.5922 + 0.0410n7.5922 + 0.0410n

Linear growth with QuIDDPro

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Conclusions and Future WorkConclusions and Future Work Asymptotic performance whenAsymptotic performance when

QuIDD form of oracle is poly-sizedQuIDD form of oracle is poly-sized QuIDDProQuIDDPro: ~: ~1.661.66nn; ; Ideal Q. ComputerIdeal Q. Computer: ~: ~1.411.41nn

Far more efficient than other classical simulation Far more efficient than other classical simulation techniquestechniques MATLABMATLAB, , Blitz++Blitz++: : ((22nn))

We plan to simulate other algorithmsWe plan to simulate other algorithmsusing QuiDD Pro (using QuiDD Pro (+ inject errors+ inject errors)) A simulation of Shor’s algorithm operationalA simulation of Shor’s algorithm operational

Details in Details in quant-ph/0208003quant-ph/0208003

DARPADARPA

ReferencesReferences

[1] C.Y. Lee, “Representation of Switching Circuits by Binary Decision [1] C.Y. Lee, “Representation of Switching Circuits by Binary Decision Diagrams”, Diagrams”, Bell System Technical Jour.Bell System Technical Jour., 38:985-999, 1959., 38:985-999, 1959.

[2] R. Bryant, “Graph-Based Algorithms for Boolean Function [2] R. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation”, Manipulation”, IEEE Trans. On ComputersIEEE Trans. On Computers, vol. C-35, pp. 677-691, , vol. C-35, pp. 677-691, Aug 1986.Aug 1986.

[3] R. I. Bahar et al., Algebraic Decision Diagrams and their [3] R. I. Bahar et al., Algebraic Decision Diagrams and their Applications”, Applications”, In Proc. IEEE/ACM ICCADIn Proc. IEEE/ACM ICCAD, pp. 188-191, 1993., pp. 188-191, 1993.

[4] E. Clarke et al., “Multi-Terminal Binary Decision Diagrams and [4] E. Clarke et al., “Multi-Terminal Binary Decision Diagrams and Hybrid Decision Diagrams”, In T. Sasao and M. Fujita, eds, Hybrid Decision Diagrams”, In T. Sasao and M. Fujita, eds, Representations of Discrete FunctionsRepresentations of Discrete Functions, pp. 93-108, Kluwer, 1996., pp. 93-108, Kluwer, 1996.

[5] M. Boyer et al., “Tight Bounds on Quantum Searching”, [5] M. Boyer et al., “Tight Bounds on Quantum Searching”, Fourth Fourth Workshop on Physics and ComputationWorkshop on Physics and Computation, Boston, Nov 1996., Boston, Nov 1996.

Documents

DARPA Simulation and Synthesis of Quantum Circuits Igor L. Markov and John P. Hayes Advanced Computer Architecture Laboratory University of Michigan, EECS