Da Tklgs Vb2

7/31/2019 Da Tklgs Vb2

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A BCin

Cout

Sum

A, B, Sum: 32 bt; Cin, Cout: 1 bt

Bi 2: Thit k cc khi nh:

2.1 Thit k m phng khi ROM 64x8 bit lu tr chu k u ca

hm 255*Sin(X).2.2 Thit k m phng khi ROM 64x8 bit lu tr chu k u cahm 255*COS(X).

2.3. Thit k khi ROM lu tr hnh dng ca cc k t t A->Z vikch thc 8x8

V d ch A

0 0 0 0 1 1 0 0 0 0

0 0 0 1 1 1 1 0 0 0

0 0 0 1 1 1 1 0 0 0

0 0 1 1 0 0 1 1 0 0

0 0 1 1 0 0 1 1 0 0

0 0 1 1 1 1 1 1 0 0

0 1 1 1 1 1 1 1 1 0


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0 1 1 0 0 0 0 1 1 0

1 1 0 0 0 0 0 0 1 1

1 1 0 0 0 0 0 0 1 1

2.4. Thit k v m phng khi nh RAM 1 cng c ghi ng bkch thc 64x8.

2.5. Thit k v m phng khi nh RAM 2 cng c ghi ng bkch thc 64x8.

2.6. Thit k khi Ram 1 cng c ghi ng b. 16x9 trong mi mthng cha 8 bit thp l 1 byte d liu cn bt cao nht l bit parity ca

d liu tng ng trn hng. Bit parity bng 1 nu s lng bit 1 trongs 8-bit d liu l s l.2.7. Thit k khi thanh ghi a nng General Purpose Register trong

vi x l, kch thc 16x16bit h tr hai cng c ng b v 1cng ghi ng b.

2.8. Thit k v m phng khi nh FIFO kch thc 16x8.

2.9. Thit k v m phng khi nh LIFO 16x8.

Bi 3: Thit k khi tng hp dao ng NCO.

S khi thc hin n chia thnh cc phn chnh c th nh sau:


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ACC_

REG

27 MHz

DATA_

REG

m

Data

DAC

NCO

n ln c chia thnh 2 n nh nh hnh trn theo ng nt t,b khi DAC.

3.1 Thit k khi cng tch ly 8 bit.

3.2 Thit k khi SINROM 64x8 bit cha thng tin chu k SIN, h trtham chiu ton b chu k SIN

Bi 4: Thit k v kim tra thanh ghi dch a nng h tr thao tc ghi d liusong song iu khin bi tn hiu LOAD v cc lnh dch logic v arithmetictri, phi, dch vng khng s dng ton t dch, gi tr dch l mt s 5 bit,d liu dch l chui 32 bit. Tn hiu iu khin gm LEFT quy nh dch tri

hay phi, LOGIC quy nh dch logic hay s hc, ROLL quy nh dch vnghay dch tnh tin.

n ln c chia thnh 3 n nh nh sau:

4.1 : Xy dng khi dch logic 32 bt khng s dng ton t dch, gi trSHIFT_VALUE dch l 5 bt, tn hiu LEFT quy nh hng dch.

4.2 : Xy dng khi dch s hc 32 bt khng s dng ton t dch, gi trSHIFT_VALUE dch l 5 bt, tn hiu LEFT quy nh hng dch.


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4.3 : Xy dng khi dch vng 32 bt khng s dng ton t dch, gi trSHIFT_VALUE dch l 5 bt, tn hiu LEFT quy nh hng dch.

Bi 5: Thit k b cng s thc 32 bit theo chun IEEE 754, h tr mt kiulm trn ti s gn nht chn.



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Compare _exponent

MUX

Correct

_exponent

shifter

mbeaeasbsa ma

REG2

REG1

shift _value

mb3ma 3

A B

Operands unpack

PHASE 1

PHASE 2

Sel

Significand _adder

Nomalize

Nomalize

Rounding and selectivecomponent

Adjust exponent

Adjust exponent

Sign logic

REG_OUT

PHASE 4

result pack

REG 3

PHASE 3

n ln c chia thnh 4 n nh nh hnh trn theo ng nt t.

5.1 Thit k khi so snh s m v a ra kt qu l tham s cho khidch phn nh tr.


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5.2. Khi iu chnh s m v khi dch phn nh tr

5.3. Khi cng phn nh tr(sinificand adder, chun ha(Normalize), viu chnh s m ln mt (exponent adjustment).

5.4. Khi lm trn (Rounding) , chun ha ln 2 (Normalize), v iu

chnh s m ln hai.

Bi 6. Thit k b nhn s thc 32 bit theo chun IEEE 754, h tr mt kiulm trn ti s gn nht chn.


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Exponent_adder

Significand Multiplier

mbeaea

sbsa ma

REG1

A B

Operands unpack

PHASE 1

Nomalize

Nomalize

Rounding

Adjust exponent

Adjust exponent

REG_OUT

PHASE 4

result pack

n ln c chia thnh 2 n nh nh hnh trn theo ng nt t.

6.1 Thit k khi cng s m

6.2. Thit k khi nhn phn nh tr

6.3. Khi chun ha ln 1(Normalize), v iu chnh s m ln 1(exponent adjustment).


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Exponent_adder

Significand Division

mbeaea

sbsa ma

REG1

A B

Operands unpack

PHASE 1

Nomalize

Nomalize

Rounding

Adjust exponent

Adjust exponent

REG_OUT

PHASE 2

result pack

7.1 Thit k khi tnh ton s m

7.2. Thit k khi chia phn nh tr

7.3. Khi chun ha ln 1(Normalize), v iu chnh s m ln 1(exponent adjustment).


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7.4. Khi lm trn (Rounding) , chun ha ln 2 (Normalize), v iuchnh s m ln hai.

Bi 8: Thit k v kim tra khi nhn s nguyn khng du KxK = 2K bit

dng thut ton cng dch tri.


MUX Kbit

2k bit

SHIFT_REG

REG 2K-bit2K bitMultiplicand

0

product

SHIFT LEFT

Multiplier

2K bit0000000000 K-bit

n ln s c chia thnh cc n nh nh sau:

8.1 Khi nhn gi tr u vo, dch s b nhn (SHIFT_REG), khi chn(MUX K-bit).

8.2 Khi cng 2K-bit dng cu trc generate.

8.3 Thanh ghi tch ly (REG 2K-bit) v khi dch tri 2K bit(SHIFT_LEFT).


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MUX3-1 Kbit

k+1-bitSHIF T_REG

Multiplicand

0

product

RADIX 2

BOOTH

ENCODING

Multiplier & 0

-multiplicand

K bit K-1 bitSign

K-1 bit 1bitK bit

n ln c chia thnh cc phn nh nh sau:

10.1 Khi nhn gi tr u vo, dch s b nhn (SHIFT_REG), khi mha BOOTH2 .

10.2 Khi sinh ra cc gi tr v khi chn gi tr MUX3-1.

10.3 Khi cng K+1-bit dng thut ton cng ni tip cc full_adder.

10.4Thanh ghi tch ly (REG 2K-bit) v cc phn ghp tn hiu cn li.

Bi 11: Thit k v kim tra khi nhn s nguyn c du 2Kx2K = 4K-bitdng thut ton m ha Booth c s 4.



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MUX5-1 Kbit

k+1-bitSHIF T_REG

Multiplicand

0

product

RADIX 4

BOOTH

ENCODING

Multiplier &0

-mult iplicand 2*mult iplicand -2*mult iplicand

K+1 bit K-2 bitSignSign

K-2 bit 2bitK+1 bit

n ln c chia thnh cc n nh nh sau:

11.1 Khi nhn gi tr u vo, dch s b nhn (SHIFT_REG), khi mha BOOTH4 .

11.2 Khi sinh ra cc gi tr v khi chn gi tr MUX5-1.

11.3 Khi cng K+1-bit dng thut ton cng ni tip cc full_adder.

11.4Thanh ghi tch ly (REG 2K-bit) v cc phn ghp tn hiu cn li.

Bi 12: Thit k khi thc hin giao thc PS/2


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ln 1 n v bng tn hiu Pcinc, t li gi tr b m bng gi tr PC_in vtn hiu iu khin PC_set.Bi 14: Thit k khi thc hin thut ton MontGomery tnh module ca tchhai s A.B cho 1 s nguyn t N theo s thit k sau, rng bit K= 128,

A

MUX Kbit

k bit

B

k bit

MUX Kbit

N

S

MONTGOMERY MULTIPLICATIONS = A.B mod N

A

B

S

14.1. Thanh ghi dch B, thanh ghi A v khi chn MuxK-bit.

14.2. Thanh ghi S, N, Khi cng K bit.

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Da Tklgs Vb2