CY9266 HOTLink Evaluation Board User’s Guidedlm.cypress.com.edgesuite.net/akdlm/downloadmanager/documents/CY9266-c... · CY9266 HOTLink Evaluation Board User’s Guide 3 JP3—60-Position

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600March 11, 1999

CY9266 HOTLink™ Evaluation Board User’s Guide

OverviewThis document describes the construction, interfaces, andoperation of the CY9266–F (optical fiber), CY9266–P (plasticoptical fiber), CY9266–T (shielded twisted pair/twinax), andCY9266–C (coaxial cable) HOTLink™ Evaluation Boards.These boards implement a complete bidirectionalparallel-to-serial and serial-to-parallel communications link,capable of operation at serial rates of 150 to 400 Mbits/sec-ond (15 to 40 Mbytes/second). The supported rate of commu-nication may be limited by the specific type and speed-gradeof optical module or copper cable type used.

The CY9266 Evaluation Boards are optically, electrically, andmechanically compatible with the ANSI T11 Fibre ChannelInterface, as documented in the ANSI standard ANSX3.230–1994. It provides three different methods of accessfor the TTL parallel interface and supervisor functions, fortesting or exercising the serial data link.

Block Diagram

The block diagram in Figure 1 illustrates the major functionalblocks contained in the CY9266. These include:

• 10-bit TTL parallel transmit data input

• 10-bit TTL parallel receive data output

• Selectable Encoded or Bypass operation modes

• On-board socketed oscillator

• Selectable internal/external clocking

• Selectable signal-detect polarity

• Selectable local loopback

• Power supply voltage monitor

• Built-in self-test (BIST) pattern generation and checking hardware with error/status display

Board Connectors

This board offers three primary methods of TTL-level access:

• JP2—A 58-position (2 x 29) set of holes, capable of ac-cepting a 0.025″ sq. pin-header on the top or bottom of the board

• JP3—A 60-position (2 x 30) 0.1″ spaced board-edge finger stock

• JP4—A 48-position (4 x 12 matrix) 0.025″ sq. pin-header mounted on the bottom of the board

Connectors JP2 and JP3 provide access to all data input andoutput buses as well as all BIST, control, and clocking signalsfor the HOTLink Transmitter and Receiver. These connectorsmay be used individually or together since all signals presenton JP2 are also present on JP3. Power for the board is alsobrought in through these same connectors.

Connector JP4 is positioned and pinned to match up with theconnector and signals present on other industry-standard Fi-bre Channel modules. Unlike these other modules (whichmay contain two full-duplex channels), this evaluation boardonly provides a single full-duplex channel. While sufficientroom exists to build a board with two channels, other function-ality was added (on-board oscillator, BIST PLD and display,etc.) in this space to allow better testing and demonstration ofthe enhanced capabilities present in the Cypress HOTLinkparts.

Figure 1. HOTLink Evaluation Board Block Diagram

OLCHeader

JP4

BoardEdgeJP3

BoardHeader

JP2Optical or Copper

XMTR

BISTDisplay

BISTPLD

Latc

h

CY7B923XMTR

CY7B933RCVR

Optical or CopperRCVR

CY9266 HOTLink Evaluation Board User’s Guide

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An additional jumper block (JP1) is used to configure three ofthe operating characteristics of the board: clock sourcing, se-rial output enable (FOTO), and local loopback control.

Optical Modules

The CY9266–F Evaluation Board is designed to operate withindustry-standard footprint optical modules. The evaluationboard contains low-profile socket pins so the user may selectand test optical modules from different vendors. This boardaccepts both the four-row DIP and the single-row 1X9 typesof modules.

These modules are available from multiple vendors with ei-ther ST- or SC-type optical fiber connectors. Because thesemodules are all LED-based, they are not required to meetmany of the safety standards (ANSI Z136.1 and Z136.2,F.D.A. regulation 21 CFR subchapter J, and IEC 825) neces-sary for LASER-based modules. These modules should beused with 62.5/125-mm multimode graded-index fiber.

For longer distance communications, LASER-based modulesare also available that are compatible with the CY9266–Fcards. However, when used with LASER transmitters, it is theresponsibility of the user to receive what ever safety certifica-tions are necessary.

The CY9266–P Evaluation Board is electrically identical tothe CY9266–F, except that it is shipped with an optical moduleconfigured for low-cost plastic optical fiber, and set for a lowerdata rate (155 MBaud).

Coaxial Cables

The CY9266–C Evaluation Board is configured to support75Ω coaxial cables that attach through BNC/TNC connectors.Other cable impedances may be used with the board bychanging the value of the termination and driver bias resistorson the board.

Shielded-Pair Cables

The CY9266–T Evaluation Board is configured to support150Ω shielded twisted-pair or twinaxial cable that attachesthrough a 9-pin D-sub connector. Other cable impedancesmay be used with the board by changing the value of thetermination and driver bias resistors on the board.

BIST Support

The CY9266 contains an on-board control PLD and atwo-digit error-count display that are used in conjunction withthe BIST (Built-In Self-Test) capability of the Cypress Semi-conductor HOTLink Transmitter and Receiver. This capabilityallows the parts, and any serial link, to be exercised and mon-itored at their full data rate without the use of expensive ex-ternal test equipment.

The BIST PLD (CY7C344) contains a simple state machinethat monitors the HOTLink Receiver BIST state, and an er-ror-counter that drives an external display. The complete con-tents of this PLD are documented in Appendix C.

This BIST PLD also drives the four decimal point LEDs on thedisplays. These indicators are used to present additional sta-tus information about the state of the board, the BIST statemachine, and the serial link.

Design CriteriaThe CY9266 Evaluation Board was designed as a low-costdemonstration vehicle for the Cypress Semiconductor

HOTLink family of data communications parts. The goals ofthis board are to:

• Present an interface board that is fully compliant with the mechanical, electrical, optical, coding, and protocol spec-ifications in levels 0 and 1 of the ANSI X3.230 Fibre Chan-nel standard

• Allow full data rate testing of the serial link without expen-sive test equipment

• Allow the user to exercise all modes of operation of the receiver and transmitter

• Offer various parallel attachment methods for simplified system interfacing

• Offer various media types for evaluation

• Allow simple interfacing to existing OLC-compatible test platforms

Because of the flexibility inherent in the HOTLink parts, thesegoals were easily achieved.

Three electrical connection methods are provided: a 60-pinboard-edge connector, a 58-pin (2 x 29) 0.025″ squarepin-header, and a 48-pin (4 x 12) 0.025″ square pin-header.These different connectors allow the user to select the con-nector form that best suits their desired mode of attachment.

The HOTLink Transmitter and Receiver contain a BIST capa-bility. This capability was designed into the HOTLink parts toallow high-speed serial testing without expensive test equip-ment. All hardware necessary to exercise and monitor theBIST function is present on the CY9266 board. This hardwareallows a bit-error-rate (BER) test to be performed without ad-ditional equipment.

The BIST capability of the HOTLink Transmitter and Receiverallows offline testing of the transmitter, receiver, and seriallink, by performing a bit-by-bit comparison of the data while a511-character pseudo-random data stream is repeatedlysent, received, and checked.

Through use of either JP2 or JP3, users may exercise allmodes of operation of the parts. JP4 is configured as a func-tional system interface, and thus does not include all themode, clock, and special control signals present on JP2 andJP3, all of which may be selected or controlled in JP1 or S1.

Connector Pin NumberingJP2—58-Position Pin-Header

The 58-position pin-header (JP2) holes are located next tothe board-edge connector. Pin 1 of this connector area isidentified on the board by a square solder pad. The remainingpin locations use a round solder pad.

The connector hole pattern is made to accept fifty-eight0.025″ square pins soldered into the board. The numberingfor this connector is shown in Figure 2.

Note: The numbering of this connector is specified to matchup with standard 0.050″ centerline flat cable connectors. Be-cause of the location of pin 1 of this hole pattern, the matingpins for this connector should normally be on the bottom ofthe board. If a connector is instead attached to the top side ofthe board, the even- and odd-numbered pins of the connectorare effectively swapped. This means that conductor 1 of acable attached to the top side of the board is in reality con-nected to the signal listed for pin 2 in Table 1.


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JP3—60-Position Board-Edge

The 60-position board-edge connector (JP3) is a section ofgold plated 0.062″ board finger-stock that connects to thesame signals as JP2. Contact centerline for this connector is0.1″, with even- and odd-numbered signals on opposing sidesof the board.

To prevent the evaluation board from being plugged into amating connector backwards (and possibly damaging it), a0.040″ x 0.450″ keying slot is present between contacts 3/4and 5/6. The pin numbering for this connector is shown inFigure 3.

Note: The numbering of this connector is specified to matchup with standard 0.050″ centerline flat-cable connectors. Be-cause of the location of pin 1 of this board-edge connector,the mating connector would normally be a mass-terminateboard-edge to flat-cable type connector. If a standardboard-edge connector is used instead, the even and oddnumbered pins of the connector are effectively swapped. Thismeans that pin 1 of a standard board-edge connector is inreality connected to the signal listed for pin 2 in Table 1.

JP4—OLC-Compatibility Connector

The JP4 (OLC-compatibility) connector is located on the bot-tom (passive-component) side of the board. Pin 1 of this con-nector is identified on the board by a square solder pad. Theremaining pins use a round solder pad.

For the CY9266 Evaluation Board, pins of sufficient length arepresent so that analysis equipment may be attached to thesesignal pins on the top (active-component) side of the board

Figure 2. JP2 Pin Numbering, Top Side of Board View

2-CD_POL4-DIP_RCV A/B6-SWRCVBISTEN8-XMIT_ENA10-XMIT_MODE

14-XMIT_BISTEN12-XMIT_ENN

16-GND18-GND20-B YTE_SYNC22-VCC24-EXTREFCLK26-GND28-VCC30-GND32-GND34-VCC36-GND38-RESET40-GND42-VCC44-GND46-RD Y48-VCC50-GND52-GND54-RP56-XMITCL OCK58-L OOP_BACKLINK_CONTROL-57

GND-55XMIT_1-53XMIT_2-51XMIT_5-49XMIT_0-47XMIT_4-45XMIT_3-43XMIT_6-41XMIT_7-39

ENBYTESYNC-37XMIT_8-35

RCV_CLK0-33RCV_CLK1-31

XMIT_9-29REC_1-27REC_0-25REC_3-23REC_4-21

LINK_STATUS-19REC_7-17REC_2-15REC_5-13REC_8-11REC_6-9REC_9-7

RCV_MODE-5DIP_FOTO-3

SYNC_POL-1

Figure 3. JP3 Pin Numbering, Edge of Board

Figure 4. JP4 Pin Numbering, Top Side ofBoard View (Pins Are On the Bottom)

1-SYNC_POL3-DIP_FOTO5-RCV_MODE7-REC_99-REC_611-REC_813-REC_515-REC_217-REC_719-LINK_ST ATUS21-REC_423-REC_325-REC_027-REC_129-XMIT_931-RCV_CLK133-RCV_CLK035-XMIT_837-ENB YTESYNC39-XMIT_741-XMIT_643-XMIT_345-XMIT_447_XMIT_049-XMIT_551-XMIT_253-XMIT_155-GND57-LINK_CONTROL59-GNDGND-60

LOOP_BACK-58XMITCLOCK-56

RP-54GND-52GND-50VCC-48RDY-46GND-44VCC-42GND-40

RESET-38GND-36VCC-34GND-32GND-30VCC-28GND-26

EXTREFCLK-24VCC-22

BYTE_SYNC-20GND-18GND-16

XMIT_BISTEN-14XMIT_ENN-12

XMIT_MODE-10XMIT_ENA-8

SWRCVBISTEN-6DIP_RCVA/B-4

CD_POL-2

1-REC_913-REC-82-GND14-REC_53-REC_615-VCC4-REC_416-REC_35-VCC17-REC_16-REC_018-GND7-RCV_CLK119-RCV_CLK08-VCC20-ENB YTESYNC9-XMIT_421-GND10-XMIT_122-XMIT_211-GND23-N/C12-XMITCL OCK24-VCCLOOP_BACK-36

VCC-48GND-35

LINK_CONTROL-47XMIT_0-34XMIT_5-46XMIT_3-33

N/C-45XMIT_6-32XMIT_7-44

VCC-31XMIT_8-42RESET-30XMIT_9-42

GND-29GND-41

GND-40N/C-28

REC_2-27GND-39GND-26

LINK_STATUS-38REC_7-25

BYTE_SYNC-37


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while it is plugged into a mating connector. The numberingsequence for the JP4 connector pins is shown in Figure 4.

The connector is made from forty-eight 0.025″ square pinssoldered into the board. To allow full mating with anOLC-compatible connector, these pins must extend at least0.250″ beyond the bottom surface of the board.

Connector PinoutsThe CY9266 provides three interface connectors to the user:JP2, JP3, and JP4. Table 1 shows which signal is present oneach connector pin.

Table 1. I/O Connector Pinouts

Pin No. JP3 JP2 JP4

Pin No. JP3 JP2 JP4

1 SYNC_POL SYNC_POL REC_9 31 RCV_CLK1 RCV_CLK1 VCC

2 CD_POL CD_POL GND 32 GND GND XMIT_6

3 DIP_FOTO DIP_FOTO REC_6 33 RCV_CLK0 RCV_CLK0 XMIT_3

4 DIP_RCVA/B DIP_RCVA/B REC_4 34 VCC VCC XMIT_0

5 RCV_MODE RCV_MODE VCC 35 XMIT_8 XMIT_8 GND

6 SWRCVBISTEN SWRCVBISTEN REC_0 36 GND GND LOOP_BACK

7 REC_9 REC_9 RCV_CLK1 37 ENBYTESYNC ENBYTESYNC BYTE_SYNC

8 XMIT_ENA XMIT_ENA VCC 38 RESET RESET LINK_STATUS

9 REC_6 REC_6 XMIT_4 39 XMIT_7 XMIT_7 GND

10 XMIT_MODE XMIT_MODE XMIT_1 40 GND GND GND

11 REC_8 REC_8 GND 41 XMIT_6 XMIT_6 GND

12 XMIT_ENN XMIT_ENN XMITCLOCK 42 VCC VCC XMIT_9

13 REC_5 REC_5 REC_8 43 XMIT_3 XMIT_3 XMIT_8

14 XMIT_BISTEN XMIT_BISTEN REC_5 44 GND GND XMIT_7

15 REC_2 REC_2 VCC 45 XMIT_4 XMIT_4 N/C

16 GND GND REC_3 46 RDY RDY XMIT_5

17 REC_7 REC_7 REC_1 47 XMIT_0 XMIT_0 LINK_CONTROL

18 GND GND GND 48 VCC VCC VCC

19 LINK_STATUS LINK_STATUS RCV_CLK0 49 XMIT_5 XMIT_5

20 BYTE_SYNC BYTE_SYNC ENBYTESYNC 50 GND GND

21 REC_4 REC_4 GND 51 XMIT_2 XMIT_2

22 VCC VCC XMIT_2 52 GND GND

23 REC_3 REC_3 N/C 53 XMIT_1 XMIT_1

24 EXTREFCLK EXTREFCLK VCC 54 RP RP

25 REC_0 REC_0 REC_7 55 GND GND

26 GND GND GND 56 XMITCLOCK XMITCLOCK

27 REC_1 REC_1 REC_2 57 LINK_CONTROL LINK_CONTROL

28 VCC VCC N/C 58 LOOP_BACK LOOP_BACK

29 XMIT_9 XMIT_9 GND 59 GND

30 GND GND RESET 60 GND


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Signal Naming ConventionsThere are three types of signal names used throughout thisdocument: I/O connector pin names, on-board signal names,and HOTLink Transmitter and Receiver pin names. Except forthe transmit and receive data buses, these names are unique.

The names used for the transmit and receive data bus pinson connectors JP2, JP3, and JP4 are different from the signalnames present on the HOTLink Transmitter and Receiver.The functional names for these signals also change depend-ing on the current operating mode of the HOTLink Transmitteror Receiver. Table 2 lists the transmit data bus signals and thenames mapped to them in each transmitter mode.

The output data bus from the HOTLink Receiver is pipelinedwith a single register stage between the receiver outputs andthe board output pins. Table 3 lists the receive data bus sig-nals and the names mapped to them in each receiver mode.

.

Signal DescriptionsThe I/O signals listed in Table 1 fall into six groups: power,switched control, control, status, clock, and data. These sig-nals are described in Table 4.

Table 2. Transmit Bus Signal Name Map

Transmit Bus Input Pin Name

HOTLink Transmitter Pin Name

Encoded Mode Bypass Mode

XMIT_0 SC/D Da

XMIT_1 D0 Db

XMIT_2 D1 Dc

XMIT_3 D2 Dd

XMIT_4 D3 De

XMIT_5 D4 Di

XMIT_6 D5 Df

XMIT_7 D6 Dg

XMIT_8 D7 Dh

XMIT_9 SVS Dj

Table 3. Receive Bus Signal Name Map

Receive Bus Output Pin Name

HOTLink Receiver Pin Name

Decode Mode Bypass Mode

REC_0 SC/D Qa

REC_1 Q0 Qb

REC_2 Q1 Qc

REC_3 Q2 Qd

REC_4 Q3 Qe

REC_5 Q4 Qi

REC_6 Q5 Qf

REC_7 Q6 Qg

REC_8 Q7 Qh

REC_9 RVS Qj


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Table 4. I/O Signal Descriptions

Signal Name Group Description

VCC Power +5 VDC @ 1.0A typical

GND Power Ground

XMIT_BISTEN Input, Switched Control

Transmitter BIST Enable (S1-1). When this signal is LOW, the HOTLink Transmit-ter is placed into its BIST mode. Exact operation of the transmitter is also deter-mined by the settings of the ENA (S1-4) and ENN (S1-3) signals. With both ENA and ENN HIGH, the transmitter outputs an alternating 0–1 pattern (D10.2 or D21.5). If either ENA or ENN is LOW, the transmitter sends a repeating 511-character test sequence. The receiver contains a matching mode that allows this transmitter BIST mode to be used to test the entire serial link without external hardware. The transmitter BIST enable is kept separate from the receiver BIST enable on this board to allow each component to be tested with external patterns that are not part of the BIST sequence.

XMIT_MODE Input, Switched Control

Encoder Mode Select (S1-2). This signal is used to select whether pre-encoded (10-bit) or non-encoded (8-bit) data is clocked into the HOTLink Transmitter. When LOW (Encoded mode), this input enables the internal 8B/10B encoder and accepts 8-bit parallel data from the transmitter data bus (D0–D7 as listed in Table 2). When HIGH (Bypass mode), the encoder is bypassed and a 10-bit pattern is accepted (Da–Dj as listed in Table 2).

XMIT_ENN Input, Switched Control

Enable Next Parallel Transmitter Data (S1-3). This signal is used to control when data is loaded into the HOTLink Transmitter. When this signal is LOW at the rising edge of CKW, the data present on the transmitter inputs at the next rising edge of CKW is loaded, processed, and sent. When this signal is HIGH, the transmitter ignores the data present on its inputs at the next rising edge of CKW and instead inserts a SYNC character (K28.5) to fill in the data stream. When ENA is used for data control, the ENN signal should be tied HIGH, but may be used to enable BIST mode.

XMIT_ENA Input, Switched Control

Enable Parallel Transmitter Data (S1-4). This signal is used to control when data is loaded into the HOTLink Transmitter. When LOW at the rising edge of CKW, the data present on the transmitter inputs is loaded, processed, and sent. When this signal is HIGH, the transmitter ignores the data present on its inputs and instead inserts a SYNC character (K28.5) to fill in the data stream. When ENN is used for data control, the ENA signal should be tied HIGH, but may be used to enable BIST mode.

SWRCVBISTEN Input, Switched Control

Receiver BIST Enable (S1-5). When this signal is LOW, the HOTLink Receiver monitors the data stream for the BIST loop initialization character (D0.0). This signal also enables the BIST PLD (CY7C344–U8), which is used to monitor the progress and status of the BIST loop through the receiver RDY and RVS outputs. When the receiver detects the initialization character, it begins comparing received data with a built-in data sequence that can be used to verify the proper functionality of the transmitter, receiver, and the serial link connecting them. The receiver BIST enable is kept separate from the transmitter BIST enable on this board to allow each component to be tested with external patterns that are not part of the BIST sequence.

RCV_MODE Input, Switched Control

Receiver Mode Select (S1-6). This signal is used to select whether encoded (10-bit) or non-encoded (8-bit) data is output from the receiver. When LOW (De-code mode), this input enables the internal 10B/8B decoder and outputs 8-bit par-allel data (Q0–Q7 as listed in Table 3). When HIGH (Bypass mode), the decoder is bypassed and a 10-bit pattern is output (Qa–Qj as listed in Table 3).


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DIP_RCVA/B Input, Switched Control

DIP-Switch Controlled Receiver A/B Port Select (S1-7). This signal is used to determine which port (INA± or INB±) the receiver uses for the input serial data stream. When LOW, this signal selects the receiver B port that is directly connected to the C port on the transmitter. When HIGH, this signal selects the receiver A port that is connected to the optical receiver output. This signal is also routed through jumper block JP1. In order for this signal to control the port selection of the receiver, it is necessary to have a shorting jumper across the X and Y pins of JP1-C. To allow the LOOP_BACK signal on the I/O connectors (JP2, JP3, and JP4) to control the A/B port selection, this jumper should be moved to JP1-B.

DIP_FOTO Input, Switched Control

DIP-Switch Controlled FOTO (S1-8). This signal is used to enable the A and B differential output drivers of the HOTLink Transmitter. When this signal is LOW, the differential outputs are allowed to follow the pattern of the data serialized by the transmitter. When this signal is HIGH, the A and B differential outputs of the trans-mitter are driven to a logic zero state (+ output is logic HIGH, – output is logic LOW). This places an attached optical transmitter in a state where no light is output. This signal is also routed through jumper block JP1. In order for this signal to control the FOTO (fiber-optic transmitter-off) enable on the transmitter, it is necessary to have a shorting jumper across the X and Y pins of JP1-E. To allow the LINK_CONTROL signal on the I/O connectors (JP2, JP3, and JP4) to control the FOTO enable, this jumper should be moved to JP1-F.

CD_POL Input, Switched Control

Signal-Detect Polarity Select (S1-9). This input selects the output polarity of the LINK_STATUS signal. When LOW, the LINK_STATUS signal is HIGH when a valid signal is present. When HIGH, the LINK_STATUS signal is LOW when a valid signal is present.

SYNC_POL Input, Switched Control

Byte Sync Polarity Select (S1-10). This input, in conjunction with the HOTLink Receiver MODE input, selects the active level of the BYTE_SYNC signal.When LOW with the receiver in Bypass mode, the BYTE_SYNC signal is LOW when a K28.5 SYNC character is present on the receive data bus. When HIGH with the receiver in Bypass mode, the BYTE_SYNC signal is HIGH when a K28.5 SYNC character is present on the receive data bus.When LOW with the receiver in Decode mode, the BYTE_SYNC output remains HIGH for strings of K28.5 SYNC characters, or while awaiting the first K28.5 SYNC character after being placed into Reframe mode (RF is set HIGH). When HIGH with the receiver in Decode mode, the BYTE_SYNC output remains LOW for strings of K28.5 SYNC characters, or while awaiting the first K28.5 SYNC character after being placed into Reframe mode (RF is set HIGH).

LOOP_BACK Input, Control Loopback Control. This signal is used to determine which port (A or B) the HOTLink Receiver uses for the input serial data stream. When LOW, this signal selects the receiver B port that is connected directly to the transmitter C port. When HIGH, this signal selects the receiver A port that is connected to the optical receiver output. This signal is also routed through jumper block JP1. In order for this signal to control the port selection of the receiver, it is necessary to have a shorting jumper across the X and Y pins of JP1-B. To allow the DIP_RCVA/B signal (S1-7, also present on JP2 and JP3) to control the A/B port selection, this jumper should be moved to JP1-C.

ENBYTESYNC Input, Control Enable Byte Sync Detect. This signal controls when the HOTLink Receiver is allowed to reframe to the incoming serial data (e.g., acquire character sync). When this signal is HIGH, each K28.5 SYNC character received in the shifter will frame the data that follows. When this signal is LOW, the framing logic in the receiver is disabled. Because the CKR output of the receiver must line up with the reframed data, it is possible to generate significant phase jumps in the CKR clock. To prevent the generation of very short high or low pulses on the CKR output (which could cause timing violations in downstream logic) the Cypress HOTLink Receiver uses look-ahead hardware to prevent these short pulses. Instead, a portion of the clock period for the character preceding the reframed data is lengthened.

Table 4. I/O Signal Descriptions (continued)



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LINK_CONTROL

Input, Control Link Control. This signal is used to enable the A and B differential output drivers of the HOTLink Transmitter. When this signal is LOW, the differential outputs are allowed to follow the pattern of the data serialized by the transmitter. When this signal is HIGH, the A and B differential outputs of the transmitter are driven to a logic zero state (+ output is logic HIGH, – output is logic LOW). This places an attached optical transmitter in a state where no light is output. This signal is also routed through jumper block JP1. In order for this signal to control the FOTO enable on the transmitter, it is necessary to have a shorting jumper across the X and Y pins of JP1-F. To allow the DIP_FOTO signal on the I/O connectors (JP2 and JP3) to control the FOTO enable, this jumper should be moved to JP1-E.

RESET Output, Status Reset/Power OK. This output is used to emulate the voltage monitor function present on the OLC card. It remains active (LOW) until the VCC input to the board is above 4.65V DC. This output also becomes active when the BIST RESET switch (S2) is pressed.

LINK_STATUS Output, Status Link Status. This signal operates as a signal-detect status for the serial interface. The polarity of this signal is determined by the CD_POL input (S1-9). When CD_POL is LOW, LINK_STATUS drives HIGH when a signal is present. When CD_POL is HIGH, LINK_STATUS drives LOW when a signal is present.

RP Output, Clock Read Pulse. This is a 60% LOW duty-cycle pulse train suitable for clocking data out of Cypress’s CY7C42X family of asynchronous FIFOs. This pulse is generated by the HOTLink Transmitter in response to the XMIT_ENA input being active at the rising edge of CKW. For repeated pulses the RP period is the same as CKW, yet is totally independent of the duty cycle of CKW. When the transmitter is in BIST mode, the RP signal remains HIGH for all but the last character of the BIST loop, where it pulses LOW.

XMITCLOCK Input, Output, Clock

Transmitter External Clock. This is the external character-rate clock input. This clock is used to drive the transmitter CKW input. To allow for operation using the on-board oscillator, the XMITCLOCK signal is run through jumper block JP1. To operate using an external HOTLink Transmitter clock source, a shorting jumper should be placed across pins X and Y of JP1-G. To use the on-board oscillator instead, this shorting jumper should be moved to connect pin JP1-GY to JP1-HY. When operated from XMITCLOCK, the receiver REFCLK may also be set to use this same clock. This is done by placing a shorting jumper across pins JP1-HX and JP1-IX. To allow the receiver REFCLK to operate from the on-board oscillator, this jumper should be moved to connect the X and Y pins of JP1-I. The on-board oscillator may also be driven out on the XMITCLOCK line by placing a shorting jumper across pins X and Y of JP1-H.

EXTREFCLK Input, Output, Clock

External Reference Clock. This character-rate clock is used to drive the HOTLink Receiver REFCLK from an external source other than XMITCLOCK. This input may be used to test the tracking and capture range of the receiver PLL. It may also be used to operate the receiver at a different data rate from the transmitter. To allow the receiver PLL to properly lock to the received serial stream, this clock must be within 0.1% of the clock used to generate the received serial data. To drive the receiver REFCLK from this clock source, a shorting jumper should be placed across pins JP1-IX and JP1-JX.The on-board oscillator may also be selected to drive the EXTREFCLK line by placing a shorting jumper across pins X and Y of JP1-J. With this jumper in place it is still possible to drive the receiver REFCLK input from the on-board oscillator by placing a shorting jumper across the X and Y pins of JP1-I.

RCV_CLK0 Output, Clock Receive Clock 0. This is the character-rate recovered clock used for received data. The period of this clock is determined by the serial data rate entering the HOTLink Receiver. The duty-cycle of this signal is determined by the receiver and is fixed at 50%. This clock may experience a large phase jump when reframing to a serial data stream. The phasing on this clock is such that the rising edge of the clock occurs coincident with the start of each interval where a character is present on the output received data bus. This signal is a buffered form of the HOTLink Receiver CKR clock.




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RCV_CLK1 Output, Clock Receive Clock 1. This is the character-rate recovered clock used for received data. The period of this clock is determined by the serial data rate entering the HOTLink Receiver. The duty-cycle of this signal is determined by the receiver and is fixed at 50%. This clock may experience a large phase jump when reframing to a serial data stream. The phasing on this clock is such that the rising edge of the clock occurs near the center of each interval where a character is present on the output received data bus. This signal is a buffered and inverted form of the HOTLink Receiver CKR clock.

RDY Output, Clock RDY (Ready). This signal is used both as a HOTLink Receiver data output clock and a status indicator for the receiver when in BIST mode. This is an unbuffered output from the receiver. It is normally used to clock valid data from the receiver data bus into synchronous FIFOs. Because of the additional pipeline register in the data bus (added for OLC compatibility) this signal will operate one character prior to the data being available at the I/O connectors.

BYTE_SYNC Output, Data Byte Sync Detected. This signal is a pipelined form of the receiver RDY output. This additional pipeline stage for the RDY signal (and the rest of the receiver data bus) was added to match the specific timing of the OLC Byte Sync signal. The active level of this output is determined both by the operating mode of the HOTLink Receiver and by the state of the SYNC_POL input.With the HOTLink Receiver in Bypass mode, the BYTE_SYNC signal is used as a K28.5 SYNC character indicator. With SYNC_POL LOW, BYTE_SYNC is LOW when a K28.5 SYNC character is present on the receive data bus. With SYNC_POL HIGH, BYTE_SYNC is HIGH when a K28.5 SYNC character is present on the receive data bus.With the receiver in Decode mode, the BYTE_SYNC signal is used as a valid data indicator. With SYNC_POL LOW, BYTE_SYNC is LOW whenever a usable data character is present on the receive data bus. With SYNC_POL HIGH, BYTE_SYNC is HIGH whenever a usable data character is present on the receive data bus.

REC_9 Output, Data RVS(Qj). This signal is a series-terminated, pipelined form of the HOTLink Receiver RVS(Qj) signal. This termination and additional pipeline stage for the RVS(Qj) sig-nal (and the rest of the receive data bus) was added to match the specific timing and signal characteristics of the OLC card.

REC_8 Output, Data Q7(Qh). This signal is a series-terminated, pipelined form of the HOTLink Receiver Q7(Qh) signal.

REC_7 Output, Data Q6(Qg). This signal is a series-terminated, pipelined form of the HOTLink Receiver Q6(Qg) signal.

REC_6 Output, Data Q5(Qf). This signal is a series-terminated, pipelined form of the HOTLink Receiver Q5(Qf) signal.

REC_5 Output, Data Q4(Qi). This signal is a series-terminated, pipelined form of the HOTLink Receiver Q4(Qi) signal.

REC_4 Output, Data Q3(Qe). This signal is a series-terminated, pipelined form of the HOTLink Receiver Q3(Qe) signal.

REC_3 Output, Data Q2(Qd). This signal is a series-terminated, pipelined form of the HOTLink Receiver Q2(Qd) signal.

REC_2 Output, Data Q1(Qc). This signal is a series-terminated, pipelined form of the HOTLink Receiver Q1(Qc) signal.

REC_1 Output, Data Q0(Qb). This signal is a series-terminated, pipelined form of the HOTLink Receiver Q0(Qb) signal.

REC_0 Output, Data SC/D(Qa). This signal is a series-terminated, pipelined form of the HOTLink Re-ceiver SC/D(Qa) signal.

XMIT_9 Input, Data SVS(Dj). This signal is the SVS(Dj) input to the HOTLink Transmitter. It is latched into the transmitter in the rising edge of CKW, when enabled by ENA or ENN.




10

Power Signals

The CY9266 Evaluation Board is designed to operate from asingle +5V ±10% DC supply capable of delivering 1.0A (typi-cal). All VCC and GND pins on JP2, JP3, and JP4 are (respec-tively) common to each other. There are no distinctions madefor separate supplies pins for the different logic sections.

Switched Control Signals

The CY9266 Evaluation Board contains a 10-position DIPswitch (S1). This switch is connected in parallel with a numberof control signals on JP2 and JP3. Each of these control sig-nals is pulled-up by a 5-kΩ resistor through R-pack R20. Noneof these Switched Control signals are available at the JP4connector.

The signals present in this group are:

• XMIT_BISTEN (S1-1)

• XMIT_MODE (S1-2)

• XMIT_ENN (S1-3)

• XMIT_ENA (S1-4)

• SWRCVBISTEN (S1-5)

• RCV_MODE (S1-6)

• DIP_RCVA/B (S1-7)

• DIP_FOTO (S1-8)

• CD_POL (S1-9)

• SYNC_POL (S1-10)

To allow these signals to be controlled through the externalconnectors (JP2 and JP3), the corresponding S1 switch mustbe in the off (open) position. Care should be taken when driv-ing these signals, as any switch inadvertently left in the closedposition will present a direct short to ground for an attacheddriver.

Control Signals

In addition to the Switched Control signals that are onlypresent on JP2 and JP3, three additional control inputs arepresent that connect to JP2, JP3, and JP4.

These control signals are:

• LOOP_BACK

• ENBYTSYNC

• LINK_CONTROL

These control inputs are connected directly to the HOTLinkTransmitter or Receiver. Because the HOTLink parts containinternal pull-up resistors on their TTL compatible inputs,these signals may be driven with either open-collector buffers,CMOS, or TTL drive levels.

Status Signals

Two status output signals (RESET and LINK_STATUS) areprovided at all three I/O connectors. The RESET signal is aslow-speed signal and does not require the series terminationused with LINK_STATUS.

Clock Signals

Six signals are available at the I/O connectors that are usedas clocks in some form. Two of these (XMITCLOCK andEXTREFCLK) are input/output clocks that are routed throughthe JP1 jumper block, and three are output clocks.

These clock signals are:

• XMITCLOCK

• EXTREFCLK

• RP

• RDY

• RCV_CLK0

• RCV_CLK1

XMIT_8 Input, Data D7(Dh). This signal is the D7(Dh) input to the HOTLink Transmitter. It is latched into the transmitter in the rising edge of CKW, when enabled by ENA or ENN.

XMIT_7 Input, Data D6(Dg). This signal is the D6(Dg) input to the HOTLink Transmitter. It is latched into the transmitter in the rising edge of CKW, when enabled by ENA or ENN.

XMIT_6 Input, Data D5(Df). This signal is the D5(Df) input to the HOTLink Transmitter. It is latched into the transmitter in the rising edge of CKW, when enabled by ENA or ENN.

XMIT_5 Input, Data D4(Di). This signal is the D4(Di) input to the HOTLink Transmitter. It is latched into the transmitter in the rising edge of CKW, when enabled by ENA or ENN.

XMIT_4 Input, Data D3(De). This signal is the D3(De) input to the HOTLink Transmitter. It is latched into the transmitter in the rising edge of CKW, when enabled by ENA or ENN.

XMIT_3 Input, Data D2(Dd). This signal is the D2(Dd) input to the HOTLink Transmitter. It is latched into the transmitter in the rising edge of CKW, when enabled by ENA or ENN.

XMIT_2 Input, Data D1(Dc). This signal is the D1(Dc) input to the HOTLink Transmitter. It is latched into the transmitter in the rising edge of CKW, when enabled by ENA or ENN.

XMIT_1 Input, Data D0(Db). This signal is the D0(Db) input to the HOTLink Transmitter. It is latched into the transmitter in the rising edge of CKW, when enabled by ENA or ENN.

XMIT_0 Input, Data SC/D(Da). This signal is the SC/D(Da) input to the HOTLink Transmitter. It is latched into the transmitter in the rising edge of CKW, when enabled by ENA or ENN.




11

Of the output clocks, the RP and RDY signals are only avail-able at JP2 and JP3. The RP signal is generated in theHOTLink Transmitter and is used for reading data from asyn-chronous FIFOs, while the RDY signal is generated in theHOTLink Receiver and is used for writing data into asynchro-nous FIFOs. When interfacing to synchronous FIFOs , the RPsignal is not normally used. Because these signals are notpresent in JP4, they are not series terminated.

The other two output clocks (RCV_CLK0 and RCV_CLK1)are a buffered form of the recovered CKR clock from the re-ceiver. The RCV_CLK1 signal is an inverted form ofRCV_CLK0.

Data Signals

The CY9266 Evaluation Board has two data buses: one input(to the HOTLink Transmitter) and one output (from theHOTLink Receiver).

The input data bus consists of ten parallel transmit data sig-nals that are sampled at the rising edge of the HOTLink Trans-mitter CKW clock. In addition to these ten signals, ENN andENA (while part of the Switched Control signals) may also beconsidered part of the data bus as they are also sampled atthis same time. While the XMIT_BISTEN input is also sam-pled at this same time, it is not normally used to transfer dataand is therefore not considered part of the input data bus.

The output data bus is comprised of ten parallel received datasignals that are synchronous to the HOTLink Receiver CKRclock. To meet specific timing requirements for OLC compat-ibility, there is also an external pipeline register between theHOTLink Receiver data bus output, and the received data busconnected to JP2, JP3, and JP4.

One other signal, BYTE_SYNC, is also clocked through thispipeline register and is thus considered part of the data bus.

All signals on this output bus are series-terminated with a 22Ωinline resistor to minimize transmission line ringing.

Configuration SettingsThe CY9266 board may be user-configured to allow manymodes of operation. This configuration is performed throughthe jumper block JP1 and the option select switch S1.

JP1 Jumper Block

The JP1 jumper block is used for configuring those options ofthe CY9266 that are (primarily) either to protect the boardfrom signal contention, or for those signals having multiplesources and destinations. These functions are:

• Receiver Mode Select

• Receiver Loopback Source Select

• Transmitter Mode Select

• Transmitter FOTO Source Select

• Transmitter Clock (CKW) Source Select

• Receiver Reference Clock (REFCLK) Source Select

JP1 exists as a 2 x 10 matrix of 0.025″ square pins on the topof the board. The rows in this matrix are identified on the topsilk screen as A through J. The columns are identified as Xand Y. A drawing of the JP1 jumper block is shown in Figure 5.

Receiver Mode Select

This jumper ties pins X and Y of JP1-A together. It is used toconnect the receiver’s MODE select pin to the option select

switch (S1-6), and to allow the HOTLink Receiver mode to beset to the clock Test mode (see Figure 13). The three modesof receiver operation are:

• Decode Mode—S1-6 ON (closed)

• Bypass Mode—S1-6 OFF (open)

• Test Mode—JP1-A, X and Y open

Because this clock Test mode is not normally used for com-munications testing, the jumper (JP1-A) is permanently wiredin place with a foil trace on the bottom of the board. For thoseusers who wish to actually place the receiver in Test mode, itmay be necessary to cut this foil on the back of the board.

Once this foil has been cut, it will be necessary to use a short-ing jumper across pins X and Y of JP1-A to allow the two datamodes of the receiver to be set by the option select switch(S1-6) and the RCV_MODE signal on JP2 and JP3.

Receiver Source Loopback Select

This function uses two positions (JP1-B and JP1-C) of thejumper block to select the source of the HOTLink Receiverloopback signal. Because this jumper is used to select be-tween one of two sources, only one of these two positions(JP1-B or JP1-C) may contain a shorting jumper at any onetime (see Figures 10 and 11).

By placing a shorting jumper across pins X and Y of JP1-B,the receiver loopback (A/B) input is then controlled by theLOOP_BACK signal on JP2, JP3, and JP4. If this shortingjumper is moved to JP1-C, then the receiver loopback input iscontrolled by the option select switch (S1-7) and theRCV_MODE signal on JP2 and JP3. If a jumper is not presentin either position, the INA± path is selected (external serialdata).

Transmitter Mode Select

This jumper ties pins X and Y of JP1-D together. It is used toconnect the transmitter MODE select pin to the option selectswitch, and to allow the HOTLink Transmitter mode to be setto the clock Test mode (see Figure 7). The three modes oftransmitter operation are:

• Encode Mode—S1-2 ON (closed)

Figure 5. JP1, Top Side View

JP1

-RCV_MODE-LOOPBACK-DIP_RCVA/B-XMIT_MODE-DIP_FOTO-LINK_CONTROL-CKW-LCLCLK-LCLCLK-LCLCLK

X Y

ABCDEFGHIJ

RCVMODE-RCV_A/B-

XMITMODE-ENLFOTO-ENLFOTO-

XMITCLOCK-XMITCLOCK-

REFCLK-EXTREFCLK-

RCV_A/B-


12


• Test Mode—JP1-D, X and Y open

Because this clock Test mode is not expected to be used fornormal data communications testing, the jumper (JP1-D) ispermanently wired in place with a foil trace on the bottom ofthe board. For those users who wish to actually place thetransmitter in Test mode, it may be necessary to cut this foilon the back of the board.

Once this foil has been cut, it will be necessary to use a jump-er across JP1-D to allow the two data modes of the transmit-ter to be set by the option select switch (S1-2) and theXMIT_MODE signal on JP2 and JP3.

Transmitter FOTO Source Select

This function uses two positions (JP1-E and JP1-F) of thejumper block to select the source of the HOTLink TransmitterFOTO signal. Because this jumper is used to select from oneof two sources, only one of these two positions (E or F) maycontain a jumper at any one time (see Figures 8 and 9).

By placing a shorting jumper across pins X and Y of JP1-F,the HOTLink Transmitter FOTO signal is then controlled bythe LINK_CONTROL signal on JP2, JP3, and JP4. If thisshorting jumper is moved to JP1-E, then the transmitterFOTO signal is controlled by the option select switch (S1-8)and the DIP_FOTO signal on JP2 and JP3. If a jumper is notpresent in either position, the transmitter OUTA± and OUTB±differential drivers are placed in a mode where a differentiallogic 0 is driven.

Transmitter Clock Source Select

The HOTLink Transmitter CKW clock can be sourced fromtwo different signals: LCLCLK from the on-board oscillatorand XMITCLOCK from JP2, JP3, and JP4 (see Figure 7).

To select the on-board oscillator, a shorting jumper should beplaced across pins JP1-GY and JP1-HY. To select theXMITCLOCK signal, this shorting jumper should be moved toconnect pins X and Y of JP1-G. To allow the transmitter tooperate, it is necessary for a jumper to be in one (and onlyone) of these two positions.

Receiver Reference Clock Source Select

The HOTLink Receiver REFCLK signal can be sourced fromthree different signals: LCLCLK from the on-board oscillator,XMITCLOCK (from JP2, JP3, and JP4), and EXTREFCLK(from JP2 and JP3) (see Figure 13).

To select the on-board oscillator, a shorting jumper should beplaced across the X and Y pins of JP1-I. To select theXMITCLOCK signal, this shorting jumper should be moved toconnect pin X of JP1-I to pin X of JP1-H. To select theEXTREFCLK signal (used for PLL range testing), the shortingjumper should be placed across pin X of JP1-I and pin X ofJP1-J. To allow the receiver to operate it is necessary for ajumper to be in one (and only one) of these three positions.

S1 Option Select Switch

The S1 Option Select Switch is used for configuring thoseoptions of the CY9266 that may be changed on a regularbasis or are used to operate the board in a standalone mode.These functions are:

• Transmitter BIST Enable

• Encoder Mode Select

• Enable Next Parallel Transmitter Data

• Enable Parallel Transmitter Data

• Receiver BIST Enable

• Receiver Mode Select

• Receiver A/B Port Select

• Transmitter FOTO Enable

• Signal-Detect Polarity

• Byte Sync Polarity

S1 exists as a 10-position DIP switch. The switch positions(numbered 1 through 10) are identified on the top of theswitch. When a switch is on (closed), the signal connected tothat switch is tied directly to ground. When a switch is off(open), the signal on that switch is pulled up through a 5-kΩresistor in R-pack R20.

These signals are also connected to pins on JP2 and JP3 toallow external logic to control these functions. A drawing ofthe S1 option select switch is shown in Figure 6.

Transmitter BIST Enable

Switch S1-1 (XMIT_BISTEN) is used to enable the HOTLinkTransmitter BIST function. When this switch is on (closed), theBISTEN input to the transmitter is pulled LOW, placing thetransmitter into its BIST loop. The exact patterns transmittedare determined by the levels on the XMIT_ENN andXMIT_ENA signals, located on S1-3 and S1-4 respectively(see Figure 7).

Encoder Mode Select

Switch S1-2 (XMIT_MODE) is used to select the data encod-ing mode of the HOTLink Transmitter. When this switch is on(closed), the internal 8B/10B encoder is enabled and the 8-bitdata characters are encoded into 10-bit transmission charac-ters. When this switch is off (open), the encoder is bypassedand the transmitter accepts 10-bit patterns for direct serializa-tion (see Figure 7).

Enable Next Parallel Transmitter Data

Switch S1-3 (XMIT_ENN) is used, along with S1-1 (transmit-ter BIST enable) and S1-4 (XMIT_ENA), to select which datapatterns are sent during HOTLink Transmitter BIST opera-tions (see Figure 7).

Figure 6. S1 Option Select Switch

12

34

56

78

910

OF

F

- XMIT_BISTEN

- XMIT_MODE

- XMIT_ENN

- XMIT_ENA

- SWRCVRBISTEN

- RCV_MODE

- DIP_RCV A/B

- DIP_FOTO

- CD_POL

- SYNC_POL


13

If BIST is enabled (S1-1 on and S1-4 off), setting this switchoff (open) causes the transmitter to send an alternating 1-0pattern (D10.2 or D21.5). When turned on (closed), it enablesan internal pattern generator in the transmitter that generatesa repeating sequence of 511 10-bit patterns.

For normal data transfer operations this switch should remainoff, with the XMIT_ENN signal controlled externally throughJP2 and JP3.

Enable Parallel Transmitter Data

Switch S1-4 (XMIT_ENA) is used, along with S1-1 (transmit-ter BIST enable) and S1-3 (XMIT_ENN), to select which datapatterns are sent by the HOTLink Transmitter during BISToperations (see Figure 7).

If BIST is enabled (S1-1 on and S1-3 off), setting S1-4 off(open) causes the transmitter to send an alternating 1-0 pat-tern (D10.2 or D21.5). When turned on (closed), it enables aninternal pattern generator in the transmitter that produces arepeating sequence of 511 10-bit patterns.

For normal data transfer operations this switch should remainoff, with the XMIT_ENA signal controlled externally throughJP2 and JP3.

When operated from the JP4 system connector, this switchshould be turned on (closed), because the system hardwareis required to provide a valid 10-bit transmission character ordata character for each CKW clock.

Receiver BIST Enable

Switch S1-5 (SWRCVBISTEN) is used to enable the HOTLinkReceiver BIST function (see Figure 13). When this switch ison (closed), the receiver awaits a D0.0 transmission character(sent once per BIST loop). When this character is detectedthe BIST state machine in the receiver begins matching thefollowing received transmission characters with its internalpattern generator. This pattern generator follows the samesequence of patterns as those sent by the HOTLink Transmit-ter when sending its BIST sequence.

When this switch is off (open), the HOTLink Receiver oper-ates in one of its two data modes (Decode or Bypass).

Receiver Mode Select

Switch S1-6 (RCV_MODE) is used to select the data decod-ing mode of the HOTLink Receiver (see Figure 13). When thisswitch is on (closed), the internal 10B/8B decoder is enabledand the received 10-bit transmission characters are decodedinto 8-bit data characters. When this switch is off (open), thedecoder is bypassed and the receiver outputs 10-bit transmis-sion characters directly to the output data and status pins.

Receiver A/B Port Select

Switch S1-7 (DIP_RCVA/B) is used to select which input port(A or B) the HOTLink Receiver should use for receiving serialdata (see Figures 10 and 11). While the A/B input of the re-ceiver is a 100K ECL (emitter-coupled logic) compatible input,it is connected here to allow control from a switch or TTLdriver. This requires use of an external resistor network, con-nected between that input and the select switch, to allow fullrail-to-rail swings to be used.

When this switch is on (closed), the INB+ input to the HOTLinkReceiver is selected. This input is directly connected to theOUTC+ output from the HOTLink Transmitter. This is the Lo-cal Loopback mode for the CY9266 evaluation board that al-

lows the transmitter and receiver to be tested without an ex-ternal serial data cable or optical module.

When this switch is off (open), the INA± differential input ofthe receiver is enabled to accept data from the optical module(U4) or copper cable.

Transmitter FOTO Enable

Switch S1-8 (DIP_FOTO) is used to enable the OUTA± andOUTB± differential output drivers of the HOTLink Transmitter.When this switch is on (closed), the differential outputs areallowed to follow the pattern of the data serialized by thetransmitter (see Figures 8 and 9). When this switch is off(open), the OUTA± and OUTB± differential outputs of thetransmitter are driven to a logic zero state (+ output is logicLOW, – output is logic HIGH). This places an attached opticaltransmitter in a state where no light is output, or presents notransitions on a copper cable.

Signal-Detect Polarity

Switch S1-9 is used to control the active level of the signal-de-tect output signal, LINK_STATUS. When this switch is on(closed) LINK_STATUS is driven HIGH when a signal ispresent and LOW when one is not. When this switch is off(open) these levels are reversed (see Figure 13).

The signal-detect status is also displayed on one of the deci-mal point indicators of the two-digit BIST display. When theindicator is on, a signal is present. The state of S1-9 has noaffect on the operation of this indicator.

Byte Sync Polarity

Switch S1-10 is used to control the active level of theBYTE_SYNC output signal. This level is also affected by theoperating mode of the HOTLink Receiver (S1-6) (see Figure13).

With the HOTLink Receiver in Bypass mode, theBYTE_SYNC signal is used as a K28.5 SYNC character indi-cator. With SYNC_POL LOW, BYTE_SYNC is LOW when aK28.5 SYNC character is present on the receive data bus.With SYNC_POL HIGH, BYTE_SYNC is HIGH when a K28.5SYNC character is present on the receive data bus.

With the receiver in Decode mode, the BYTE_SYNC signal isused as a valid data indicator. With SYNC_POL LOW,BYTE_SYNC is LOW whenever a usable data character ispresent on the receive data bus. With SYNC_POL HIGH,BYTE_SYNC is HIGH whenever a usable data character ispresent on the receive data bus.

CY9266 SchematicThe complete schematic for the CY9266–F and CY9266–PEvaluation Boards is shown in Appendix A, and the schematicfor the CY9266–C and CY9266–T Evaluation Boards isshown in Appendix B.

Sheet 1 of the top-level schematic contains four functionalblocks, which are detailed on the remaining pages of theschematic.

Sheet 2 contains the power-supply filtering and bypass ca-pacitors. It also contains a sacrificial Zener diode that is usedto protect the components on the board in case of over volt-age or incorrect connection of the power supply.

Sheet 3 contains the BIST PLD and the error/status displays.


14

Sheet 4 of Appendix A contains the HOTLink Transmitter andReceiver, as well as the optical interface module. It also con-tains the on-board oscillator and option-select DIP switch.

Sheet 4 of Appendix B contains the HOTLink Transmitter andReceiver, as well as the copper interface and signal-detectcircuit. It also contains the on-board oscillator and option-se-lect DIP switch.

Sheet 5 contains the parallel interface connectors, the voltagemonitor/reset generator, and the OLC-compatibility registers.

Theory of OperationThe CY9266 Evaluation Board operation is broken down intofive functional sections:

• Transmitter Parallel Interface

• Transmitter to Optical Module or Copper Serial Interface

• Optical Module or Copper to Receiver Serial Interface

• Receiver Parallel Interface

• BIST and Support Hardware

Transmitter Parallel Interface

The purpose of the transmitter parallel interface is to loadparallel data from an external source and move that data tothe shifter inside the transmitter. This portion of the designconsists of three parts: the transmit data bus, transmitter con-trol signals, and transmitter clocks. A simplified schematic ofthis interface is shown in Figure 7.

Transmit Data Bus

The transmit data bus is composed of the ten signals namedXMIT_0 through XMIT_9. This bus may be driven from any ofthree possible sources: JP2, JP3, or JP4. The data presenton this bus is sampled by the HOTLink Transmitter(U1-CY7B923) at the rising edge of CKW.

The information present on the transmit data bus is interpret-ed by the HOTLink Transmitter in one of two ways, based on

the setting of the MODE input to the transmitter. When MODEis HIGH (Bypass mode), all ten signals are accepted as theactual data to be transmitted and are fed directly to the shifter.The letter form (Da–Dj, as shown in Figure 7) of the bit iden-tifiers is followed for this setting. These designators specifywhich encoded data bit is connected to a specific XMIT_0 toXMIT_9 signal. In this mode the user must encode the datainto the 10-bit patterns used to send data across the serialinterface. While it is not necessary to use the 8B/10B codedescribed in the HOTLink datasheet, it is advised that thiscode be used for simplicity. If another code is used, it is theuser’s responsibility to insure that sufficient transitions arepresent in the serial data stream to allow the receiver to prop-erly phase-lock to the serial data stream. For the HOTLinkReceiver to provide character framing and synchronization,the K28.5 pattern must be used for framing initialization.

When the MODE input is LOW (Encode mode), the internal8B/10B encoder is enabled. In this mode the ten input bits arepartitioned into eight data bits (D0–D7) and two data-modifierbits (SC/D and SVS). For transmitting normal data patterns,both the SVS and SC/D pins must be LOW. In this setting the8-bit data character present on D0–D7 is latched at the risingedge of CKW and presented to the encoder. The encoderthen converts the data character into the appropriate 10-bittransmission character. Following conversion, the transmis-sion character is loaded into the shifter.

The two data-modifier bits, SC/D (Special Character/Data Se-lect) and SVS (Send Violation Symbol), are used to sendtransmission characters other than those used to representdata. When the SC/D input is HIGH, the normal 8B/10B en-coding of the data characters present on D0–D7 is changed.Now special control codes are generated (see listing in theCY7B923/CY7B933 data sheet). These control codes areused to send framing, control, status, and other supervisoryfunctions across the interface.

The SVS pin is used for diagnostic purposes. When this inputis HIGH, the HOTLink Transmitter shifter is loaded with a10-bit pattern that is not a valid 8B/10B transmission charac-ter. When the HOTLink Receiver detects this encoding viola-tion it responds with its RVS (Received Violation Symbol) out-put.

Note: The SVS input is intended for diagnostic purposes only.If used within normal message traffic, it may cause unexpect-ed receive errors.

Transmitter Control Signals

In addition to the transmit data bus, four other signals areused to control the serial data stream generated by theHOTLink Transmitter. Two of these signals (BISTEN andMODE) control operating modes of the transmitter. The othertwo signals (ENN and ENA) are used to specify when validdata is present on the transmit data bus.

Unlike the transmit data bus, these control signals are notconnected to JP4, but are instead connected to JP2, JP3, andseparate switches of S1. These switches allow the controlinputs to be set LOW or HIGH when an external controller isnot present. These switches are used both to control BISTmode for standalone applications and to set the proper oper-ating characteristics for systems which only connect to JP4.

The BISTEN and MODE inputs are used to control whichtransmission characters are generated by the HOTLink Trans-

Figure 7. Transmitter Parallel Interface


15

mitter. Setting BISTEN LOW places the HOTLink Transmitterinto one of two auto pattern-generation modes.

When BISTEN is LOW and both ENN and ENA are HIGH, theHOTLink Transmitter sends an alternating 1–0 pattern (D10.2or D21.5). This pattern provides the highest baseband outputfrequency that the transmitter can generate, and is equal to5x the frequency of CKW. This pattern may be useful to testor characterize various serial link components (i.e., fiber-opticmodules, jitter tests, etc.).

When BISTEN is LOW and either ENN or ENA is also LOW,the HOTLink Transmitter begins a repeating test sequencethat allows the transmitter and receiver to work together totest the functionality of the entire serial link. The repeatingsequence is 511 characters in length and includes all stan-dard codes as well as patterns that are normally consideredcode violations. This sequence may also be useful for per-forming serial link margin tests.

The MODE input pin is used to select both how the data onthe transmit data bus is interpreted (encoded or non-encod-ed) and to place the HOTLink Transmitter into a clock Testmode. This input is capable of selecting one of these threepossible modes from a single pin by use of an internalthree-level comparator. These modes are:

• Encode Mode—S1-2 ON (closed)


• Test Mode—JP1-D, X and Y open

When the MODE input is LOW (Encode mode), the internal8B/10B encoder is enabled. This allows the transmit data busto be interpreted as an 8-bit data bus (D0–D7) with two controlbits (SC/D and SVS). When the MODE input is HIGH (Bypassmode), the internal encoder is bypassed. This allows the databus to be interpreted as a 10-bit bus (Da–Dj). Either of thesemodes may be set from JP2, JP3, or S1-2.

The clock Test mode is accessed by allowing the MODE inputpin to float. Through use of an internal bias network in thetransmitter, the MODE input pin is placed at VCC/2. This clockTest mode can be accessed two ways on the board. The eas-iest is to cut the foil on the bottom of the board that shorts theX and Y pins of JP1-D together. Once cut it will be necessaryto place a shorting jumper across these pins to allow JP2,JP3, or S1 to place the transmitter into one of its normal datamodes.

The other method of accessing this mode is to actively biasthe XMIT_MODE pin on JP2 or JP3 to VCC/2. When doing so,keep in mind that this input also has a 5-kΩ pull-up resistorattached to this signal.

The ENN (Enable Next Parallel Data) and ENA (Enable Par-allel Data) inputs are normally used to specify when valid datais present on the transmit data bus. Both of these inputs aresampled on the rising edge of CKW at the same time as the10-bit transmit data bus.

If ENA is LOW and ENN is HIGH at the rising edge of CKW,the data present on the transmit data bus is loaded, pro-cessed, and sent to the shifter. If both ENA and ENN areHIGH at the rising edge of CKW, the latched data is ignoredand a K28.5 SYNC code is sent in its place.

If ENN is LOW and ENA is HIGH at the rising edge of CKW,the data present on the transmit data bus at the next risingedge of CKW is loaded, processed, and sent to the shifter. Ifboth ENN and ENA are HIGH at the rising edge of CKW, the

data latched on the next rising edge of CKW is ignored and aK28.5 SYNC code is sent in its place.

These two enable control signals are used to allow differenthardware interfaces to be implemented with the least amount(usually none) of additional data pipelining hardware. Whenone of these enable inputs is used for enable control, the oth-er is usually tied HIGH, but may be used in conjunction withBISTEN for link testing without affecting the data path control-ler.

Transmitter Clocks

The transmitter interface operates with both an Input Clock(CKW) and an Output Clock (RP). The input clock is used togenerate both the internal shifter clock and the output clock.

The CKW input clock can be sourced from either the on-boardoscillator or from the XMITCLOCK signal. This selection ismade through jumper block JP1.

All internal operations of the HOTLink Transmitter are basedon the rising edge of the CKW clock. The CKW clock must begenerated from a crystal-based source. While the duty cycleof the CKW clock source is relatively unimportant, it must stillmeet certain minimum pulsewidth times as listed in theCY7B923/CY7B933 data sheet.

The RP output clock pulse is a modified duty cycle pulsewhose HIGH and LOW components are set for operation withasynchronous FIFOs (CY7C42X family). The phase relation-ship of this clock pulse to CKW, and its duty cycle (both setby the internal PLL), are positioned to have valid data on thetransmit data bus at the rising edge of CKW.

This RP clock pulse may be directly connected to the readcontrol pin (R) of an attached FIFO. Because the presence ofthis pulse signifies a FIFO read operation, it is only generatedin response to the ENA input being pulled LOW.

Transmitter to Optical Module Serial Interface

The transmitter has three differential output pairs that eachoutput the same serial data stream from the shifter. Becauseof the switching speeds used for these serial outputs (and forcompatibility with optical interface modules) they are all im-plemented using positive-referenced 100K ECL-compatibledrivers. A simplified schematic of the interface present on theCY9266–F and CY9266–P is shown in Figure 8.

The normal mode of ECL operation is for all signaling to bedone at voltages below ground. Because the ground point forECL is only a reference, the same signaling can also be im-plemented above ground. When this is done the referencepoint changes from ground to VCC. When operated in thismode ECL is often referred to as PECL (positive-ECL). Thisis the mode of operation for the serial outputs on the transmit-ter.

Two of the differential outputs (OUTA± and OUTB±) are alsocontrolled by a TTL-level enable pin called FOTO (Fiber-OpticTransmitter-Off). This control input is used to disable all lightoutput from the optical module. While not specifically neces-sary for LED-based optical modules, the ability to disable alllight output is a safety requirement for all laser-based links(ANSI Z136.1 and Z136.2, F.D.A. regulation 21 CFR sub-chapter J, and IEC 825). When FOTO is HIGH, the OUTA±and OUTB± differential pairs are forced to a logic 0 state(OUT+ is LOW and OUT– is HIGH). When FOTO is LOW, the


16

OUTA± and OUTB± differential outputs are allowed to followthe serial data pattern from the shifter.

The FOTO pin on the HOTLink Transmitter may be configuredto be controlled from either the JP2, JP3, or JP4 connectors(LINK_CONTROL) or from S1-8 (DIP_FOTO). To avoid pos-sible signal contention from these sources, this signal is firstrun through jumper block JP1.

Placing a shorting jumper across the X and Y pins of JP1-Fallows the transmitter FOTO pin to be controlled from theLINK_CONTROL signal. Moving this jumper to JP1-E allowsthis selection to be made through S1-8 or through theDIP_FOTO signal on JP2 and JP3. If the jumper is omittedfrom the board, the OUTA± and OUTB± outputs are placed inthe disabled state.

The OUTC± differential output is not controlled by FOTO. Thisoutput continues to follow the serial shifter data at all times.Because it is never disabled, this signal is used for the localloopback. While this signal is available differentially, it is con-nected to the receiver single-ended. This allows the INB– in-put on the receiver to be used as an ECL-to-TTL translator forthe receive optical module’s signal-detect signal.

Because ECL signals are only active in one direction, it isnecessary to provide a bias/load network of some type for thesignals to properly switch. The typically specified load for ECLsignals is 50Ω connected to VCC – 2V (i.e., +3V for PECL).

This type of load can be created in many ways. For large ECLsystems a separate power supply is usually present to gen-erate this bias voltage. This provides the lowest power dissi-pation. For small systems (like this one), a simpler method isto use two resistors to create a network whose Théveninequivalent is this same 50Ω connected to VCC – 2V. This isused for the OUTA± differential pair. The capacitor presentacross the Thévenin pair is necessary to produce an AC shortbetween the power and ground planes.

The OUTB± output pair is not used on this evaluation board.While normal ECL drivers left in this mode would still dissipatea significant amount of power, the HOTLink ECL outputs con-tain additional internal structures to sense if an output is usedor left open, and disables the internal current sources of un-used output drivers. This results in a current savings of ap-proximately 5 mA (25 mW) for each unused output pair.

The OUTC± output pair is biased to VCC – 5V (ground)through 270Ω resistors. This bias arrangement is used hereto reduce the overall component count. This type of load maybe used for short connections because it provides a similarcurrent load to a Thévenin termination but, due to asymmetricrise and fall times, it induces more jitter into the data. This typeof biasing should not be considered as a type of line termina-tion. If the switching speeds and length of circuit traces dictatethat the line should be terminated, a Thévenin bias networkshould be used to match the line impedance.

Even in those cases where the connection to the optical mod-ules is short and a 270Ω resistor to VCC – 5V may seem to beusable, it should not be used. While this type of connectionmay work for very short optical cable lengths, the jitter intro-duced by the bias network reduces the overall system jittermargin.

Transmitter to Copper Cable Serial Interface

On the CY9266–C and CY9266–T boards, the transmitteroutput is configured to drive either a coaxial or shielded-paircable. A simplified schematic of this interface is shown inFigure 9.

The copper-based CY9266–C and CY9266–T boards use atransformer-coupled interface. Transformer coupling is sup-ported in the ANSI Fibre Channel standard for copper-basedinterfaces. Its primary advantages are excellent commonmode rejection, balanced-to-unbalanced conversion (for co-axial cables), and DC isolation (up to 2 kV hi-pot tested).

The CY9266–C and CY9266–T boards are designed to allowother modes of line biasing and coupling to be used for pre-

Figure 8. HOTLink Transmitter-to-Optical Serial Interface

Figure 9. HOTLink Transmitter to Copper Serial Interface


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senting a signal into the cable. Pads are present on the boardto allow a Thévenin bias to be used on OUTA±. These resistorlocations are identified as R72 and R73 on Sheet 4 of theCY9266–C/T schematic (see Appendix B).

The CY9266–C and CY9266–T are designed to operate withcable systems providing a reflection coefficient of zero. Thismeans that the receiving end of the cable should be terminat-ed in the characteristic impedance of the cable.

Pads are also present to allow both source termination andcapacitive coupling to the transformer. These componentsare identified as R54, R55, C25, and C26 on Sheet 4 of theCY9266–C/T schematic (see Appendix B). To use parts inthese locations it is necessary to remove the foil shorts acrossthe pads for these components on the circuit board.

The control signal inputs for copper-based interfaces operateidentically to those of the optical interface. The difference inoperation is that when the OUTA± outputs are disabledthrough the use of the FOTO signal, instead of disabling alllight, all output transitions are disabled.

Optical Module to Receiver Serial Interface

The HOTLink Receiver has two differential input pairs (INA±and INB±) that can both be used to receive the high-speedserial data streams generated directly by the transmitter or asoutput from an optical receiver. These serial inputs are alsoPECL and are directly compatible with the HOTLink Transmit-ter. ECL was chosen for these signals for the same reasons(speed, low noise, compatibility with optical modules) it wasused for the transmitter.

A separate PECL input signal (A/B) is used to select whichinput pair (INA± or INB±) is actually fed to the receiver shifterand PLL. A simplified schematic of the optical module-to-re-ceiver serial interface on the CY9266–F/P is shown in Figure10.

Optical Module Signals

The optical receiver generates two signals; a 100K PECL dif-ferential received data signal, and a single-endedsignal-detect signal. While the DIP package form of the opti-cal module does provide both + and – forms of the signal-de-tect signal, only the + form is available on the endfire package.To allow the same circuitry to be used with either module type,only the + signal-detect signal is used.

Receiver Data Inputs

The HOTLink Receiver differential INA and INB inputs aresimilar, but not identical. While the INA± inputs must alwaysoperate as a differential pair, the INB± signals do not. Thisallows the INB± inputs to be split into two separate ECL in-puts: INB+, which feeds the shifter and PLL, and INB–, whichfeeds an ECL-to-TTL translator.

The configuration of the INB± inputs is controlled by the SOoutput of the translator. While technically an output, the SOpin on the HOTLink Receiver also contains sense circuits thatmonitor the voltage level on the pin during power-up. If the SOoutput is connected to VCC, the INB– input becomes part ofthe INB± differential serial input. If the SO output is normallyloaded (no resistive pull-up to VCC), the INB+ input becomesa single-ended serial data receiver and the INB– input be-comes part of a PECL-to-TTL translator.

This split mode is used on the CY9266 Evaluation Board. Itallows the INB– input to be used to convert the PECL sig-

nal-detect output of the optical module (SIGO) to the TTL-lev-el signal needed on the receiver parallel interface.

Receiver Port Select

The HOTLink Receiver uses a single-ended PECL input (A/B)to control which serial input is fed to the shifter and PLL. Whenthe A/B input is HIGH, the differential INA± pair is connectedto the shifter and PLL. When the A/B input is LOW, the INB+input is fed to the shifter and PLL. Because the INB+ input isdirectly connected to the OUTC+ output from the HOTLinkTransmitter, this LOW setting is used for a local loopback andallows the transmitter and receiver to communicate withoutusing an optical module.

The A/B input is a PECL input and normal TTL or CMOS logicswings will not work to control it. This input uses PECL (orlarger) signal swings. These can still be achieved in a TTLenvironment through use of a resistive divider network asshown in Figure 10.

Using this network, a TTL LOW level on the input to the dividercreates a PECL LOW at the A/B input to the receiver. With aTTL (or CMOS) HIGH into the divider, the A/B input is placedat (or above) a PECL HIGH. While standard 100K ECL inputsshould never be taken above VCC – 700 mV, the ECL inputson the HOTLink Receiver may be connected directly to VCCwithout degradation or damage.

The divider network on this evaluation board may be config-ured to be controlled from either the JP4 connector(LOOP_BACK) or from S1-7 (DIP_RCVA/B). To avoid possi-ble signal contention from these sources the signal is first runthrough jumper block JP1.

Figure 10. Optical-to-HOTLink Receiver Serial Interface


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Placing a shorting jumper across the X and Y pins of JP1-Ballows the receiver port selection to be controlled from theLOOP_BACK signal. Moving this jumper to JP1-C allows thisselection to be made through S1-7 or through theDIP_RCVA/B signal on JP2 and JP3. If the jumper is left offthe board, the A± pair is selected.

Copper to Receiver Serial Interface

The CY9266–C and CY9266–T Evaluation Boards replacethe optical module with a transformer-coupled electrical inter-face. The transformer used here provides the same function-ality as the one used at the transmit end of the cable. A sim-plified schematic of the copper-cable-to-receiver serialinterface on the CY9266–C/T is shown in Figure 11.

The output side of the transformer connects to two resistors.These resistors provide the line termination for the transmis-sion line connected to the transformer. Two resistors are usedfor the termination network to allow a reference voltage to beset for the center of the received signal. This reference pointis set by an external three-resistor divider, and is set in thiscircuit to VCC – 1.3V. This is near the center of the commonmode range of the MC10H116 ECL receiver that is used tobuild a signal detection circuit. If this signal-detect circuit isnot used, it would be better to bias this point at VCC – 1.5V,the center of the HOTLink Receiver’s common mode range.

Both of these reference points must be bypassed to allowthem to remain stable under dynamic signal conditions.

Unlike the optical receiver, which outputs a logic zero in theabsence of light (INA+ = 0, INA– = 1), the AC-coupled inter-face used for copper connections does not. When the signalis removed, the INA+ and INA– inputs to the HOTLink Receiv-er are set to the same voltage. Because of the high gainpresent in the HOTLink Receiver to allow use with long cables(low amplitude received data), the HOTLink Receiver willprobably oscillate. This oscillation under a no-signal conditioncan be corrected by forcing a small offset between the INA+

and INA– inputs, however, this offset will induce more jitterinto the data stream and limit the usable length of a cop-per-based serial link. Rather than compromise operationallength, a signal detection circuit can be added to validate thereceived data (in addition to the validation mechanismspresent in the data itself).

The CY9266–C and CY9266–T boards also contain the padsand routing necessary for implementing an equalizer to allowlonger cables to be used. The function of an equalizer is topresent a frequency selective attenuation to the received sig-nal that brings the amplitude and phase of the frequency com-ponents in that signal into the same amplitude and phase.Because signals transmitted over copper cables are effective-ly run through a high-frequency attenuator, the equalizer usedfor copper cables is a form of low-frequency attenuator(high-pass filter).

The equalizer is implemented in a bridged-H configurationthat is designed for balanced line operation. It is shown onSheet 4 of the CY9266–C schematic in Appendix B and isconstructed using R64, R65, R66, R67, R68, R69, R70, R71,C29, C30, and L1. To implement this equalizer it is necessaryto remove the foil shorts across R64 and R71.

Copper Signal-Detect

The signal-detect circuit used on the CY9266–C andCY9266–T boards is shown in Figure 12. This circuit uses twoECL s agreceivers as level comparators to detect the pres-ence of 1- and 0-level pulses on the incoming signal. The gateconnected to the top side of the transformer (shown in Figure11) detects the presence of received 1 pulses while the gateconnected to the bottom of this transformer detects the pres-ence of received 0 pulses. The input capacitance of thesecomparators is isolated from the actual received signalthrough 100Ω resistors to prevent this additional load fromdistorting the received signal.

The input signal amplitude necessary to detect either a 1 ora 0 is set by the three-resistor divider shown in Figure 11. Toprevent the 10H116 gate from oscillating it is recommendedthat this threshold be set to a minimum of 50 mV above thetermination reference voltage.

The outputs of these two gates are then wire-ORed togetherto charge a capacitor. Because of the low on resistance of the

Figure 11. Copper-to-HOTLink Receiver Serial Interface

Figure 12. Copper Interface Signal-Detect


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emitter follower output transistors of the 10H116 gates, thecapacitor can be charged quite quickly. In the absence of 1 or0 transitions above the set threshold level, this capacitor isdischarged both by a bleeder resistor to VEE, and through theinput of the third gate.

The third gate is configured as a comparator with feedback toform a Schmitt trigger. This feedback is necessary becauseof the slow transition rate of the input signal to this gate. Iffeedback was not used, this gate would oscillate as the inputsignal slowly passes through the threshold region of the gate.The output of this Schmitt trigger is then connected to theHOTLink Receiver INB– input, which is configured as aPECL-to-TTL translator.

Receiver Parallel Interface

The receiver parallel interface is used to move the characterframed in the HOTLink Receiver to the external world whereit can be used. This portion of the design consists of five sec-tions: receiver parallel data output, OLC-compatibility regis-ters, receiver clocks, receiver control inputs, and receiver sta-tus outputs. A simplified schematic of this interface is shownin Figure 13.

Receiver Parallel Data Output

The receiver data bus is composed of ten signals namedREC_0 through REC_9. This bus drives all three I/O connec-tors (JP2, JP3, and JP4). Due to the external register in thedata path, these outputs change coincidental with the risingedge of RCV_CLK0 (CKR).

The information placed on the receiver data bus is deter-mined by the HOTLink Receiver MODE select pin. WhenMODE is HIGH (Bypass mode), all ten outputs are the ten bitsthat were received and framed. The letter form (Qa–Qj, asshown in Figure 13) of the bit identifiers is followed for thissetting. These designators specify which encoded data bit isconnected to a specific REC_0 to REC_9 signal. In this modethe user must decode the data from the 10-bit patterns usedto send the data across the serial interface.

While it is not necessary to use the 8B/10B code describedin the HOTLink data sheet, it is advised that this code be usedfor simplicity. If another code is used, it is the user’s respon-sibility to insure that sufficient transitions are present in the

data stream to allow the HOTLink Receiver to properlyphase-lock to the serial data stream.

For the HOTLink Receiver to maintain character framing andsynchronization, the K28.5 pattern must also be used forframing initialization. For those systems that perform theirown framing (SONET, SMPTE, etc.), the HOTLink Receiverwill phase-lock to a serial data stream without K28.5 codespresent and clock out a character every 10 bit-clocks. Thesesystems must operate in Bypass mode as the HOTLink Re-ceiver decoder requires operation with the 8B/10B code andmust acquire character sync to recover valid data. These sys-tems must provide external character framing.

When the HOTLink Receiver MODE input is LOW, the internal10B/8B decoder is enabled. In this mode, the ten output bitsfrom the shifter are sent to the decode register once every tenbit-clocks, as determined by the framer. The 8-bit output fromthis decoder is then placed on the receiver output data busbits Q0–Q7, along with the two data status bits SC/D andRVS.

When receiving normal data patterns, both the RVS andSC/D pins are LOW. In this setting, the 8-bit data characterpresent on Q0–Q7 is latched at the rising edge of CKR intothe external register and presented to the output of the board.

The two status bits, SC/D (special character/data select) andRVS (received violation symbol), are used to indicate recep-tion of characters other than those used to represent data.When the SC/D output is HIGH, special control codes (seelisting in the CY7B923/CY7B933 data sheet) have been de-coded. These control codes are used to indicate framing, con-trol, status, and other supervisory functions across the inter-face.

The RVS pin is used for diagnostic purposes. When this out-put is HIGH, the HOTLink Receiver decoder has detected a10-bit pattern that is not a valid 8B/10B transmission charac-ter or sequence. When the receiver detects this encoding vi-olation, it asserts RVS and places information on the Q0–Q7outputs to represent the type of error detected. Because all ofthese errors are represented with special codes (C0.7, C1.7,C2.7, and C4.7) the SC/D output is always HIGH wheneverRVS is HIGH. These possible error-type codes are listed inthe HOTLink datasheet.

OLC-Compatibility Registers

In order for this evaluation board to operate in an OLC-266compatible system, the timing of the RDY signal has to bemodified. This signal from the receiver is used for four func-tions: to indicate when a K28.5 SYNC character has beenreceived, to indicate that valid data has been received, toclock valid data into an external asynchronous FIFO, and toindicate the end of a BIST loop.

To support these different functions from a single pin requiresthe addition of a single register to convert the waveform gen-erated by the RDY signal into the BYTE_SYNC status signalthe OLC card generates. Additional registers were then add-ed to the data bits to keep them in the same character-phaserelationship as the BYTE_SYNC signal (which is now delayedone clock).

Note: The CY7B9331 HOTLink receiver (rather than theCY7B933 receiver used on the CY9266 Evaluation board) isnormally used in systems requiring OLC-266 compatibility.This special HOTLink receiver provides alternate timings and

Figure 13. HOTLink Receiver Parallel Interface


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logic levels for those signals that are different from the defaultsignals on an OLC compatible interface. This allows an OLCinterface to be implemented without additional registers orinverters.

The 22Ω series termination present on these signals shouldnot be necessary for most systems, but are added here toallow a flat-cable-type attachment to this card.

Figure 14 shows the relative timing relationships between theHOTLink Receiver data, the RDY signal, the BYTE_SYNCsignal, and the output clocks. For RDY to operate in this fash-ion, the RF (Reframe enable) control input must be HIGH andthe receiver must be in Bypass mode (receiver MODE isHIGH).

When RF is LOW, the RDY and BYTE_SYNC outputs operatethe same as that shown in Figure 14. The difference is thatthe clocks are not allowed to change phase or width upondetection of a K28.5 SYNC character.

The functionality of the RDY (and thus BYTE_SYNC) signalchanges when the receiver is in Decode mode (receiverMODE is LOW). Here the RDY signal pulses LOW for everycharacter received including the K28.5 SYNC character.When multiple consecutive SYNC characters are received,RDY is inhibited except for the last K28.5 character received.This is done to prevent overfilling a receiver FIFO withnon-data information. Figure 15 shows the relative timing re-lationships for this type of operation.

Because RF is LOW in Figure 15, the CKR clock (and thusRCV_CLK0 and RCV_CLK1) is not allowed to reframe on

new K28.5 SYNC characters detected. When RF is HIGH inDecode mode, the HOTLink Receiver RDY output ceasespulsing until the first K28.5 SYNC code is detected, afterwhich the behavior shown in Figure 15 is resumed.

Receiver Clocks

The HOTLink Receiver parallel interface (see Figure 13) op-erates with a single input clock (REFCLK) and two outputclocks (CKR and RDY).

The REFCLK input clock does not directly clock anything inthe receiver, but is used as a reference for the receiver PLL.This clock is required to be both stable and reasonably accu-rate. It must match the character-rate frequency of the re-ceived data within ±0.1%. Unlike an OLC card, which requiresa special sequencing of the LOCK_TO_REF signal to allowthe receiver to track to a reference clock, the HOTLink Receiv-er PLL continuously operates in a mode that compares itsfrequency to that of the reference clock, even when valid datais being received.

If the frequency of the received data varies outside of specificfixed limits, the HOTLink Receiver stops locking to the serialdata and reverts to the REFCLK. Once the received serialdata stream returns to an acceptable frequency, the PLLagain locks to the received data. Since it is likely that charac-ter sync has been lost, a reframe cycle should be performedto allow the framer to lock up again. Detection of this and therecovery process is normally handled automatically by high-er-level functions in the communications system.

The REFCLK input to the receiver can be sourced from threedifferent signals on the evaluation board: the on-board oscil-lator, the XMITCLOCK input, or the EXTREFCLK input. Se-lection of the clock source can only be done through jumperblock JP1.

The on-board oscillator is used primarily for standalone oper-ation and testing using the BIST capabilities of the HOTLinkparts. This clock is selected by placing a shorting jumperacross pins X and Y of JP1-I.

The XMITCLOCK input is used for normal data transmit/re-ceive functions and for OLC-compatibility mode. This clock isselected by placing a shorting jumper across pins JP1-HXand JP1-IX.

The EXTREFCLK input is used for those instances when thetransmitter and receiver are to be clocked with different fre-quency clocks. This is expected to be used only to test for PLLcapture/lock range testing of the receiver, or when theHOTLink Receiver is connected to a transmitter operating ata different frequency from the local HOTLink Transmitter. Thisclock is selected by placing a shorting jumper across pinsJP1-JX and JP1-IX.

The CKR output clock is generated in the HOTLink Receiverand is based directly on the internal PLL frequency. This out-put is synchronous with the receiver output data bus and maybe used to clock the data into an associated register (as isdone on this board) or into synchronous FIFOs.

The period and duty cycle of the CKR output clock are fixedby the logic in the receiver. To achieve compatibility withOLC-type systems, the CKR signal is used to generate twonew clock signals (RCV_CLK0 and RCV_CLK1) that are trueand complement copies of the CKR clock. To keep matcheddelays and to minimize the number of additional logic pack-

Figure 14. Receiver Data Timing, Bypass Mode, RF HIGH

Figure 15. Receiver Data Timing, Decode Mode, RF LOW


21

ages on the board, these two clocks are generated usingXOR gates.

When framing occurs, the CKR clock can experience largephase changes. These changes are exhibited by a lengthen-ing of either the HIGH or LOW portion of the CKR waveform.This can be seen in the waveforms shown in Figure 14. Whilethis functionality is not required by the ANSI Fibre ChannelStandard, it is included in the HOTLink Receiver to protectdownstream clocked logic from the narrow pulses or glitchesthat can occur otherwise.

The RDY output signal is used both as a status output and asa clock. Its use as a clock is primarily for clocking data presenton the receiver data bus outputs into asynchronous FIFOs.The duty cycle of the RDY pulse and its position relative to theoutput data is such that it may be directly connected to the W(write) input on CY7C42X FIFOs.

Receiver Control Inputs

The receiver parallel interface is controlled by three input sig-nals: RF (Reframe), MODE (Receiver Mode select), andBISTEN (BIST Enable).

The RF input is used to select when the HOTLink Receiver isallowed to reframe (acquire character-sync) to the incomingserial data stream. This input is present to prevent the receiv-er from mis-framing on aliased K28.5 SYNC codes, whichwould cause long running decode errors.

When RF is LOW the framer is disabled; it does not changethe starting bit location of each received character. Any re-ceived K28.5 SYNC code is treated as normal data and isclocked out with the CKR and RDY clocks. If this SYNC codeis received across two character boundaries, the framer doesnot reframe. If the HOTLink Receiver is operating in Decodemode, the existence of such a non-aligned pattern may gen-erate one or more characters in error.

When RF rises, the RDY output is inhibited. With RF heldHIGH, the framer continuously monitors the serial datastream for either disparity form of the K28.5 SYNC character.When this character is detected, the bit counter used to countoff serial data bits and specify received character boundariesis asynchronously reset to properly frame the subsequentlyreceived bits on character boundaries.

If the receiver is set to Decode mode, the RDY output as-sumes its normal function of pulsing LOW for each characterafter the first K28.5 SYNC code is detected. If the receiver isinstead set to Bypass mode, the RDY signal pulses LOW onlyfor the SYNC (K28.5) characters while RF is HIGH or LOW.

Because of characteristics of the 8B/10B code, it is possibleto transmit legal character sequences that can cause incor-rect framing (this requires sending control codes other thanK28.5). These codes should be avoided while RF is HIGH.Once the framer is disabled (RF LOW) these sequences maybe used to pass control information across the interface with-out causing the receiver to incorrectly frame the data that fol-lows.

The MODE input pin on the HOTLink Receiver is used to se-lect both how the received serial data is to be presented onthe data bus (encoded 10-bit character or decoded 8-bit char-acter), and to place the receiver into a clock Test mode. Thisinput is capable of selecting one of these three possiblemodes from a single pin through use of an internal three-levelcomparator.

When the MODE input is LOW, the internal 10B/8B decoderis enabled (Decode mode). This allows the receiver outputdata bus to be interpreted as an 8-bit data bus (Q0–Q7) withtwo status bits (SC/D and RVS). When the MODE input isHIGH, the internal decoder is bypassed (Bypass mode). Thisallows the data bus to be interpreted as a 10-bit bus (Qa–Qj).Either of these modes may be set from JP2, JP3, or S1-6.

The clock Test mode is accessed by allowing the MODE inputpin to float. Through use of an internal bias network in thereceiver, the MODE input pin is placed at VCC/2. This clockTest mode can be accessed two ways on the board. The eas-iest is to cut the foil on the bottom of the board that shorts theX and Y pins of JP1-A together. Following this, it will be nec-essary to place a shorting jumper across these pins to allowJP2, JP3, or S1-6 to place the receiver into one of its normaldata modes.

The other method of accessing this mode is to actively biasthe RCV_MODE pin on JP2 or JP3 to VCC/2. When doing so,keep in mind that this input also has a 5-kΩ pull-up resistorattached to the signal.

The BISTEN input pin is used to place the HOTLink Receiverin a special pattern verification mode. This mode is designedto work in conjunction with a matching pattern generationmode in the transmitter. While not shown on the schematic inFigure 13, the BISTEN input is actually run through the BISTPLD (U8-CY7C344). This is not necessary but is done hereto allow other conditioning of the BISTEN signal if desired.

When the HOTLink Receiver BISTEN input is set LOW, thereceiver’s BIST state machine is enabled and enters itsself-test mode. At this point it sets RDY HIGH and beginslooking for the BIST start-of-loop character (D0.0) in the serialdata stream. Once this character is detected, the RDY outputis driven LOW, where it remains until the end of the 511-char-acter BIST loop. At this point RDY pulses HIGH for one char-acter and starts the next 511-character loop.

While BIST mode is enabled, the RVS output is used to indi-cate that a pattern mismatch has occurred. This means thatthe 10-bit pattern received did not exactly match the 10-bitpattern that was expected (expected code violations are noterrors).

Receiver Status Outputs

The HOTLink Receiver parallel interface generates two statusoutput signals: RDY and SO.

The RDY output is used both for status information and as aclock. As a status output, its information is valid at the risingedge of CKR. This means that the RDY signal must be regis-tered to present its status information. For normal data trans-fer modes, the registered form of RDY is used to identify thepresence of multiple K28.5 SYNC characters (HIGH at risingedge of CKR) and of data or control characters (LOW at therising edge of CKR). This registered form of RDY generatesthe BYTE_SYNC signal.

The RDY signal is also used to identify what phase theHOTLink Receiver BIST mode is in. When HIGH for two ormore CKR clocks, the receiver is looking for the start charac-ter of the BIST loop. When LOW, the receiver is in the BISTloop. When HIGH for a single clock, the receiver has complet-ed another BIST loop.

The SO output is used as part of an ECL-to-TTL translator tospecify the current state of the signal on the serial interface,


22

and is used to drive the LINK_STATUS signal. When a validsignal is present and S1-9 (CD_POL) is off (open),LINK_STATUS is LOW. This polarity is reversed by turningS1-9 on (closed) or pulling SYNC_POL LOW.

BIST and Support Hardware

The CY9266 Evaluation Board contains not only those com-ponents necessary to form a serial link, but also a few supportcomponents to enhance OLC compatibility and to support theBIST capability in the HOTLink Transmitter and Receiver. Asimplified schematic of these additional components is shownin Figure 16.

The MAX707 is used to monitor the power-supply voltage andremove the RESET signal when VCC is above 4.65V. This isa close approximation to the 4.75V RESET threshold speci-fied for the OLC card. This part also supports an externalmechanical switch input that also controls the RESET output.This input is controlled by the BIST reset push-button switch(S2). When this switch is depressed, the RESET output isdriven LOW until 200 ms after the switch is released. ThisRESET signal is used to clear the BIST error-counter locatedin the BIST PLD (U8). The PWR ON indicator is extinguishedas long as RESET is active.

The BIST PLD is a Cypress CY7C344 MAX EPLD pro-grammed with the counters and state machines necessary tomonitor the status of the receiver outputs and count whenBIST-compare errors are detected. This PLD also drives thedecimal points on the attached displays to indicate four statussignals. These status signals are:

• PWR ON—Lit when power is present and above the 4.65V sense threshold

• CAR DET—Lit when a valid signal is present

• BIST WAIT—Lit when BIST is enabled but the receiver has not detected the start of the BIST loop

• BIST OVFL—Lit when the BIST error count exceeds 99

BIST State Machine

The BIST state machine has six states that control when acounter is enabled to count pattern-match errors. A bubblediagram of this state machine is shown in Figure 17 while theMAX+PLUS source file for this state machine is listed in Ap-pendix C.

This state machine controls when the error counter is enabledto count. It operates off of two input signals: BISTEN and RDY.Whenever BISTEN is not present, the machine is returned to

the WAIT0 state (while all state transition arrows are shownfor these transitions, not all of them are labeled).

Once BISTEN becomes active, the machine goes throughtwo secondary wait states (WAIT1 and WAIT2) before startingto look for RDY being active. These wait states are necessaryto allow the receiver time to recognize the BISTEN signal andbring RDY HIGH.

When the ENABLED state is reached, the machine remainsin this state until RDY goes LOW, causing the machine tomove to the first of the two LOCKED states. This signifies thatthe receiver has received the start-of-loop character (D0.0)and is now performing matching of the received data bits toits internal pattern generator.

In the LOCKED states, the external counter is enabled tocount errors. The reason two LOCKED states are present isto allow for the single pulse on RDY that indicates the end ofa BIST loop. If RDY is ever HIGH for more than one clock, theHOTLink Receiver has determined that it is no longer in syncwith the transmitter and it starts looking for the start-of-loopcharacter again.

Other BIST PLD Functions

The complete schematic for the BIST PLD is shown in Appen-dix C. Other than the BIST state machine, the other main logicfunctions present in the part are for driving the four statusindicators and the actual error counter.

Error Display

The error display is made from two hexadecimal LED displays(TIL311). These displays are each capable of showing theentire hexadecimal character set (0–9, A–F) as well as havingtwo independent decimal points. These decimal points areused as individual status indicators for the board.

External Serial Interface ConnectionsThe primary difference between the CY9266 card types is inthe external high-speed serial interface. Each card type oper-

Figure 16. BIST Support Hardware Figure 17. BIST State Machine Bubble Diagram

BISTEN

WAIT10

WAIT00

WAIT20

ENABLED0

LOCKED21

LOCKED11

BISTEN

BISTEN

BISTEN RDY

RDY RDYRDY

RDY

RDY


23

ates with not only a different media type (optical, coaxial,shielded twisted pair), but also different connectors and cabletypes.

CY9266–F/P Serial Interface Connections

The CY9266–F/P HOTLink Evaluation Boards implement afiber-optic-based serial interface. This interface uses indus-try-standard LASER and LED-based fiber-optic modules thataccept SC-type fiber-optic connectors.

Optical Modules

The CY9266–F/P HOTLink Evaluation Boards are designedto operate using de facto standard-footprint optical modules.Any optical module meeting the pinout and dimensions of thisde facto standard (established originally for FDDI) should op-erate with the CY9266–F/P.

Note: These standard-footprint optical modules are availablein a wide range of operating data rates. Because the operat-ing data rate for some of these modules may be outside the150- to 400-Mbit/second operating range of the HOTLinkTransmitter and Receiver, care should be exercised when se-lecting an optical module.

This footprint supports two types of optical modules: thosewith four rows of vertical pins, and those with a single row ofpins along the bottom edge. In vendor literature these arereferred to as DIP, and 1X9 or endfire-type packages.

While specified originally for FDDI, modules meeting this foot-print are also available for Fibre Channel and ATM data rates.Figure 18 shows the mechanical footprint dimensions of thisde facto standard package.

Both package types operate from a +5V supply and interfacedirectly with 100K ECL/PECL. The biggest mechanical differ-ence between them is that the endfire-type packages havetwo oversized pins (1 and 32) that are used only to hold thepackage in place. The main electrical difference between thepackages types is that the DIP package drives the Signal De-tect output differentially while the endfire package only pro-vides the active HIGH output. Table 5 lists the pinouts for thisstandard-footprint optical module.

The active signals listed in Table 5 are:

• SD—Signal Detect

• TD—Transmit Data

• RD—Receive Data

• Case—Outer Case of Module

• VCC—Positive Supply Voltage

• VEE—Negative Supply Voltage

Pins marked “Case” are not necessarily isolated pins. Be-cause the optical module is used in the CY9266–F/P in aPECL mode, these Case pins are connected to the VEE(ground) supply. When selecting an optical module, careshould be taken to insure that the pins marked “Case” areeither floating or are attached to the appropriate power supplyrail.

To allow evaluation of different types of optical modules, theCY9266–F/P Evaluation Board is built using low-profile sock-et pins for the optical module. This allows the modules to beeasily replaced. In addition, two slotted holes are provided fora cable-tie to hold the module in place.

Figure 18. Optical Module, Top View Dimensions


24

Fiber-Optic Connector

The optical modules specified for use on the CY9266–FHOTLink Evaluation Board (listed in Appendix A, item U4) aredesigned to accept SC-type fiber-optic connectors. Theseconnectors are available in both simplex (single-fiber) and du-plex (dual-fiber) versions. Figure 19 shows a simplex SC fi-ber-optic connector. A duplex connector is formed either byjoining two simplex connectors together with a clip (some-times referred to as a “Z” clip) or by using a connector thatsupports two fibers in the same form factor. The standardoptical fiber type used with these connectors and LED-basedoptical modules is 62.5/125-mm multimode graded-index fi-ber.

When using duplex connector cables, the cable constructioncontrols which fiber is connected to the transmit LED andwhich is connected to the receive photodetector. When usingsimplex cables, this polarization control is left to the user. Thetransmit and receive connectors on the fiber-optic module areshown in Figure 20.

The optical modules specified for use on the CY9266-PHOTLink Evaluation Board (listed in Appendix A, item U4) are

designed to accept Hewlett Packard Versatile Link-type fiber-optic connectors. These connectors are available in both sim-plex (single-fiber) and duplex (dual-fiber) versions. Figure 21shows a simplex Versatile Link fiber-optic connector. A duplexconnector is formed either by joining two simplex connectorhalves together or by using a connector that supports twofibers in the same form factor. The standard optical fiber type

Table 5. Optical Module Pinout

DIP Pin Assignments

Pin Signal Pin Signal

1 Case 2 No Pin

3 Case 4 VEE

5 VEE 6 +SD

7 –SD 8 Case

9 Case 10 –RD

11 +RD 12 VCC

13 VCC 14 VCC

15 Case 16 Case

17 Case 18 Case

19 VCC 20 VCC

21 Case 22 +TD

23 –TD 24 Case

25 Case 26 VBB

27 Case 28 Case

29 VEE 30 VEE

31 No Pin 32 Case

1X9 (Endfire) Pin Assignments

Pin Signal Pin Signal

33 VEE 34 +RD

35 –RD 36 +SD

37 VCC 38 VCC

39 –TD 40 +TD

41 VEE

Figure 19. SC Simplex Fiber-Optic Connector

Figure 20. U4 Fiber-Optic Module Connectors

Figure 21. Versatile Link Plastic Optical Fiber Connector

TransmitConnector

ReceiveConnector


25

used with these connectors and LED-based optical modulesis 1-mm multimode step-index plastic fiber.

Versatile Link connectors offer no specific form of polariza-tion. When used with simplex or duplex connectored cables,polarization control is left to the user. The transmit and receiveVersatile Link connectors on the fiber-optic module are shownin Figure 22.

CY9266–C Serial Interface Connections

The CY9266–C HOTLink Evaluation Board implements acopper-based serial interface. This interface uses 75Ω coax-ial cables having BNC- and TNC-type connectors.

Coaxial Board Connectors

The CY9266–C HOTLink Evaluation Board has two right-an-gle female coaxial cable connectors: a BNC (BayonetNeil-Councilman) for the J1 transmit connector, and a TNC(Threaded Neil-Councilman) as the J2 receive connector.These connectors and their location on the board are shownin Figure 23.

Coaxial Cable Connectors

Many different coaxial cables may be used with theCY9266–C HOTLink Evaluation Board. The only require-ments for the cable are 75Ω characteristic impedance andBNC/TNC connectors at each end to attach to the board. Oth-

er cable impedances may also be used, however, the termi-nation (R40 and R41) and bias (R61 and R62) resistors onthe board must then be changed for correct operation.

Coaxial cables for the CY9266–C should have a BNC con-nector on one end and a TNC connector on the other. Thisdual-connector mechanism is specified by ANSI to preventthe inadvertent cabling of a transmitter to another transmitter,or a receiver to another receiver. When connecting cables toa CY9266–C board, the cable BNC connector always attach-es to a transmit port (J1) and the cable TNC connector alwaysattaches to a receiver port (J2). TNC/BNC dual-female barrelconnectors (e.g., Amphenol #76400) are available to allowsplicing of cables to evaluate multiple lengths of cable. Figure24 illustrates typical TNC and BNC connectors.

CY9266–T Serial Interface Connections

The CY9266–T HOTLink Evaluation Board implements acopper-based serial interface. This interface uses 150Ωshielded twisted-pair (STP) cables with 9-pin male D-submin-iature-type connectors.

STP Board Connectors

The CY9266–T HOTLink Evaluation Board has a right-anglefemale 9-pin D-subminiature connector. Unlike the coaxial ca-ble version of the CY9266, which uses separate connectorsfor transmit and receive, the CY9266–T uses only a singleconnector (P1) for both. This connector and its location on theboard is shown in Figure 25.

Figure 22. Versatile Link Board Connectors

Figure 23. J1 and J2 Coaxial Board Connectors

TransmitConnectorJ1 (BNC)

ReceiveConnectorJ2 (TNC)

Figure 24. TNC/BNC Cable Connectors

Figure 25. STP P1 Board Connector

ThreadedNeil–CouncilmanConnector (TNC)

BayonetNeil–CouncilmanConnector (BNC)

Pins 1 and 6Transmit Data

Pins 5 and 9Receive Data


26

STP Cable Connector

There are presently two STP cable types identified by ANSIfor use with Fibre Channel; both specify 150Ω differentialcharacteristic impedance. These cable types are known aseither EIA/TIA568 Type-1 and Type-2, or more generically asIBM Type-1 or Type-2. Both of these cable types contain twoindividually shielded pairs of solid conductors. The Type-2 ca-ble also contains four non-shielded conductors that are oftenused for either low-speed signaling or voice-grade communi-cations. The CY9266–T also accepts the twinax cable speci-fied for Fibre Channel interfaces, when terminated in style-19-pin connectors.

For installations where the cables may see more flexing, astranded conductor cable is available that meets the 150Ωimpedance. This cable type is commonly known as IBM®Type-6. Other cable types may also be used with theCY9266–T HOTLink Evaluation Board. The only require-ments for the cable are 150Ω differential characteristic imped-ance and a properly wired (see Figure 27) 9-pin male D-sub-miniature connector at each end of the cable. Other cableimpedances may also be used, however, the termination (R40and R41) and bias (R61 and R62) resistors on the board mustthen be changed for correct operation.

Figure 26 shows an example of a compatible STP cable con-nector and how the pins in the connector are numbered. Thisis a 9-pin male D-subminiature connector. While connectorsof this type are available with a plastic housing, proper oper-ation with STP cables requires using connectors having ametal or conductive shell. When properly connected, asshown in Figure 27, the shield of each pair in the cable isattached to the conductive front shell of the connector. Tomaintain shielding effectiveness it is recommended that theconnector backshell/strain relief also be metallic or conduc-tive.

The STP cable is wired in a crossover fashion where thetransmit connections at one end of the cable are connectedto the receive connections at the other end of the cable, asshown in Figure 27. The cable shields for both pairs are tiedtogether and connected to the D-sub shell at each end.

OLC Mode ConfigurationThe CY9266 Evaluation Board may be configured to operatein an OLC-266 compatible system. This emulation is strictlyat the TTL parallel interface level; the optical and electricalserial interfaces are not compatible. In addition, the CY9266

is only a single-channel board while the OLC-266 is availablein either single- or dual-channel versions.

The TTL parallel interface attachment is provided through theJP4 connector. This connector is pinned and positioned tomate with host systems designed for the OLC-266 board.

The following configuration sets the CY9266 for 10-bit dataand Bypass mode on both the transmitter and receiver. Thetransmitter and receiver are both clocked by the XMITCLOCKsignal on JP4, and the receiver A/B selection is controlled bythe LOOP_BACK signal on JP4.

JP1 Settings

The CY9266 jumper block JP1 controls many of the optionson the board. For the CY9266 to operate in an OLC socket,jumper block JP1 must be configured with shorting jumpersas shown in Figure 28.

The shorting jumper across pins X and Y of JP1-B allows theLOOP_BACK signal in the JP4 connector to control the A/Binput selection on the HOTLink Receiver. The jumper acrosspins X and Y of JP1-F allows the LINK_CONTROL signal tocontrol the FOTO enable of the HOTLink Transmitter. Thejumper connecting pins X and Y of JP1-G connects theXMITCLOCK input to the HOTLink Transmitter CKW clock.The jumper connecting pins JP1-HX to JP1-IX connects theXMITCLOCK input to the HOTLink Receiver REFCLK input.

Note : The active signal level of the LOOPBACK signal, asimplemented on the CY9266, is opposite that of an actualOLC-266 card. If this signal is under software control, itshould be programmed to allow signal loopback when thesignal is active LOW. For hardware controlled systems an ex-

Figure 26. STP Cable Connector and Connector Pinout

59

48

37

26

1

Figure 27. STP Cable Connectors

Figure 28. JP1 OLC-Compatibility Settings

+XMIT 1-XMIT 6

+RCVR 5-RCVR 9

SHELL

1 +XMIT6 -XMIT

5 +RCVR9 -RCVR

SHELLCable Shield

JP1ABCDEFGHIJ

X Y

RCV_A/B - - L OOPBACK

ENLFOTO -

XMITCLOCK -

- LINK_CONTROL

- CK W

XMITCLOCK -

REFCLK -


27

ternal signal inversion is necessary, or the signal may be jum-pered at JP1 for operation from the S1-7 DIP switch.

S1 Settings

The S1 DIP switch is also used to configure many of theHOTLink Transmitter and Receiver options. The settings forthese switches are listed in Table 6.

The setting of switches S1-7 and S1-8 are not applicablewhen jumpers JP1-B and JP1-F are in place.

Assembly and OptionsThe design of the CY9266–F/P and CY9266–C/T EvaluationBoards offer many different assembly options for those usersinterested in making modifications for their own evaluation.

Optical Module

Optical module U4 on the CY9266–F/P is socketed for userevaluation of different optical modules. The hole pattern onthe board supports direct soldering of the optical module tothe board. This should not be attempted on a board that isalready equipped with a socket for the module because re-moval of the socket pins may damage the board.

Transmitter

The HOTLink Transmitter B± differential output signals on theboard are left open to conserve power. Pads are present onthe bottom of the board (labeled R1, R2, R3, and R4) forbias/termination resistors for these outputs. While these re-sistors are present on the board schematic, they are not partof the delivered assembly. If the B± outputs are used for prob-ing or test purposes, resistors must be added in these loca-tions to enable the output drivers.

Oscillator

The on-board oscillator (U5) is used primarily for exercisingthe BIST capability of the board in a standalone mode. If theboard is only used with an external clock, the oscillator doesnot need to be present. This part is socketed to allow the userto select the operating frequency.

When selecting an oscillator, care must be taken to insure thefrequency stability and jitter characteristics of the oscillator

are within the specifications of the HOTLink Receiver andTransmitter and the intended system application.

The hole pattern on the board supports direct soldering of theoscillator to the board. This should not be attempted on aboard that is already equipped with a socket for the oscillator,as removal of the socket pins may damage the board.

BIST Support Hardware

The BIST support hardware does not interact with the func-tionality of the HOTLink Transmitter or Receiver and is notpart of the communications link. If there is no requirement forBIST and display hardware, the following components may beremoved from the board:

• U6 and U7—TIL311 Hex Displays

• U8—CY7C344 EPLD

• S2—Reset Switch

• R21, R22, R23, and R24—1 kΩ• C13—0.022 µF

• C18—100 pF

Voltage Monitor

The voltage monitor (U11) is used as part of the BIST functionand also drives the RESET signal on JP2, JP3, and JP4. Ifmonitoring of the specific voltage is not necessary (and BISTcapability is not used) this part may be removed.

If U11 is removed, it may be necessary to bias the RESETline to allow an external system controller to properly sensea high on the RESET output. This may be done by solderinga jumper wire from pin 7 of U11 to pin 2 of R20.

JP2

The area of the board labeled as JP2 provides a hole patterndesigned to accept multiple types of headers and connectors.These connectors allow access to all the signals present onJP3 and JP4.

The current pin 1 designation for JP2 assumes a pin-headerconnector designed for flat cable is attached to bottom of theboard. If this type of connector is instead attached to the topof the board, the even and odd pins are effectively swappedin the connector and cable, from those listed in Table 1.

OLC-Compatibility Registers

The 74F174 hex D-registers (U9 and U10) are used to pro-vide compatibility with OLC-266 sockets. For those users notrequiring this capability, or for those who wish to use the re-ceiver RDY signal to clock received data into asynchronousFIFOs, these registers can be removed.

Once U9 and U10 are removed, it is necessary to short elev-en adjacent pad pairs on U9 and U10 to allow the receiverdata bus to connect to the output connectors. The pairs thatmust be shorted are listed in Table 7.

Table 6. S1 OLC-Compatibility Settings

DIP Switch Settings

Sw # State Controlled Signal

1 Off Transmitter BIST Enable

2 Off Transmitter Mode Select

3 Off Enable Next Parallel Xmit Data

4 On Enable Parallel Xmit Data

5 Off Receiver BIST Enable

6 Off Receiver Mode Select

7 N/A Switch Controlled Loopback

8 N/A Switch Controlled FOTO

9 Off Signal-Detect Polarity Select

10 Off BYTE_SYNC Polarity Select


28

Copper Cable Connectors

The CY9266–C and CY9266–T are assembled on the samesubstrate and may be configured for use with either coaxial orshielded-pair cables. Changing from coax to shielded-pair re-quires the removal of the J1 BNC and J2 TNC connectors andreplacing them with a female 9-pin D-sub connector at loca-tion P1 (see Appendix B for manufacturer part numbers).Also, the foil traces that connect pins 6 and 9 of P1 to the

shield of J1 and J2 (located on the bottom of the board) mustbe cut. Because the cable impedance used for shielded-paircable is different from that of coax cable, the line terminationresistors R40 and R41 must be replaced with 75Ω resistors,and coupling transformer T1 must also change to the higherinductance type.

Changing from shielded-pair to coax requires removal of theP1 D-sub connector and the addition of connectors J1 and J2.It is necessary to connect pin 6 of the P1 pad set to the shieldpin of J1, and pin 9 of P1 to the shield pin of J2. Because thecable impedance used for coax cable is different from that ofshielded-pair cable, the line termination resistors R40 andR41 must be replaced with 37.4Ω resistors, and couplingtransformer T1 must also change to the lower inductancetype.

Redesign CapabilityThe CY9266–F, CY9266–P, CY9266–C, and CY9266–Tboards were designed strictly as a demonstration vehicle forthe Cypress Semiconductor HOTLink family of communica-tions parts. The designs shown here may not be optimal formost applications, as these are expected to be more special-ized and may not require all the configuration and BIST dem-onstration hardware contained on these boards.

Examination of the evaluation boards will show that the com-ponents necessary for creating a serial link are all on one halfof the board, while the components used for configuration andBIST support are located on the other half of the board. Thisplacement of parts was intentional, and shows that two com-plete channels may be placed on a board of the same size asthe CY9266 without placing active components on both sidesof the board.

HOTLink is a trademark of Cypress Semiconductor.IBM is a registered trademark of International Business Machines.

Table 7. OLC-Compatibility Register BypassConnections

Register Pin Connections

Part Pins Signal Name

U10 14, 15 RCVR_0

U10 12, 13 RCVR_1

U10 10, 11 RCVR_2

U10 6, 7 RCVR_3

U10 4, 5 RCVR_4

U10 2, 3 RCVR_5

U9 10, 11 RCVR_6

U9 12, 13 RCVR_7

U9 14, 15 RCVR_8

U9 6, 7 RCVR_9

U9 4, 5 RDY


29

/

Appendix A. CY9266–F Schematic (Sheet 1 of 5)


30



31



32



33



34

Appendix A. CY9266–F Parts List

Instance Part Number Description

U1 Cypress CY7B923-JC HOTLink Transmitter

U2 Cypress CY7B933-JC HOTLink Receiver

U3 74F86 Quad XOR Gate, SOIC Package

U4 (CY9266–F) AMP/Lytel 269063-1, Hewlett Packard HFBR-5302,Siemens TC-266C2EP,CTS 1408N, or Equivalent

266-MBaud 1300-nm LED Transceiver Module

U4 (CY9266–P) See Cypress application note “Replacing Wire with Inexpensive Plastic Fiber Solutions” for module design and bill of materials

155-MBaud LED Transceiver Module for POF

U5* (CY9266–F) CTS CTX126 or Equivalent 25-MHz TTL Clock Oscillator

U5* (CY9266–P) Cypress ICD6233 QuiXTAL 15.5-MHz TTL Programmable Clock Oscillator

U6*, U7* TI TIL311 Hex Display With Logic

U8* Cypress CY7C344-15HC 32-Macrocell MAX EPLD

U9, U10 74F174 Hex D-Register, SOIC Package

U11* Maxim MAX707CSA or Equivalent Voltage Monitor

D1* 1N4735A 1W, 6.2V Zener Diode

S1* AMP 3-435668-0 or Equivalent 10-position DIP Switch

S2* ECG 520-01-3 or Equivalent Momentary Pushbutton Switch

JP1* Sullins PZC10DAAN or Equivalent 2 x 10 Position 0.25” Sq. Pin-Header

JP4 Sullins PZC12DFBN or Equivalent 2 – 2 x 12 Position 0.25” Sq. Pin-Header

C1, C3, C7, C9, C11, C13, C17

0.022 µF MLC X7R 0805 Chip Cap

C2, C4, C8, C10, C12, C18

100 pF MLC NPO 0805 Chip Cap

C14, C15 10 µF 16V Tantalum Electrolytic Cap

C16, C21 0.1 µF MLC X7R 1206 Chip Cap

C19, C20 330 pF MLC NPO 0805 Chip Cap

R5, R6, R16, R17 82Ω 1/8W 1206 Chip Resistor

R7, R8, R18, R19 130Ω 1/8W 1206 Chip Resistor

R9, R12, R13, R14, R15

270Ω 1/8W 1206 Chip Resistor

R21*, R22*, R23*, R24* 1-kΩ 1/8W, 5% 1206 Chip Resistor

R74 510Ω 1/8W, 5% 1206 Chip Resistor

R20 CTS 766-161-R512 or Equivalent 5.1-kΩ R-Pack-15 SO16

R38, R39 CTS 766-143-R220 or Equivalent 22Ω R-Pack-7 SO14

AMP 645955-2 or Equivalent 41 – Low Profile Socket-Pin

3M 929955-06 or Equivalent 4 – 0.1” Centerline Shorting Jumper

* — Used only for supervisory functions. Not needed for communications.


35

Appendix B. CY9266–C/T Schematic (Sheet 1 of 5)


36



37



38



39



40

Appendix B. CY9266–C/T Parts List


U1 Cypress CY7B923-JC HOTLink Transmitter

U2 Cypress CY7B933-JC HOTLink Receiver

U3 74F86 Quad XOR Gate, SOIC Package

U5* CTS CTX126 or Equivalent 25-MHz TTL Clock Oscillator

U6*, U7* TI TIL311 Hex Display With Logic

U8* Cypress CY7C344-15HC 32-Macrocell MAX EPLD

U9, U10 74F174 Hex D-Register, SOIC Package

U11* Maxim MAX707CSA or Equivalent Voltage Monitor

U12* Motorola MC10H116FN ECL Triple Line Receiver

D1* 1N4735A 1W, 6.2V Zener Diode

S1* AMP 3-435668-0 or Equivalent 10-Position DIP Switch

S2* ECG 520-01-3 or Equivalent Momentary Pushbutton Switch

J1 227161-3 or Equivalent RA Female BNC Connector

J2 227818-1 or Equivalent RA Female TNC Connector

JP1* Sullins PZC10DAAN or Equivalent 2 x 10 Position 0.25” Sq. Pin-Header

JP4 Sullins PZC12DFBN or Equivalent 2 – 2 x 12 Position 0.25” Sq. Pin-Header

P1 747844-6 or Equivalent RA Female 9-Pin D-Sub Connector

C14 10 µF 16V Tantalum Electrolytic Cap

C1, C3, C7, C9, C11, C13, C27*

0.022 µF MLC X7R 0805 Chip Cap

C2, C4, C8, C10, C12, C18, C21, C24*

100 pF MLC NPO 0805 Chip Cap

C20, C23* 0.01 µF MLC X7R 0805 Chip Cap

C28 1000 pF 1 kV, Y5P Disc Cap

T1 Pulse Engineering PE-65507 for STPPulse Engineering PE-65508 for coax

Dual-Wideband Pulse Transformer

R12, R13, R14, R15 270Ω 1/8W, 5% 1206 Chip Resistor


R21*, R22*, R23*, R24* 1-kΩ 1/8W, 5% 1206 Chip Resistor

R40, R41 37.4Ω 1/10W, 1% for Coax75.0Ω 1/10W, 1% for STP

0805 Chip Resistor

R43 40.2Ω 1/10W, 1% 0805 Chip Resistor

R49*, R50* 100Ω 1/10W, 5% 0805 Chip Resistor

R51*, R57* 150Ω 1/10W, 1% 0805 Chip Resistor

R47*, R48*, R58*, R59* 270Ω 1/10W, 5% for 150Ω cable 0805 Chip Resistor

R61, R62 200Ω 1/10W, 5% of 75Ω cable 0805 Chip Resistor

R52* 348Ω 1/10W, 1% 0805 Chip Resistor


R42 1.5-kΩ 1/10W, 1% 0805 Chip Resistor


41

R56* 2.2-kΩ 1/10W, 5% 0805 Chip Resistor

R63 510Ω 1/2W Axial Lead Resistor

R20 CTS 766-161-R512 or Equivalent 5.1-kΩ R-Pack-15 SO16

R38, R39 CTS 766-143-R220 or Equivalent 22Ω R-Pack-7 SO14

AMP 645955-2 or Equivalent 4 – Low Profile Socket-Pin

3M 929955-06 or Equivalent 4 – 0.1” Centerline Shorting Jumper

* — Used only for supervisory functions. Not needed for communications.

Appendix B. CY9266–C/T Parts List (continued)



42

Appendix C. BIST PLD State Machine Source Code

SUBDESIGN bist_sm (ready, bisten, clock : INPUT;enable : OUTPUT)

VARIABLEss : MACHINE OF BITS (enable_q)

%state output%WITH STATES (wait0 = 0,

wait1 = 0,wait2 = 0,enabled = 0,locked1 = 1,locked2 = 1);

BEGINss.clk = clock; %assign machine clock%enable = enable_q; %assign output of machine%

TABLE%present present next %% state inputs state%

ss, bisten, ready => ss;

% define reset vectors %wait0, 0, x => wait0;wait1, 0, x => wait0;wait2, 0, x => wait0;enabled, 0, x => wait0;locked1, 0, x => wait0;locked2, 0, x => wait0;

% define operational vectors %wait0, 1, x => wait1;wait1, 1, x => wait2;wait2, 1, x => enabled;enabled, 1, 1 => enabled;enabled, 1, 0 => locked1;locked1, 1, 1 => enabled;locked1, 1, 0 => locked2;locked2, 1, 1 => locked1;locked2, 1, 0 => locked2;

END TABLE;END;


43

Appendix C. BIST PLD Logic Schematic


44

Appendix D. CY9266–F Artwork — Top Silkscreen


45

Appendix D. CY9266–F Artwork — Top Layer Copper


46

Appendix D. CY9266–F Artwork — Power Layer


47

Appendix D. CY9266–F Artwork — Ground L ayer


48

Appendix D. CY9266–F Artwork — Bottom Layer Copper


49

Appendix D. CY9266–F Artwork — Bottom Silkscreen


50

Appendix D. CY9266–F Artwork — Drill Chart

fif


51

Appendix E. CY9266–C/T Artwork — Top Silkscreen


52

Appendix E. CY9266–C/T Artwork — Top L ayer Copper


53

Appendix E. CY9266–C/T Artwork — Power Layer


54

Appendix E. CY9266–C/T Artwork — Ground Layer


55

Appendix E. CY9266–C/T Artwork — Bottom L ayer Copper


56

Appendix E. CY9266–C/T Artwork — Bottom Silkscreen


57

Appendix E. CY9266–C/T Artwork — Drill Chart


© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorizeits products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of CypressSemiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Appendix F. CY9266 Configuration Guide

Function JP1 Jumper Settings

Switch SW1 Settings (0=on, 1 = off)

1 2 3 4 5 6 7 8 9 10

Xmtr BIST Enable * 0

Xmtr BIST External * 1

Xmtr Encode Mode * 0

Xmtr Bypass Mode * 1

Xmtr ENA Active * 0

Xmtr ENA External * 1

Xmtr ENN Active * 0

Xmtr ENN External * 1

Rcvr BIST Enable * 0

Rcvr BIST External * 1

Rcvr Decode Mode * 0

Rcvr Bypass Mode * 1

Rcvr Port A Selected *CX–CY

1

Rcvr Port B Selected * 0

Xmtr Enabled (FOTO Off) *EX–EY

0

Xmtr External * 1

Active HIGH Carrier Detect * 0

Active LOW Carrier Detect * 1

Active HIGH Byte Sync * 1 1

0 0

Active LOW Byte Sync * 1 0

0 1

Rcvr Port Select DIP CX–CY

Rcvr Port Select External BX–BY

FOTO Select DIP EX–EY

FOTO Select External FX–FY

Xmtr Clock Local Oscillator GY–HY

Xmtr Clock XMITCLOCK GX–GY

Rcvr Clock Local Oscillator IX–IY

Rcvr Clock XMITCLOCK HX–IX

Rcvr Clock EXTREFCLK IX–JX

OLC–266 Mode BX–BY, FX–FY, GX–GY, HX–IX 1 1 1 0 1 1 1 1

BIST Mode w/Cable (Standalone) CX–CY, EX–EY, GY–HY, IX–IY 0 0 1 0 1 0

BIST Mode wo/Cable (Standalone) CX–CY, EX–EY, GY–HY, IX–IY 0 0 1 0 0 0

* – These SW1 controlled signals have a 5.1-kΩ pull-up resistor on the CY9266 card, and may be controlled externally when the SW1 switch is in the off position. With no attached external driver these signals go to a logic-1 state when the SW1 switch position is off.

Documents

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