C/VHDL Codesign for LHCb C/VHDL Codesign for LHCb VELO zero-suppression VELO zero-suppression

algorithmsalgorithms

Manfred Muecke, CERNManfred Muecke, CERN

C/VHDL Codesign C/VHDL Codesign Manfred MueckeManfred Muecke page page 22

Introduction – TELL1Introduction – TELL1

36 values * 64 links* 1.1MHz * 10bit

= 2.95GB/s

50.44 cluster * 1.1MHz * 2B

= 106MB/s

(L1 raw bandwidthw/o protocol overhead)

DSP on 5 Altera Stratix EP1S25DSP on 5 Altera Stratix EP1S25..evolving algorithms..evolving algorithms..at high data rates..at high data rates

64 links @ 40MHz or24 fibers @ 1,2Gbps

2 (4) GBE copper links

LHCb DAQ Interface Board (EPFL) x300

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Motivation – Code ConsistencyMotivation – Code Consistency

System SimulationFramework

(C++)

DSP on FPGA

parallel progress -how to guarantee

consistency?

FPGA Design(VHDL)

DSP

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RequirementsRequirements

to guarantee consistency, one of the two models to guarantee consistency, one of the two models has to be generated automatically..has to be generated automatically..

? ? VHDL VHDL- syntesizeable VHDL- syntesizeable VHDL- latency as design parameter- latency as design parameter- efficient resource usage- efficient resource usage

? ? C C - fast execution- fast execution

- simple integration/interface- simple integration/interface

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Chosen solutionChosen solution

Confluence – Confluence – a synchronous a synchronous hardware generation hardware generation language and compilerlanguage and compiler

.cf

.vhd .v .c .jhdl .nusmv

ConfluenceCompiler +Code Generator

.fnf

Cf

FNF

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ConfluenceConfluence

Open source project Open source project ((www.confluent.org)) ..functional language for synchronous systems..functional language for synchronous systems

..written in O’Caml..written in O’Caml

..runs under Unix/Linux/Cygwin/....runs under Unix/Linux/Cygwin/..

synthesizable VHDLsynthesizable VHDL

bit- and cycle-accurate C-modelbit- and cycle-accurate C-model

.vhd

.c

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FPGA Design(VHDL)

DSP (VHDL)

Common code baseCommon code base

System SimulationFramework

(C++)

DSP on FPGA (C)

DSP.cf

X

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Example -Example -Linear Common Mode SuppressionLinear Common Mode Suppression

calculates mean, slope and deviation over calculates mean, slope and deviation over 32 samples32 samples

40MHz data stream (x16/FPGA)40MHz data stream (x16/FPGA)

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MeasurementsMeasurements

LCMSLCMS Handcoded Handcoded VHDLVHDL

ConfluenceConfluence

CC VHDLVHDL

ResourcesResources

(LE, memory bits)(LE, memory bits)235 LEs, 7680 235 LEs, 7680 bits, 2 9bDSPbits, 2 9bDSP --

329 LEs, 1088 329 LEs, 1088 bits, 6 9bDSPbits, 6 9bDSP

VHDL simulation VHDL simulation time (ModelSim)time (ModelSim)

1 000 000 1 000 000

cyclescycles

P4 2,6G

Hz

P4 2,6G

Hz

~120s~120s -- ~80s~80s

C runtimeC runtime

(gcc)(gcc)-- <1s<1s --

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OutlookOutlook

Implementing further algorithms Implementing further algorithms

Integrating C model in VELO simulationIntegrating C model in VELO simulation

automated checking of model consistencyautomated checking of model consistency

language features for DSPlanguage features for DSP

Other solutions/languages?Other solutions/languages?

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LinksLinks

LHCb - LHCb - http://lhcb-public.web.cern.chTELL1 - http://lphe.epfl.ch/~ghaefeliTELL1 - http://lphe.epfl.ch/~ghaefeli

Confluence - Confluence - http://www.confluent.orgO’Caml - O’Caml - http://www.ocaml.org

email - Manfred.Muecke_at_cern.chemail - Manfred.Muecke_at_cern.ch

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Thanks for your attention!Thanks for your attention!

Questions?Questions?

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Algorithm Algorithm VHDL VHDL

IP-based source (Simulink)IP-based source (Simulink)(Xilinx, TI, Synplicity DSP Synthesis, …)(Xilinx, TI, Synplicity DSP Synthesis, …)- vendor locked (MathWorks + TI/…)- vendor locked (MathWorks + TI/…)- limited/application-specific IP- limited/application-specific IP

Algorithmic source (behavioural synthesis)Algorithmic source (behavioural synthesis)- on the go (Celoxica, Mentor Catapult C, - on the go (Celoxica, Mentor Catapult C, Forte’s Cynthesizer)Forte’s Cynthesizer)- SLDL efforts: SystemC, SystemVerilog- SLDL efforts: SystemC, SystemVerilog-> no RTL control (latency)-> no RTL control (latency)

=> as of now, we still have to code in => as of now, we still have to code in VHDL/RTL (if we care about speed)!!VHDL/RTL (if we care about speed)!!

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Confluence featuresConfluence features

Functional language (recursion)Dynamic typing (ports adapt)List typeList typeVector type -> HardwareVector type -> HardwarePurely synchronousImplicit Synchronization (clock, reset, enable)