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CURRENT�MODE DIGITAL MULTIPLIERS FOR RADIX N AND MODULO N ARITHMETIC

O. Maslennikow, P. Pawlowski, N. Maslennikowa, R. Berezowski,Technical University of Koszalin, Poland

6 No. 4. 2019SYNCHROINFO JOURNAL

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8 No. 4. 2019SYNCHROINFO JOURNAL

REFERENCES

[1] M. Ingels, “Design strategies and techniques for reducing

the effects of electrical interference in mixed�mode ICs”,

IEEE J. of Solid�State Circuits, No. 7, 1997, pp. 1136�1141.

[2] P. Pawlowski, “Current Mode Digital Gates for Mixed

Mode Reprogrammable Integrated System”, Proc. of 1st

IEEE Int. Conf. on Circuits and Syst. for Com.,

ICCSC’2002, St. Petersburg, Russia, 2002, pp. 178�181.

[3] O. Maslennikow, “Approaches to Designing and

Examples of Digital Circuits Based on the Current�Mode

Gates”, Data Recording, Storage & Processing, Vol. 3, No.

2, 2001, pp. 84�98.

[4] O. Maslennikow, D. Gretkowski, P. Pawlowski,

“Current�Mode Circuits for Multiple�Valued Logic and

Residue Number System Arithmetic”, Proc. of the 10�th Int.

Conf. on Mixed Design, MIXDES’2003, pp. 182�187.

[5] A. K. Jain, R. J. Bolton, M. H. Abd�El�Barr, “CMOS

Multiple�Valued Logic Design”, IEEE Trans. Circ. and Syst.

I, No. 8, 1993, pp. 503�514.

[6] Residue Number System Arithmetic: Modern

Applications in DSP. M. Soderstrand, W. Jenkins, G. Jullien

(editors), IEEE Press, 1988.