Current saturation mechanism and FBSOA of the SIMEST

Pergamon

Solid-Dart= Electronics Vol. 41, No. 4, 561-566. 1997 pp. 0 1997 Elsevier Science Ltd

Printed in Great Britain. All rights reserved PII: S003&1101(96)00202-X 0038-I 101/97 $17.00 + 0.00

CURRENT SATURATION MECHANISM AND FBSOA OF THE SIMEST

S. SRIDHAR and B. J. BALIGA

Power Semiconductor Research Center, North Carolina State University, Raleigh, NC 27695-7924, U.S.A.

(Received 23 May 1996; in revised form I October 1996)

Abstract-It is demonstrated that the current saturation mechanism for the SIMEST is due to operation of the thyristor region in a non-regenerative mode by the shunting of holes from the P-base region via a lateral P-MOSFET, a mechanism not observed in previous power devices. The FBSOA of the SIMEST is shown to be limited by avalanche breakdown in the drift region at low current densities and by the breakdown of the lateral N-channel MOSFET at high current densities. The effects of the parametric variations on the output characteristics and the FBSOA are reported for the first time. 0 1997 Elsevier Science Ltd. All rights reserved

INTRODUCTION

Power semiconductor devices are required for applications such as motor drives, uninterrupted power supplies (UPS), appliance controls, lighting ballasts, etc. For these applications, it is desirable to have high input impedance, voltage controlled devices with low on-state voltage drops and high switching speeds in order to minimize the power losses. The most commonly used device for these applications today is the IGBT[l,2]. In MOS-gated thyristors, the on-state voltage drops are lower than that for the IGBT due to better conductivity modulation of the drift region. Several MOS gated thyristors (such as the MCT[34], conventional EST (C-EST)[5-71, Dual Channel EST (DC-EST)[8], and BRT[9]) have been reported. Of these structures, the EST is the device most likely to replace the IGBT because it combines the current saturation feature of the IGBT (which is absent in other MOS-gated thyristors) with the lower on-state voltage drop of the thyristor structure. However, in the C-EST and the DC-EST, the maximum controllable current is limited by the presence of an inherent parasitic thyristor caused by the integration of the lateral N-channel MOSFET with the vertical thyristor. Recently, a new EST structure called the SIMEST[lO], in which the parasitic thyristor is eliminated by locating the lateral N-channel MOS- FET of the EST within an oxide tub, has been reported. This device has been experimentally demonstrated to exhibit low on-state voltage drops with gate controlled operation at high current densities due to elimination of the parasitic thyristor[ll]. In this paper, the current saturation mechanism of the SIMEST is analyzed with the aid of two-dimensional numerical simulations, and

shown to be different to that of previous power devices, such as the IGBT. In addition, the dependence of its forward biased safe operating area (FBSOA) on cell parameters is reported for the first time.

DEVICE STRUCTURE AND OPERATION

The cross-section of the SIMEST is shown in Fig. 1. By locating the lateral N-channel MOSFET in an oxide tub, the parasitic thyristor inherent in previous EST structures is eliminated. The P-base region of the main thyristor segment is shorted to the cathode in a dimension perpendicular to the cross-section shown in Fig. 1. Forward blocking is achieved when the gate is shorted to the cathode, and the applied anode voltage is supported by the P-base/N-drift region junction. When a positive bias is applied to the anode with the gate biased above its threshold voltage, electrons are injected into the N-drift region from the cathode via the series path comprising of the lateral N-channel MOSFET, metal strap and turn-on gate. The device then operates like an IGBT at low current densities with injection of holes from the P+ substrate. The hole current collected in the P-base region flows under the floating N+ region in a direction perpendicular to the cross-section of Fig. 1 into the short to the cathode. The potential in the P-base region is then determined by the resistive drop caused by the flow of hole current in the P-base region into the cathode short. When the hole current flowing in the P-base region of the main thyristor segment is sufficiently large so as to forward bias the N+/P-base junction (J,), the main thyristor latches up. Since the thyristor current is constrained to flow through the lateral N-channel MOSFET, gate control is retained over the device

561

562 S. Sridhar and B. J. Baliga

Metal strap P(t”mm<MOSFET N(turna)-MOSFET

Ji N- Drift Region

N Buffer Layer

P+ Substrate

Anode

Fig. 1. Cross-section of the SIMEST.

operation. Turn-off can be achieved by reducing the gate bias to zero. This open circuits the floating N+ region, thereby cutting off the supply of electrons to the thyristor, disrupting the regenerative thyristor action, and turning-off the device. The turn-off mechanism in the SIMEST is therefore similar to what has been previously reported for the EST[S].

At low gate bias voltages, current saturation is obtained in the SIMEST by an unique mechanism not previously observed in other power devices. When the bias on the anode terminal is increased, the potential in the drift region increases. When the potential in the drift region at point A in Fig. 1 exceeds the voltage applied to the gate, an inversion layer is formed which shunts holes away from the P-base region to the P+ diverter via the P-MOSFET. This tends to turn the thyristor off in a manner similar to the BRT[9]. Due to shunting of the base current, the current gain of the NPN transistor is reduced and the thyristor can no longer operate in the regenerative mode (i.e. aNPN + aNPN < 1). However, the current flow is maintained by the vertical NPN transistor supplying base current to the PNP transistor with the PNP transistor operating in its forward active mode. The anode voltage is therefore mainly supported in the drift region resulting in current saturation even at high anode voltages beyond the breakdown voltage of the lateral N-channel MOSFET. A theoretical analysis of current saturation mechanism of the SIMEST is discussed in detail in this paper with the goal of defining mechanisms that determine the FBSOA of the SIMEST.

TWO-DIMENSIONAL NUMERICAL SIMULATIONS

Extensive two-dimensional numerical simulations were performed using MEDICI[12] to analyze the current saturation mechanism in the SIMEST. The simulated device had a buried oxide thickness of 4000 A, SO1 thickness of 2000 A, gate oxide thickness of 500 A, drift region doping and thickness of 1 x 10’4cm-’ and 50 pm, buffer layer doping and thickness of 1 x lOI cm-3 and 15 pm, P-base dose and junction depth of 7 x lOI crnd2 and 3 pm, N+ dose and junction depth of 5 x lOIs cm-’ and 1 pm, and P+ diverter dose and junction depth of 4 x 10“’ cm-2 and 1 pm, identical to the parameters in the fabricated SIMEST devices. The high level lifetime value used in the simulations was 1 ps. These parameters gave the device a forward blocking voltage of 700 V when the gate was shorted to the cathode. The threshold voltage for the N-channel turn-on MOSFET and the lateral N-MOSFET were obtained to be 1.8 and 2.1 V respectively. Simulations indicated that the device exhibited high voltage current saturation, with the applied anode bias supported across the drift region as previously reported[lO,ll].

FRSOA LIMIT

Figure 2 shows the output characteristics of the SIMEST obtained by two dimensional numerical simulations. It can be seen from Fig. 2 that the device shows current saturation up to large anode biases at large current densities. The FBSOA boundary of the

Current saturation mechanism and FBSOA of the SIMEST 563

Anode voltage (v)

Fig. 2. Simulated output characteristics in the SIMEST. The device shows high voltage current saturation.

SIMEST is plotted in Fig. 3 along with the simulated FBSOA of an IGBT with doping parameters and design rules identical to the SIMEST. It can be seen in Fig. 3 that the FBSOA boundaries for the SIMEST and the IGBT are different especially at higher current densities. In an IGBT, the FBSOA boundary is limited by avalanche breakdown at low current densities and by the latch-up of the parasitic thyristor at higher current densities.

It has been found that the FBSOA boundary in the dual channel EST is determined by the same two mechanisms[l3]. However, in the SIMEST, since the parasitic thyristor has been eliminated by the buried oxide layer, the FBSOA boundary at higher current densities is determined by a mechanism different from that for the IGBT and EST. At low current densities, the FBSOA boundary for the SIMEST lies almost on the calculated boundary corresponding to avalanche breakdown[ 13,141 which is also plotted in Fig. 3. This indicates that the FBSOA boundary for the SIMEST at lower operating current densities is determined by the avalanche breakdown in the drift region. It can be seen in Fig. 3 that the FBSOA boundary at higher

0 I I I

0 200 4ca MO E.3

Anode Voltage (V)

Fig. 3. Plot of the simulated FBSOA of the SIMEST as a function of the thyristor area and turn-off MOSFET gate length. The simulated FBSOA of an IGBT with identical design rules and the calculated avalanche limit is also

plotted alongside.

current densities in the SIMEST falls inside the avalanche boundary. This indicates that the FBSOA in the SIMEST at higher current densities is limited by a mechanism other than avalanche breakdown and parasitic thyristor latch-up. This mechanism is discussed in the following section.

CURRENT SATURATION MECHANISM

As was discussed earlier, holes are shunted away from the P-base region via the P-channel MOSFET during current saturation. The potential in the P-base region is therefore determined by the voltage dropped by the shunted hole current across the P-base region and the P-channel MOSFET. The potential in the P-base region during current saturation can be written as:

v&p.bau = ~shun&-base) + ~PMOS (1)

where Vp.bau is the potential in the P-base region, IIhun, is the hole current shunted through the channel, RP.~- is the resistance of the P-base region and VpMos is the drain source potential of the P-channel MOSFET. Note that &,unt is also the current flowing through the MOSFET.

The P-base region is the source of the lateral P-channel MOSFET. The threshold voltage of the lateral P-channel MOSFET is about - 1.5 V. Simulations indicate that values of the voltage applied to the channel (Vc - I/T), range from 0.5 to 1.1 V. Since the drain (P+ diverter) of the P-MOSFET is at ground potential, when the voltage appearing at the P-base (source) of the P-channel MOSFET exceeds Vo - VT (0.5 to 1.1 V in this case) the P-MOSFET operates in its saturation mode. Since, Ishunt is the current flowing in the P-channel MOSFET, we can write:

where Vo is the potential applied to the gate, VA is the potential at point A (Fig. l), and VT the threshold voltage of the P-channel MOSFET. The P-channel MOSFET operates in its saturation mode and any increase in the anode current density causes the potential in the P-base region (source of the P-channel MOSFET) to rise rapidly.

This behavior is schematically illustrated in Fig. 4, in which the operating points of the P-channel MOSFET are shown as the SIMEST goes into saturation. At low anode current densities the P-channel MOSFET is operating in its linear region (point W in Fig. 4) and it moves into saturation as the anode bias is increased. As the anode bias is increased further the anode current density increases. An increase in the anode bias causes an increase in the potential at point A (Fig. 1). Since the bias applied on the gate is fixed, this results in a larger voltage appearing across the P-channel. So the MOSFET not only goes more into saturation due to


Fig. 4. Schematic of the P-channel MOSFET’s operating points during current saturation in a SIMEST.

the increasing anode bias, but also operates at a higher current level due to an increase in the voltage applied across the channel. This results in an increase in the voltage appearing across the MOSFET ( VMOS).

This corresponds to point X in Fig. 4. As the anode bias is increased still further, the operating point of the MOSFET shifts further toward point Y (Fig. 4). Since, the NPN transistor provides the base drive for the PNP transistor, junction J, is forward biased. Thus the potential of the floating N+ region remains one junction drop below that of the P-base region. Consequently, the voltage of the drain of the lateral N-channel MOSFET also follows the increasing potential in the P-base region (source of the P-channel MOSFET). When the potential at the floating N+ region exceeds the breakdown voltage of the N-channel MOSFET, gate control is lost over the device operation (point Z in Fig. 4) because it is no longer possible to raise the potential of the P-base region to shunt holes.

The voltage supported across the N-channel MOSFET in the SIMEST structure is plotted as a function of the applied anode bias in Fig. 5. The gate bias conditions are identical to that shown in Fig. 2. It can be seen from Fig. 5 that the maximum voltage appearing across the MOSFET at any gate bias is about 12 V, which is the breakdown voltage of the

Fig. 5. Plot of the voltage supported across the lateral N-ihannel MOSFET the applied anode bias as a fActi& of

in a SIMEST.

N-channel MOSFET in the SIMEST structure. The operating points of the lateral N-channel MOSFET corresponding to the points where gate control is lost over the SIMEST operation are shown in Fig. 5. The corresponding points are marked on the output characteristics of the SIMEST (Fig. 2). From this it can be concluded that, the FBSOA boundary at higher current densities is limited by the breakdown voltage of the N-channel MOSFET. However, at low gate bias values (< 3 V), the SIMEST reaches its FBSOA boundary well before the voltage across the MOSFET reaches its breakdown voltage, as seen in Fig. 5. In this regime of operation the FBSOA boundary is determined by the avalanche boundary as is the case for the IGBT and the DC-EST. Based upon the above analysis of the current saturation mechanism, it can be concluded that the anode voltage up to which the anode current can be saturation should increase with: (a) a decrease in the length of the turn-on gate, because this leads to an increase in the hole current that can be shunted; (b) a decrease in the length of the thyristor (L, in Fig. 1) as this decreases the magnitude of the hole current that needs to be shunted through the lateral P-MOSFET at a given anode current density; (c) a decrease in the operating current density, since this results in a decrease in the hole current that must be shunted away; and (d) an increase in the breakdown voltage of the lateral N-channel MOSFET; the effect of these parameters on the current saturation capability and hence the FBSOA of the SIMEST is presented in the following section.

PARAMETRIC DEPENDENCE OF FBSOA

The forward biased safe operating area (FBSOA) is an important parameter in evaluating the performance of power devices[ 151. A good FBSOA is desirable to perform gate controlled turn-on and turn-off, and for short circuit protection. The FBSOA of the SIMEST was analyzed by simulations performed using parametric variations in the cell geometries, and compared to that of an IGBT having identical design rules and doping parameters.

(a) Thyristor area: in Fig. 3 the influence of the thyristor area (keeping all other cell parameters the same) on the FBSOA of the SIMEST is shown. By comparing cases (a) and (b), the FBSOA is seen to decrease with increasing thyristor area. This is because an increase in the thyristor area results in a larger number of holes which have to be shunted from the P-base region during current saturation. Since the ability of the P-channel MOSFET to shunt current is unchanged this results in a reduction in the current saturation capability of the SIMEST. At lower current densities where the FBSOA is limited by avalanche multiplication

Current saturation mechanism and FBSOA of the SIMEST 565

m 100 Ecu m mo a0

Anode Bias (V)

Fig. 6. Dependence of the simulated FBSOA of the SIMEST on the breakdown voltage of the lateral N-channel

MOSFET and Be device lifetime.

(b)

(cl

in the N-drift region, the FBSOA is observed to be independent of thyristor area as expected. Thus, an increase in the thyristor area results in a decrease in the FBSOA in the SIMEST at higher current densities. Turn-on gate length: the FBSOA of the SIMEST can be seen to improve with a decrease in the turn-on gate length as shown in Fig. 3 using cases (a) and (c). The turn-on gate is also the gate of the P-channel MOSFET. A decrease in the turn-on gate length results in a decrease in the channel length of the P-MOS- FET and this increases the current shunted by the P-channel MOSFET (see eqn 2) thus improving the FBSOA. N-channel MOSFET breakdown voltage: the FBSOA of the SIMEST was found to improve with an increase in the breakdown voltage of the N-channel MOSFET. Figure 6 shows the FBSOA for a SIMEST for two different lateral N-channel MOSFETs with breakdown voltages of 14 and 28 V. An increase in the breakdown voltage of the N-channel MOSFET results in that MOSFET reaching breakdown at larger anode biases, thereby improving the FBSOA at higher current densities where it is limited by the breakdown voltage of the lateral N-channel MOSFET. The FBSOA limit is unaltered at lower current densities since in that regime of operation the FBSOA limit is determined by avalanche multiph- cation. However, an increase in the N-channel MOSFET breakdown voltage results in an increase in the on-state voltage drop because it was achieved with an increase in the channel length[ 1 I].

(d) Lifetime: the FBSOA of the SIMEST was found to improve with a reduction in lifetime as is the case with the IGBT[16]. In Fig. 6, the FBSOA at lifetime values of 1 and 10 ~LS are plotted. The FBSOA for the I ps lifetime (case (a)) is larger than that for the 10 ps lifetime value (case (c)). As the lifetime is reduced, the

hole component of the on-state current decreases. Consequently, the number of holes that are shunted by the diverter at a given anode current density decreases with a decrease in lifetime. This results in a decrease in the voltage appearing across the P-channel MOS- FET and consequently results in an improve- ment in the FBSOA in the regime where it is limited by the breakdown voltage of the N-channel MOSFET. The regime where the FBSOA is limited by avalanche multiplication improves with a reduction in lifetime resulting in an increase in the FBSOA as has been reported for the IGBT[16]. Hence, a reduction in lifetime leads to an increase in the FBSOA of the SIMEST.

SUMMARY AND CONCLUSIONS

The mechanism of high voltage current saturation in the SIMEST has been analyzed and found to be limited by avalanche breakdown in the drift region at lower current densities (same as for IGBTs and ESTs) and by the breakdown voltage of the lateral N-channel MOSFET at higher current densities. This mechanism is different from that reported for the IGBT and DC-EST structures where the FBSOA is limited by the latch-up of the parasitic thyristor at high current densities. The current saturation capability and hence the FBSOA in the SIMEST is found to increase with: (1) a reduction in the thyristor size; (2) a reduction in the turn-on MOSFET gate length; (3) an increase in the breakdown voltage of the lateral N-channel MOSFET; (4) a decrease in the lifetime of the device.

Acknowledgements-The authors wish to thank the sponsors of the Power Semiconductor Research Center (PSRC) for their support and TMA associates for providing the use of MEDICI, the two-dimensional device simulator used in this work.

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REFERENCES

Baliga, B. J.. Adler, M. S., Gray, P. V., Love. R. P. and Zommer, N., The insulated gate transistor, IEDM Tech. Dig., 1982, 26&267. Russels, J. P., Goodman, A. M., Goodman, L. A. and Neilson, J. M., The COMFET, IEEE Electron Dev. Lett., EDL-4, 264-267. Temple, V. A. K., MOS controlled thyristors, IEDM Tech. Dig., 1984, 282-285. Bauer, F., Roggwiler, P., Aemmer, A., Fichtner, W., Vuilleumier, R. and Moret, J. M., Design element of MOS controlled thyristor elements, IEDM Tech. Dig., 1989, 297-300. Shekar, M. S., Baliga, B. J., Nandakumar, M., Tandon, S. and Reisman, A., Characteristics of the emitter switched thyristor, IEEE Trans. Electron Den., 1991, ED-38(7), 1619-1623. Bhalla, A. and Chow, T. P., 550 V, N-channel emitter switched thyristors with an Atomic Lattice Layout Geometry, IEEE Electron Device Lett., 1994, 15,

452454.


7

8.

9.

IO.

Bhalla, A. and Chow, T. P., RECEST: Reverse Channel 11. Emitter Switched Thvristor. Proc. of ISPSD 95.

Sridhar, S. and Baliga, B. J., The SIMEST, a new MOS-gated emitter switched thyristor structure, Proc. ISPSD, 1996. MEDICI, TMA Associates. Iwamuro, N., Shekar, M. S. and Baliga, B. J., A study of EST’s short circuit SOA. Proc. of ZSPSD 93. pp. 71-76. Baliga, B. J., Power Semiconductor Devices, PWS Publishing Co., 1996. Yamada, T.. Majumdar, G., Mori, S.. Hagino, H., Kondoh, H. and Hirao, T., Next Generation Power Module, Proc. of ISPSD 94, pp. 3-8. Baliga, B. J., Switching Speed enhancement in Insulated gate Transistors by Electron Radiation, IEEE Trans. Elec. Deu., 1984. ED-31, 179C1795.

pp. 2630. Shekar, M. S., Baliga, B. J., Nandakumar, M., Tandon, 12. S. and Reisman, A., High-voltane current saturation in 13. emitter switched thyristors, IEEE Electron Device Lerr., 1991, EDL-12, 387-389. Nandakumar, M., Baliga, B. J., Shekar, M. S., Tandon, 14. S. and Reisman, A., A new MOS-gated power thyristor structure with turn-off achieved by controlling the base 15. resistance, IEEE Electron Device L.err., 1991, EDL-12, 227-229. Sridhar, S. and Baliga, B. J., The SIMEST: a new EST 16. structure without parasitic thyristor achieved using SIMOX technology, Elec. Len., 1995, 2048-2050.

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Current saturation mechanism and FBSOA of the SIMEST