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Dept. of EECS,
Korea Advanced Institute of Science and Technology
Circuit Design & System Application Laboratory
Current-mode Driving Schemes for AMOLED Display
& SIMO PMICs
Gyu-Hyeong Cho
October 10th, 2012
KAIST
EECS, KAIST Circuit Design & System Application Laboratory
Contents
Introduction
Feedback Driving Method
-DFFC Driver
Feedforward Driving Methods
-TCF Driver
-Push-Pull TCF Driver
Real-time Image Sticking Compensation Methods
PMIC
EECS, KAIST Circuit Design & System Application Laboratory
High Contrast
Natural
Color
Thin Fast
Response
Wide Viewing
Angle
Low Power
Consumption
AMOLED (Active Matrix Organic Light Emitting Diode)
Motivation (1/2)
EECS, KAIST Circuit Design & System Application Laboratory
SCAN(N)
Driver Driver Driver
R/G/B DATA
SCAN(N+1)
Ga
te (
SC
AN
) D
riv
er
Column (DATA) Driver D
AT
A L
INE
1. Massive capacitance in data lines
2. Non-uniform TFT & Luminance
AMOLED System
Requirements for Driver
Motivation (2/2)
EECS, KAIST Circuit Design & System Application Laboratory
Introduction (1/2)
• Current • Voltage
• Current • Voltage
• PWM
• TRG • ARG
Data driving schemes for AMOLED displays
EECS, KAIST Circuit Design & System Application Laboratory
Introduction (2/2)
Conventional Driving Scheme
Analog
Voltage
Analog
Current
Digital
ARG
Digital
TRG
Voltage
Feedback
Current
Feedback
Hybrid
PWM
Threshold
Voltage
Compensation
Good Good - - Good Good
-
Mobility
Compensation Poor Good - - Good Good -
Driving
Speed Fast Slow Fast Fast Slow Medium Fast
Driving
Accuracy Medium Good Poor Medium Medium Medium Medium
Luminance
Uniformity Bad Good Good Medium Medium Good Medium
Data driving schemes for AMOLED displays
High Speed Analog Current Driving Method High Driving Accuracy & Speed Current Feedback Method
EECS, KAIST Circuit Design & System Application Laboratory
Part I
Current-mode AMOLED Drivers: DFFC (Direct-type Fast Feedback Current) Driver
EECS, KAIST Circuit Design & System Application Laboratory
Block Diagram for FFCD
Conceptual diagrams for Fast Feedback Current Driver(FFCD)
Feedback driver : Current sensing & comparison, loop compensator and error amp.
EECS, KAIST Circuit Design & System Application Laboratory
IDATA
SCAN
VDD
VB2
OLED
VB1
IPIXEL
RPD
RPF
CPF
CPD
A2
A1
CS
MP1
MP2
MP3
MD1X Y
Adaptive
Frequency
Compensation
Data Line
Parasitic
Feedback Line
Parasitic
M1M2
M3
M4
Direct-type Fast Feedback Current (DFFC) Driver
VB2 < Vth,OLED
OLED turns off during feedback loop operation
IPIXEL
Directly Compared!!
IDATA
DFFC Driver PIXEL
EECS, KAIST Circuit Design & System Application Laboratory
IDATA
SCAN
VDD
VB2
VB1
IPIXEL
RPD
RPF
CPF
CPD
A2
A1
CS
MP1
MP2
MP3
MD1X Y
Data Line
Parasitic
Feedback Line
Parasitic
CC
COLED
M1M2
M3
M4
Delay Reduction from Capacitance
Move 2nd,3rd poles to higher freq. Wider BW, faster driving speed
Impedance
Low output impedance
ωP1
ωP2
ωP3
EECS, KAIST Circuit Design & System Application Laboratory
Requirement for Min. GBW
Display
Resolution
Driving
Accuracy
1-Horizontal time
(TH)
Min. Gain-BandWidth
(ωGB,min)
WXGA
(1280 X 800)8b 20μs @60Hz 50kHz
FHD
(1920 X 1080)8b 15μs @60Hz 66kHz
Loop Characteristics Step Responses T(s)
ω0dB
①IDATA
decreasing
ωGB,min< ωGB,min > ωGB,min
②Adaptive
CC
ωGB
increasing
t
IPIXEL
IDATA
TH
(1-Horizontal time)
< ωGB,min
ωGB,min
> 0.5LSB
0
ωP1
ωP1ωP1② ①
ωP2ωP3
ωP2
(Const.)
ωP3
Valid Range
(≥ ωGB,min)
Valid Range
(≥ ωGB,min)
EECS, KAIST Circuit Design & System Application Laboratory
IDATA (nA)10 100 1000
Co
mp
en
sa
tio
n C
ap
ac
ito
r (f
F)
100
1000
10000
Min.
Gain-BandWidth
(GBW)
Phase Margin
(PM = 65°)
Selected CC
PM < 65°
PM > 65°
< Min. GBW
> Min. GBW
Valid
Range
Adaptive Freq. Compensation
VB1
D <1:7>
CC7
CC1
CC2
A1
Adaptive Freq.
Compensation Block
Compensation capacitor (CC) array
Cc from GBW and PM boundary conditions
Divide 7 ranges according to IDATA
CC Selection Rule
EECS, KAIST Circuit Design & System Application Laboratory
Loop Gain with Full IDATA Range
Frequency (Hz)
10-3 10-2 10-1 100 101 102 103 104 105 106
Ga
in (
dB
)
-20
0
20
40
60
80
100
120
IDATA=10nA
IDATA=40nA
IDATA=160nA
IDATA=640nA
IDATA=2550nA
Valid Range
(≥ ωGB,min)
ΔωP1
ΔTDC
ωGB,min
(50kHz for WXGA)
165kHz
EECS, KAIST Circuit Design & System Application Laboratory
Measurement Result (Data Transition)
D<0:7>
SCAN
2.55uA
1.27uA
310nA70nA10nA
2.55uA
Programming
PeriodEmission
Period
11μsNode Z
Programming
Period
8μs
Data current range from 10nA to 2.55A Settling time < 11s
EECS, KAIST Circuit Design & System Application Laboratory
Part II
Current-mode AMOLED Drivers: TCF (Transient Current Feedforward) Driver
EECS, KAIST Circuit Design & System Application Laboratory
TCFD (1/15)
Introduction of the TCC
EECS, KAIST Circuit Design & System Application Laboratory
TCFD (2/15)
Realization of the TCC
EECS, KAIST Circuit Design & System Application Laboratory
TCFD (3/15)
EECS, KAIST Circuit Design & System Application Laboratory
TCFD (4/15)
19/31
EECS, KAIST Circuit Design & System Application Laboratory
TCFD (5/15)
EECS, KAIST Circuit Design & System Application Laboratory
TCFD (6/15)
EECS, KAIST Circuit Design & System Application Laboratory
TCFD (7/15)
0dB 0dB
LG < 0dB !!
EECS, KAIST Circuit Design & System Application Laboratory
TCFD (9/15)
EECS, KAIST Circuit Design & System Application Laboratory
Part III
Current-mode AMOLED Drivers: PP-TCF (Push-Pull Transient Current Feedforward)
Driver
EECS, KAIST Circuit Design & System Application Laboratory
VDD
IDATA
AO
VREF1
M1 M2
M3 M4
IB IBCDP
OTA1
SinkCurrentControl
LoopGain
Control
ISINK1, 2 (t)1/g
m.D
TF
T
RDP RDP
CDP
DL with a Pixel Ckt. ADL
GND
CST
CurrentSense
M5
IB+
I TC
IB+
I TC
ITC ITC
IPIXEL
Conceptual Diagram of Push-Pull TCF Driver -Complete push-pull function for output currents -PFB gain control for removing undulation phenomena in pixel currents
PP-TCF Data Driver (1/15)
EECS, KAIST Circuit Design & System Application Laboratory
PP-TCF Data Driver (2/15)
PFBNFB
VDD
I DA
TA
CST
Pixel Emulation
M1 M2
M3
IB IBCDP CDP
IPIXELV
RE
F1
VR
EF
2
DA
MP
VB1
M4
M6 M7
M8 M5
M9
S1
OTA1
M9
RDP RDP
VDD VDD
RSENS
VB2
VB3
CSENS
OTA2
OUTA OUTB
CurrentSense
Sink Current Control
Lo
op
Ga
in C
on
tro
l
SCANEnabled
VDD
OLED
X
Y
AMP1
DTFT
ISINK1ISINK2
DL ADL
RC
CC
P
Detailed Schematic for PP-TCF Driver
EECS, KAIST Circuit Design & System Application Laboratory
PP-TCF Data Driver (4/15)
Data1
Data2
CLOCK2
PP-TCF Control Logic
Current
DACPP-TCF
Data
Selector
8b
8b
8b
Data
Generator
Data Alternation
Da
ta G
en
. E
na
ble
Ga
in C
on
tro
l E
na
ble
Ou
tpu
t S
wit
ch
Co
ntr
ol
8b CST
ESCAN
VDD
OLED
Y1
AMP1
DTFT
CST
OSCAN
VDD
OLED
Y2
AMP2
DTFT
AMOLED Panel Load Emulation
CLOCK1
Gate Controls
5-stage Distributive Network
Lo
ad
Se
lec
tio
n
VPRC
PR
C E
na
ble
OutputSwitches
OUTA
OUTB
Various functions for evaluating the performances of PP-TCF driver
Functional Diagram of Prototype Driver IC
EECS, KAIST Circuit Design & System Application Laboratory
PP-TCF Data Driver (5/15)
PFB gain control for removing undulation phenomena in pixel currents
Positive Feedback Loop (PFB) Gain Control (1)
EECS, KAIST Circuit Design & System Application Laboratory
GDAMPGDAMPGDAMPGDAMPGDAMP
12
34
5
+
−
VPFB.IN VPFB.OUT
DAMPControl 5
AO A1
PP-TCF Data Driver (6/15)
Conceptual Diagram for PFB Gain Control
10 100 1k 10k 100k 1M 10M 100M-80
-60
-40
-20
0
20
40
60
80
100
10k 100k 1M-20
-10
0
10
Loop G
ain (
dB
)
Frquency (Hz)
M=0/1/2/3/4/5
M=0/1/2/3/4/5
NFB
PFB
CPFB
Simulation Results
1.
1
1
1
1
PFB DAMP O
DAMP
PFB
DAMP
AA A
M G A
A
M G A
Positive Feedback Loop (PFB) Gain Control (2)
PFB gain control for enhancing pixel current settling (IDATA= 3uA, panel parasitic 2kOhm/ 60pF)
EECS, KAIST Circuit Design & System Application Laboratory
w/ PFB
Gain Control
I PIX
EL (
A)
0.0
1.0
2.0
3.0
5.0
6.0
7.0
8.0
4.0
Time (s)0 20 40
I PIX
EL (
A)
0.0
1.0
2.0
3.0
5.0
6.0
7.0
8.0
4.0
Time (s)0 20 40
w/o PFB
Gain Control
M = 5
4
3
2
1
Positive Feedback Loop (PFB) Gain Control (3)
PP-TCF Data Driver (7/15)
Simulated driving waveforms with/ without PFB gain control (IDATA= 1 to 5uA, panel parasitic 2kOhm/ 60pF)
EECS, KAIST Circuit Design & System Application Laboratory
PP-TCF Data Driver (8/15)
VDD
IDATA
AO
VREF1
M1 M2
M3 M4
IB IBCDP
OTA1
SinkCurrentControl
LoopGain
Control
ISINK1, 2 (t)1/g
m.D
TF
T
RDP RDP
CDP
DL with a Pixel Ckt. ADL
GND
CST
CurrentSense
M5
IB+
I TC
IB+
I TC
ITC ITC
IPIXEL
Complete push-pull function for output currents
Current Pulling Function for Enhancing Data Current Settlement (1)
EECS, KAIST Circuit Design & System Application Laboratory
PP-TCF Data Driver (9/15)
M3
M8
M9
RSENS
CSENS
Cu
rren
t Se
ns
eB
loc
k
P
I BIA
S
VDD
M3
M8 Cu
rren
t Se
ns
eB
loc
k
P
VDD
ISLEW
I BIA
S
Fast Current Sense Circuit Conv. Current Sense Circuit
Fast current sense block for current pulling operation
Current Pulling Function for Enhancing Data Current Settlement (2)
EECS, KAIST Circuit Design & System Application Laboratory
4.98A
Node Y
4.98A
Node Y
W/ Current Pulling W/O Current Pulling
60 nA
SCAN
PRC/ EQEN
0.4 / 0.6 / 0.8V
1.0V
1.2V
VPRC
0.4V0.6V
0.8V
1.0V
1.2V
No SubstantialDelays
Delays in Data Settlement
VPRC
Measurement results (1)
Pixel current settling times improved by current pulling function (IDATA transitions from 4.98uA to 60nA, VPRC= 0.4 to 1.2V, 0.2V step, panel parasitic 4kOhm/ 90pF)
PP-TCF Data Driver (12/15)
EECS, KAIST Circuit Design & System Application Laboratory
Measurement results (3)
Waveforms for various data current levels: High to low transitions and low to high transitions of data currents (data current = 20nA to 4.98uA, VPRC= 0.7V, parasitic load = 4kOhm/ 90pF)
SCAN
EQEN/ PRC
Node Y
4.98 A
Node Y
20 nA
20 nA
78 nA410 nA
1.02 A
3.01 A
78 nA
410 nA
1.02 A
3.01 A
4.98 A
VPRC = 0.7 V VPRC = 0.7 V
High to Low Transitions Low to High Transitions
6 s 6 s
DTFT in Deep Triode
PP-TCF Data Driver (14/15)
EECS, KAIST Circuit Design & System Application Laboratory
Performance summary
Appropriate for FHD AMOLED displays -Low power consumption -Stable operation at high data currents
Process 0.35 m CMOS (1P 4M)
Operation voltage 3.3 V
Data current range 20 nA to 4.98 A
Gray scale 8 bit (16.8 million colors)
Maximum driving load
(Panel parasitics)4 kW / 90 pF (Full-HD)
Settling time 6 s
Static current 4.5 A / Channel
Occupation area 60 308 m2 / 2 Channels
PP-TCF Data Driver (15/15)
EECS, KAIST Circuit Design & System Application Laboratory
Part IV
Real-time Image Sticking Compensation
using Current Driving
OLED Degradation
37
Differential aging dependent on sub-pixel. Prolonged display of static image (burn-in) RGB have different degradation curves.
Burn-in Discoloration
EECS, KAIST Circuit Design & System Application Laboratory
Conventional Image Sticking Compensation
<기존 전압 구동용 IS 보상회로>
TFT variation 문제를 해결하더라도, OLED 소자 자체의 시변 열화 특성으로 인
해 잔상(Image Sticking)효과를 유발.
OLED의 양단 전압이 열화에 따라 증가하는 현상을 이용한 Electrical Feedback
방식이 연구되고 있음.
기존 연구 방식들은 모두 전압 구동용 보상회로
EECS, KAIST Circuit Design & System Application Laboratory
OLED Degradation Sensing
<OLED degradation Sensing>
EECS, KAIST Circuit Design & System Application Laboratory
Real-time Compensation using Current Driving (2/7)
Compensation Method
using Voltage Driving
Real-time Compensation
using Current Driving
보상전류 별도의 큰 전류 작은 데이터 전류
열화 가속 Fast Slow
메모리
크기
Large
(Vth, , OLED)
기존의 1/3 이상 감소
(OLED)
보상시간 Long time Real time
IS 보상 방식 비교
EECS, KAIST Circuit Design & System Application Laboratory
Real-time Compensation using Current Driving (3/7)
1:2 DeMUX operation
Track and Hold type pixel
TCF driver
Current DAC with Reference Current Calibrator
Hybrid Data Driver
42
1. Read data-line voltage by ADC (OLED compensation) 2. Store by line voltage information of each pixel at memory 3. 1, VDAC & Amp. pre-charge data-line by pre-stored information. 4. 2, CDAC provides data current to pixel. (TFT compensation)
Data line
Block Diagram of Hybrid Data Driver
ADC10
DATA
Digital
Processing
Block
8
S/HΦ3
CDACΦ2
Φ1 Φ1
I-V
Converter
Φ1
Φ210 Latch
Stack
DATA1
DATA2
Hybrid Data Driver
S1
OLED
CS
M1
M4
M2
M3
VDD
S3
S2
Da
ta L
ine
PixelΦ1
row time
Φ2
Φ3
S1
S2
S3
frame time
Voltage
Driving
Current
Driving
Sampling
OLED Emission
VSR
IDATA1
(IDATA2)VL
CDAC sharing scheme VDAC = CDAC + I-V Converter DATA1 for voltage driving, DATA2 for current driving
EECS, KAIST Circuit Design & System Application Laboratory
Real-time Compensation using Dual Data Driving (3/4)
IDATA
IDATA
IREF VREF∙
Pre-charging voltage is made by using CDAC at each channel.
Implementation
Digital Processing Algorithm
Digital Processing Algorithm ADC
10
VL(new)-VL(init)
α-LUT
VL(new)
D VOLED
αα : degradation
percentage of OLED
VL(init)
VL(new)
DATA’
10
CDAC
2nd
Latch
1st
Latch
DATA1
Φ1
10
IDAC
VL
DATA2
Φ2
DATA’= x DATA100
100-α
DATA
10Gamma-LUT
DATA
8Memory for DATA’
DATA’10
: memory
DATA1 and DATA2 for hybrid data driving α-LUT for OLED compensation
Data Transition
Data driving waveforms for various current levels High current level (1uA~ 5uA, 1uA step)
Driving
Start
5A
1 : 5s
tS : settling time within 0.5LSB
1LSB = 5nAtS ≤ 5s
4A
3A
2A
1A1A
Data Transition
Data driving waveforms for various current levels Low current level (5nA~ 40nA)
Driving
Start
1 : 5s tS : settling time within 0.5LSB
1LSB = 5nA
2
10nA
5nA
error < 0.5LSB @ the end of 1
tS ≤ 5s
20nA
30nA
40nA
5nA
Parameter Variation with Degradation Rate
Changes of IDATA2 and ΔVOLED by compensation algorithm IDATA2 @ α=0% =100nA
Degradation Rate ()
0 10 20 30 40 50
VO
LE
D
0
100
200
300
400C
urr
en
t R
ati
o
0.0
0.5
1.0
1.5
2.0
IDATA2 @ α = 0
IDATA2
w/ compensation
w/o compensation
∆
EECS, KAIST Circuit Design & System Application Laboratory
Summary
Feedforward (TCF, ITCF, PP-TCF) drivers Full range of data currents from sub-10nA to 5A Various panel load condition from XGA to FHD-sized panel
Feedback (DFFC) driver Range of data currents from 10nA to 2.55uA WXGA-sized panel load of 1.5kOhm/ 100pF.
Real-time image sticking compensation methods Compensate the luminance degradation of OLEDs Compensate the variation of the driving TFT by current driving
Dept. of EECS,
Korea Advanced Institute of Science and Technology
Circuit Design & System Application Laboratory
KAIST
PMIC
Single-Inductor Multiple-Output (SIMO)
DC-DC Converters
51/115
Motivation (1)
Different blocks require different supplies
AMOLED display requires multiple supplies
Voltage Scheduling scheme for effective power
saving in digital circuit
Performance improvement in analog & mixed
signal systems
Why Multiple On-Chip supply ?
52/115
Background (1) – Boost converter and LDOs
EECS, KAIST Circuit Design & System Application Laboratory
Motivation (2)
Single inductor : fewer magnetic components, fewer
IC pins, lower cost, higher integration
Fewer on-chip power devices
Why SIMO converter ?
SIMO converter is a cost-effective solution !!
SIMO converter
53/115
EECS, KAIST Circuit Design & System Application Laboratory
1) Concept of Proposed OPDC
PCCM/DCM OPDC
energy transfer per 1 switching cycle 1 per 1 All per 1
# PI compensator # outputs 1
Output extension difficult easy
54/115
Existing PWM DC/DC Converters
• Output Voltage Feedback
• Output Cap. and IO affect the Loop Response
• Compensator Design is NOT EASY
Vref Gc (s) Controller
Vg Vo
L
RL
Switch
Network Io
55/35
EECS, KAIST Circuit Design & System Application Laboratory
SIMO converter with OPDC
Comparator control method
Only one PWM controller
Easy output extension and high power capacity
[Phuc.ISSCC2007, JSSC 2008]
56/115
EECS, KAIST Circuit Design & System Application Laboratory
SIMO converter with OPDC
4 Positive boosted outputs + 1 dependent negative output
57/115
EECS, KAIST Circuit Design & System Application Laboratory
Measurement Results (1) – Normal operation
DCM CCM
Boundary of DCM/CCM Boundary of DCM/CCM
58/115
EECS, KAIST Circuit Design & System Application Laboratory
Performance Summary
59/115
EECS, KAIST Circuit Design & System Application Laboratory
Boost converter
Adjustable charge-pump
2 inductors, 4 switches
Two PI-control
Bulky & Expensive
1 inductor, 3 switches
Cost effective
VOP : Comparator control
VON : PI-control
SIBO converter
2) Proposed SIBO converter
60/115
EECS, KAIST Circuit Design & System Application Laboratory
Implementation of SIBO converter
[Chae. ISSCC2007, JSSC 2009]
Modified Comparator Control (MCC) based on OPDC
61/115
EECS, KAIST Circuit Design & System Application Laboratory 62/115
VOP
control (Modified Comparator Control)
EECS, KAIST Circuit Design & System Application Laboratory
DCM operation CCM operation
IOP=ION=20mA @ Vg=3.7V
Freewheel switching
IOP=ION=35mA @ Vg=3.7V
No Freewheel switching
Measurement Results (1) – Normal operation
63/115
EECS, KAIST Circuit Design & System Application Laboratory
Performance Summary
64/115
65/115
3) Freewheeling Current Regulation
Vg
S
R
Q Ioffset
Gcf (s)
Vo
Vref
L
If
Vx
Q vnb
vn
Ifs
• Output Cap. and Load Current do NOT affect the Loop
• Compensator Design is EASY
Freewheeling Current Feedback
Output is Comparator-controlled
RL
Io
Ic
66/115
Pros and Cons
Control Scheme Loop
Dynamics Main Features
Direct Duty Control
w/ Output Voltage
Feedback
L, Co
- Complex Compensation
- Slow Response
Current Mode Control
w/ Output Voltage
Feedback
L, Co
- Difficulty in Compensation for a
Wide Load Range
Current Mode Control
w/ Freewheeling
Current Feedback
L, Co
+ Load Independent
+ Simple Wide-Bandwidth Control
- Power Switch for Freewheeling
- Small Decrease in Efficiency
67/115
Control of Multiple Output Converter
Vg
S
R
Q Ioffset
Gcf (s)
Vo1
Vref1
L
If
Vx
Q vnb
vn
Vo2
Vref2
Mn
Mf
Ifs
• No. of outputs can be increased easily
68/115
Measured Waveforms
Io
Vop
Vop,ac
IL
100mA
0A
Load Transient
Ts < 20µs Vpp < 100mV
69/115
Measured Waveforms
Vx
Vop
Von
IL
Iop = Ion = 23mA
Steady State
70/115
Measured Performance
Technology 0.5µm Power BiCMOS
Area 3.2mm2
Supply Voltage 3.7V nominal (2.7 ~ 4.5V)
Inductor / ESR 10µH / 350mW
Switching Frequency 1MHz
Filtering Capacitor 10µF Tantal // 470nF Ceramic
Maximum Efficiency 81% *
Load Transient
(No Load to 100mA) Vo,pp < 100mV, Ts < 20µs **
* 82.3% achieved in [Chae, ISSCC07].
** These values do not represent the best achievable results.
71/35
4) Vestigial Current Regulation
(Seol, ISSCC09)
Vo_xS1
+
- Vref1
EA+
-
+
-R
S
Q Vin+Vd
Vin
VA
(Vd=1V)
C2
L2
L1
D2
Sd
SfSn
Auxiliary Output VA Feedback
Output Cap. and IO affect the Loop Response(LIC)
Additional components are Needed
EECS, KAIST Circuit Design & System Application Laboratory
Implementation of Multiple Output Converter
• Vin: 2.8 ~ 4.5 V
• VR,G,B: 2 ~ 9 V
• VSP: Higher than VR,G,B by 0.5 V
(Lower limit 6.3V)
VDAC: Higher than VSP by 2V (Lower limit 8.3V)
72/115
EECS, KAIST Circuit Design & System Application Laboratory
Output switching control
Averaging of outputs by simultaneous switching
Discharging of inductor current by the averaged voltage
Enforced averaging effect by the charging sharing between outputs
Chaotic switching is alleviated by the averaging effect
Slightly different outputs
Simultaneous Turn on &Sequential Turn off
73/115
EECS, KAIST Circuit Design & System Application Laboratory
Measurements Results
Normal operating waveforms
<Step up> <Step down>
VIN=3.7V ,Ref_R,G,B=6V
VDAC VA
VR,G,B VGP
VA
VR
LX
IL
VIN=4.5V ,Ref_R,G,B=2V
VDAC VA
VR,G,B VGP
VA
VR
LX
IL
4.9V
6.0V
5.7V
2.0V
74/115
EECS, KAIST Circuit Design & System Application Laboratory
Performance Summary
fSW 1MHz
VDAC
VGP
VR,G,B
8 ~ 12V, 20mA
Process 0.5μm 1P3M BiCMOS
6 ~ 10V, 30mA
2 ~ 9.5V, 25, 25, 45mA
Accuracy 0.1 % [1.5%]*
Line regulation 0.05 %/V** [1.04%/V]
**VIN= 2.5 to 4.5 V
Load regulation 0.01 %/mA*** [0.015%/mA]
Efficiency 83 % **** [80%]
****@ VIN= 3.7 V, Ref=6, I_load=25_R, 25_G, 45_B,30_GP,10_DAC
***0mA to I_load @VIN= 3.7 V*[] result of [2]
75/115
76/35
5) Proposed Zero-Order Control
Vg
S
R
Q
VIC
Control
Vo
VREF L
Vx
Q
ΦN
RL
VIC
ΦN
ΦP UP
DOWN
VST
VISN
VOX
Mf
Mn
Loop response is independent of L & Co
If is Zero in steady-state : No decreasing Power Efficiency
Control Loop is Simple
Co
If
77/35
The Role of VST
• Make ΦP go to High even when deficient energy case
• VST causes small Offset Voltage – corrected by MCC
VISN
VIC
VO
(enlarged)
VOX
VREF
VREF
VST
ΦN
ΦP
ΦW
ID
IW
DOWN
UP
Excessive Energy Deficient Energy
VOX : 200mV
Larger than
VO’s Ripple
78/35
Pros(+) and Cons(-) - ZOC
Control Scheme Loop
Dynamics Main Features
FW Current
Control L, Co
- Extra Energy
- Power Switch for Freewheeling
- Decrease in Efficiency
Auxiliary Output
Voltage Control L, Co
+ Vestigial Current is returned
- Extra Energy
- Additional Components for VA
Zero-Order
Control L, Co
+ Balanced Energy
+ No Decrease in Efficiency
+ No Additional Components
79/35
Measured Waveforms
VX
VOUT
IL
Load = 60mA
No FW period
Steady State - CCM
80/35
Measured Waveforms
Load
IL
300mA 60mA
Load Transient
Vpp < 50mV
80µs 180µs
VOUT(AC)
6) PLL based SIMO buck converter
Switching frequency
- Constant
- High
Switch control
- Comparator control
- PMB control
Bang-bang control
- Stable
- Fast and accurate regulation
81/115
PMB Control (Vo6)
In-Phase Voltage information of error voltage is reproduced by error amplifier (EA).
Hysteresis comparator is implemented by the inverter and capacitor through the system delay.
PMB : PLL-based Multiple-Output Bang-Bang
82/115
Loop Analysis of the switching converter
83/115
Io1 = 22mA,
Io2 = 28mA,
Io3 = 32mA,
Io4 = 20mA,
Io5 = 19mA,
Io6 = 30mA.
Io1 =
100mA, Io2
= 130mA,
Io3 =
100mA,
Io4 =
130mA, Io5
= 127mA,
Io6 = 111mA.
Waveform at the Steady State
84/115
85/115
7) Proposed SIBBIF Converter (Architecture)
Hybrid Energy Transfer Media
Vg : Li-ion battery(2.7V ~ 4.5V), USB(5V)
VOP : 4.6V by boost or buck operation
VON : -5.4V by inverting flyback operation
L VOP
VON
S1
S2CF COP
CONS3
D1
D2
+
+
+
Vg
Calculated peak current comparison
0 50 100 150 200 250 3000.0
0.2
0.4
0.6
0.8
1.0
Pea
k I
nd
uct
or
curr
ent
(A)
Load Current (mA)
Previous SIBO Converter
Proposed SIBBIF Converter
L
iVVTi loadOPONS
SIBOpk
)(2_
L
iVVVTi
loadOPONgS
SIBBIFpk
)2(2_
86/115
0 50 100 150 200 250 300
60
65
70
75
80
85
Eff
icie
ncy
(%
)
Load Current (mA)
Proposed SIBBIF Converter
Previous SIBO Converter
Simulated efficiency comparison
Enhanced efficiency
87/115
88/115
Proposed SIBBIF Converter
Block Diagram
Peak current sensor
+ Artificial Ramp
(D>0.5)
+
-
Switch Control
Logic
Multi Level
Gate Driver
Oscillator
Pulse Skip
Logic
VgVOP (4.6V)
VON (-5.4V)
VREF
VREF
Hybrid Energy Transfer Media
Dead Zone
ETC
L
CF
SPM
SPA
SNM
COP
CON
CIN
DP
DN
AM OLED Pixel
Soft
start
OVP
VX1
Hybrid Fast
Transient
Control
||
Enhanced
Transient
PI control
+
Comparator
Control
VX2
89/115
Multi Level Gate Driver
MLGD is to reduce switching loss
To reduce the conduction loss, VGS is applied as large as
possible
It inevitably increases switching loss
VOP L
SNM
DP
V g
Vg
Vg
GND
2
1
Time
SggSW FVCP 2
)1(
SggSW FVCP 2)2
1()2( 2
Conventional Gate Driving
Multi Level Gate Driving
90/115
DN
VOP
VON
L
CF
SPM
SPA
SNMDP
V g
+
_V g
Multi Level Driving Voltages
Time
VON(-5.4V)
Gate voltage of SPM
VOP(4.6V)
Vg(3.7V)
GND
VON(-5.4V)
VOP(4.6V)
Vg(3.7V)
GND
Gate voltage of SPA
Time
Time
VON(-5.4V)
VOP(4.6V)
Vg(3.7V)
GND
91/115
Multi Level Gate Driver for SPM
Vg = 3.7V
Time
VON = -5.4V
GND
D1
VPM
Vg
VON
VON
IN
TD
TDVON
VOP
Vg
VPM
VX
CF
COP
CON
SPM
SPA
SNM
D1
MP4
MN2 MP5
MP6
MN3
Switch Size: SPM > SPA > SNM
92/115
Multi Level Gate Driver for SNM
Body bias of the MP1 and MP2
is selected as the largest
voltage between Vg and VOP
VOPVg
VBVB
VOP
Vg
Auto Body Bias Selector
VN1
VNM
MP1
MP2
VON(-5.4V)
VOP(4.6V)
Vg(3.7V)
GND
VNM
93/115
Measurement Results
VOP
VON
VX1
IL
Vg = 3.7V no load (Pulse skip) Vg = 3.3V load = 30mA (DCM)
Vg
VON+VgVOP
VON
VX1
Vg
VON+Vg
Vg = 4.2V load = 100mA (CCM)
VOP
VON
VX1
Vg = 5.0V load = 290mA (CCM)
VOP
VON
IL
94/115
Process 0.5m BCD 1P 3M
Supple voltage 2.7V to 4.5V & 5V(USB)
Frequency 1.25 MHz
Max efficiency 87.1 %@600mW
Output VOP VON
Line regulation 0.3 %/V 0.14 %/V
Load regulation 0.12V/A 0.2V/A
Output ripple 50mV@300mA 60mV@300mA
Max Power 3W
Voltage 4.6V -5.4V
Performance Summary
95/115
Summary
New topology about SIMO DC-DC Converter
– Cost effective solution
– AM-OLED Display application
– Focus on high stability
– Focus on high efficiency
New control method about SIMO DC-DC Converter
– Focus load independent stability
96/115
Thank You