JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.1, FEBRUARY, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/JSTS.2016.16.1.112 ISSN(Online) 2233-4866

Manuscript received Sep. 3, 2015; accepted Dec. 9, 2015 This work was partly supported by the IT R&D program of MOTIE/KEIT [10052653, Development of processing in memory architecture and parallel processing for data bounding application], and by the Basic Research Program through the National Research Foundation of Korea funded by the Ministry of Education under Grant 2013R1A1A2A10009535. This work was also supported by Samsung Electronics. Design tools supported by IDEC, KAIST 1 College of Information and Communication Engineering, Sungkyunkwan University 2 Hyun-Wook Lim was with College of Information and Communication Engineering, Sungkyunkwan University. He is now with Samsung Electronics E-mail : bskong@skku.edu

Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels

Hwan-Wook Park1, Hyun-Wook Lim2, and Bai-Sun Kong1

Abstract—This paper presents a half-rate current-integrating DFE receiver with sub-unit interval (sub-UI) inter-symbol interference (ISI) cancellation. By having a single additional DFE tap in each data path, the proposed DFE receiver can minimize BER degradation due to input pattern dependency and feedback tap latency problems in conventional current-integrating DFE receivers. The proposed DFE receiver was designed and fabricated in a 45 nm CMOS process, whose measurement results indicated that the BER bathtub width is increased from 0.235 UI to 0.315 UI (34% improvement) at 10-12 BER level. Index Terms—Decision feedback equalization, inter-symbol interference, current integration, multi-drop channel

I. INTRODUCTION

As the functionality and memory capacity of modern electronic systems are increasing, a multi-drop channel that connects multiple slaves to a single master has been widely used [1]. However, the high-frequency reflection

noise induced by impedance mismatch at channel branches and the inter-symbol interference (ISI) due to channel bandwidth limitation degrade signal integrity and worsen the eye opening, resulting in the degradation of maximum data rate. One effective way of overcoming the problem is to combine the techniques of current integration and decision-feedback equalization (DFE) [2]. The current integration at the receiver front averages out and removes high-frequency noise. The DFE cancels post-cursor ISIs without high-frequency noise enhancement. Although the current integration is very effective for eliminating the high-frequency noise, the integrator output may not provide with a sufficient integration amplitude when the input data changes at every cycle, resulting in BER degradation [3]. Moreover, the latency of the first feedback tap in the DFE may sacrifice the effective integration time, which lead to further reduction of integration amplitude [4].

Several approaches have been proposed to alleviate problems due to feedback tap latency and input pattern dependency [3, 5], but have their own demerits. Soft-decision method in [3] can alleviate the effect of the feedback latency, but should use a current-mode logic (CML) that causes high power consumption and cannot work as a high-sensitivity sampler. Moreover, CML is not compatible with traditional CMOS clocking. The sampled current-integrating summer employed can remove the input pattern dependency, but cannot eliminate high frequency noise because the integration is done for sampled data at specific time points. Moreover, the scheme suffers from the kickback noise from the sample-and-hold circuit, resulting in degraded signal integrity. Peaked integration method in [5] requires the continuous-time linear equalizer (CTLE) with high gain-

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boosting and the DFE with high tap coefficient values, which costs high power and area overhead in addition to a high distortion on integrator input signal.

In this paper, a new current-integrating DFE receiver with sub-UI ISI cancellation is proposed to address BER degradation originated from the input pattern dependency and the feedback tap latency of conventional current-integrating DFE receivers. Section 2 explains the problems of conventional current-integrating DFE. Section 3 presents the architecture and operation of the proposed sub-UI ISI cancellation-based current-integrating DFE receiver. The experimental results are presented in Section 4, followed by the conclusion in Section 5.

II. CONVENTIONAL HALF-RATE CURRENT-INTEGRATING DFE

Fig. 1(a) shows the block diagram of the conventional current-integrating DFE receiver [5]. Continuous-time linear equalizer (CTLE) equalizes channel output ch(t) into proper signal with less ISI. Gain-controlled amp, whose output x(t) enters DFE to remove residual ISI, manages the gain to provide sufficient amplitude at integrator outputs. The DFE has a half-rate configuration that samples even data at the rising edge of CLK and odd data at the falling edge of CLK. Differential input, xd(t), coming from the gain control amp is summed with feedback taps and integrated by integrators at even and odd signal paths. Resulting integrator outputs, se(t) and so(t), are sampled by sense amplifiers. The latched decision outputs from sense amplifiers are used as the first taps, and SR latch outputs work as the second taps. The third taps are from the final latch outputs.

Critical drawbacks of the conventional current-integrating DFE receiver originate from input pattern dependency and non-zero feedback tap latency that collectively prevent a full cancellation of ISI. To investigate this issue, let us consider the case in which the transmitted data is transitioning at every cycle, resulting in a sinusoidal wave-like waveform on the channel, as shown in Fig. 1(b). Then, the integrators in Fig. 1(a) that integrate this shape of incoming channel waveform will have their outputs with degraded amplitudes (see VMIN in Fig. 1(b)). (Note that, if the channel data have no transition, the channel waveform

will be flat, resulting in a maximum integrator output amplitude). On top of that, the feedback taps data for cancelling the first post-cursor ISI become available after tD1+tD2 due to the latencies of the sense amplifier (tD1) and the current D/A converter (tD2). So, the first post-cursor ISI cannot be fully removed, resulting in further degradation of integrator output amplitude. Lower

ò

ò

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Fig. 1. (a) Architecture of the conventional current-integrating DFE receiver, (b) timing diagram with channel data transitioning every cycle.

114 HWAN-WOOK PARK et al : CURRENT-INTEGRATING DFE WITH SUB-UI ISI CANCELLATION FOR MULTI-DROP CHANNELS

amplitudes at integrator outputs due to these effects will apparently cause a degraded BER performance.

III. PROPOSED HALF-RATE CURRENT-INTEGRATING DFE WITH SUB-UI ISI

CANCELLATION

The architecture of the proposed half-rate current-integrating DFE with sub-unit interval (sub-UI) ISI cancellation is shown in Fig. 2(a). For eliminating the residue ISI due to input pattern dependency and feedback tap latency, it has one more DFE tap in each data path starting at 0 UI and ending at 0.5 UI, which is implemented by an additional sense amplifier and current DAC. These added DFE taps are controlled by a pair of CLKPRE/CLKPREB, 0.5 UI faster than CLK/CLKB pair. Pre-decision data, DPREdo(t), generated in the odd data path at the rising edge of CLKPREB, is fed into the DFE summer through CPRE and C1 in the even data path. Hence, for the first half of UI, CPRE+C1 are enabled whereas, for the second half, C1 is only enabled, as indicated by the timing diagram with the channel data transitioning every cycle in Fig. 2(b). The feedback tap latency issue of the conventional DFE receiver is resolved by C1 activated as soon as the associated UI starts to begin. The input pattern dependency during the first half of the UI is also eliminated by CPRE activated only during the front period. As a result, the integrated amplitude obtained at the integrator output becomes higher for the same ISI as compared to the conventional DFE receiver, leading to a better BER performance.

Fig. 3 shows a detailed circuit diagram for DFE summing with ordinary and pre DFE taps for the even data path of the proposed DFE receiver. It consists of a current summer and integrator input stage with gain

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Fig. 2. (a) Proposed half-rate current-integrating DFE with sub-UI ISI cancellation, (b) timing diagram with channel data transitioning every cycle.

Fig. 3. Detailed circuit diagram for gain control and DFE summing with ordinary and pre DFE taps for even data path.

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control capability and four current DFE taps including pre-decision tap. In order to divide one UI integration period into two parts, TAPPRE and TAP1 circuits are merged such that, CPRE and C1 are identically activated with CLKB, and CPRE is deactivated with CLKPREB whereas C1 remains active during the whole UI. TAP2 and TAP3 also perform integration during the entire UI period.

IV. PERFORMANCE EVALUATION

The proposed current-integrating DFE was designed in a 45 nm LP process. Simulated waveforms of integrator differential outputs for the conventional DFE and the proposed DFE when the feedback tap latency (tD) is equal to 0.65UI are depicted in Fig. 4. The simulation was done with 1.1-V supply voltage. Fig. 4(a) shows the waveforms of the integrator outputs for the conventional DFE, where the worst-case integrated output voltage difference is found to be 134.2 mV. Fig. 4(b) shows the waveforms of the integrator outputs for the proposed DFE with sub-UI ISI cancellation, where the worst-case integrated output voltage difference increases to 180.0 mV, and indicates 34% improvement in terms of eye-opening.

To assess the performance, the proposed current-integrating DFE was fabrication by the same process, whose design parameters are summarized in Fig. 5(a). The test chip integrates the entire receiver circuits and BER checker running with PRBS7 pattern generator for BER measurement. CTLE block receives the channel output, and is optimized to remove fourth and the latter post-cursor ISI along with pre-cursor ISI. The ISI caused by the first, second and third post cursors are removed mainly by the DFE. Gain control signal has 5 bits, and CPRE/C1 and C2/C3 are controlled by 6 and 5 bits, respectively. Offset is also removed by 5-bit coefficient of offset canceller. Load capacitances are 200 fF for even and odd paths. Clock receiver uses a digitally controlled variable delay line. External clock is sent to the clock receiver where CLK/CLKB and CLKPRE/CLKPREB are generated for use as the integrating and sampling clocks. Delay is controlled by 10-bit digital code to generate 0.5 UI phase between CLKPRE and CLK. The photograph of the fabricated chip is shown in Fig. 5(b), whose layout area is 61,353 μm2.

Fig. 6(a) describes the environment for test chip evaluation. PRBS7 data pattern is used for the evaluation. From the transmitter, a 10-inch differential FR4 channel is combined with a 4.72-inch channel having stubless 2

134.2mV

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Fig. 4. Integrator differential output waveforms (tD=0.65UI): (a) conventional DFE, (b) proposed DFE.

Process Samsung 45nm LP Power Supply 1.1V

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Fig. 5. (a) Design summary, (b) photomicrograph of the test chip.

116 HWAN-WOOK PARK et al : CURRENT-INTEGRATING DFE WITH SUB-UI ISI CANCELLATION FOR MULTI-DROP CHANNELS

drops at equal distance. The parasitic resistance and capacitance of the channel are 10.48 Ohm and 121.3 pF per meter with 15 dB loss at 4.5 Gbps. Each drop of the channel is terminated by on-chip termination. The first drop was chosen to monitor BER because the signal integrity is worse at the first drop than at the second drop located at the far-end of the channel. BER is measured by a built-in BER checker synchronized with received data pattern. DFE tap coefficients were manually optimized by monitoring BER results at an operating speed of 4.5 Gbps. With a varying external CLK phase, BER bathtub curves of the test chip at the first drop position is presented in Fig. 6(b). The measurement result indicates that the proposed current-integrating DFE with sub-UI ISI cancellation has shown to improve BER performance by 34% (bathtub width enlarged from 0.235 UI to 0.315 UI) at 10-12 BER level. The overhead in terms of power consumption to implement the proposed sub-UI ISI equalization is estimated to be about 23%.

V. CONCLUSIONS

A new half-rate current-integrating DFE with sub-UI ISI cancellation is proposed. The high-frequency reflection noise in multi-drop channel and the input pattern dependency of the conventional current-integrating DFE have been effectively alleviated by the proposed DFE with sub-UI ISI cancellation. The BER performance of the proposed DFE is enhanced by 34% at 10-12 BER level at 4.5 Gbps.

REFERENCES

[1] Y. Yoon, et al., “A multidrop bus design with resistor-based impedance matching on nonuniform impedance lines,” IEEE TCAS-I, vol.58, no.6, pp.1264 –1276, June 2011

[2] Seung-Jun Bae, et al., “A 2-Gb/s CMOS integrating two-tap DFE receiver for four-drop single-ended signaling,” IEEE TCAS-I, vol.56, no. 8, pp.1645–1656, 2009

[3] T. O. Dickson, et al., “A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology,” IEEE JSSC, vol.44, no. 4, pp.1298–1305, 2009

[4] L. Chen, et al., “A scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS,” IEEE ISSCC, pp.180 –181, Feb. 2009

[5] J. F. Bulzacchelli, et al., “A 28-Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32-nm SOI CMOS technology,” IEEE JSSC, vol.PP, no. 99, p.1, Dec. 2012

Hwan-Wook Park received the B.S. and M.S. degrees in electronics engineering from Kyungpook National University and Korea Advanced Institute of Science and Technology (KAIST), Korea, in 1999 and 2001, respectively. He joined

Samsung Electronics in 2005 and is currently working for the high-speed memory testing and design for testability. He is currently working toward the Ph.D. degree in Sungkyunkwan University.

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Fig. 6. (a) Test environment, (b) bathtub curve of the test chip.

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Hyun-Wook Lim received the B.S. and M.S. degrees in Electrical Engineering from Korea University, Korea, in 1996 and 1998. He joined Samsung Electronics, Korea, in 1998, where he has been involved in DRAM and display interface design.

He is currently working toward the PhD. degree in Semiconductor and Display Engineering from Sungkyun- kwan University.

Bai-Sun Kong received the B.S. degree in electronics engineering from Yonsei University, Seoul, Korea, in 1990, and the M.S. and the Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST),

Taejon, Korea, in 1992 and 1996, respectively. From 1996 to 1999 he was with LG Semicon (currently SK-Hynix), Seoul, Korea, as a senior design engineer, where he was working on the design of high-density and high-bandwidth DRAMs. In 2000, he joined the faculty of Korea Aerospace University, Goyang, Korea, as an assistant professor at the School of Electronics Telecommunication and Computer Engineering. In 2005, he moved to Sungkyunkwan University, Suwon, Korea, where he is currently a professor at the College of Information and Communication Engineering. His research interests include high-performance microprocessor/ memory architecture/circuit designs, high-speed I/O transceiver design, and IC designs for low-power/high-speed applications.