Cts Design

7/29/2019 Cts Design

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Clock optimization techniques for abutted channelless floorplanningmethodologies

1) splitting the output clock port of a central clock generator module

Let's say that there are 5 toplevel modules and all of them are defined as partitions (central_partition, above_partition, left_partition, below_partition, right_partition ).

The floorplan is done in such a way that the central_partition is abutted to one of the other ones oneach side. The central_partition module has an output port 'tnyclko' that is driving the input ports'tnyclki' of the other partitioned modules.

This net is a clock net and as such a clock tree will be built on top of it.

A port splitting utility have been developed in order to split the port tclko into 4: tclko_above,tclko_below, tclko_left, tclk_right. tclk_above will drive the tclki port of partition_above, tclk_belowwill drive the tclki port of partition_below, and so on so forth.

See next pages for scenario examples.


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Before splitting the clock output port ( assume the channel width is zero)

mod5

mod6

mod2

Clock generator

( mod1 )

mod3

mod4

clkout

There are 6 hinstances at the toplevel.

Each of them will be turned in a hardblock. The clock generator module is

feeding the clock signal to the other ones.

Internally to the clock generator thebuffer that is driving clkout is drivingother flops as well

At the toplevel there would be a netclknet connecting:

Hinst2/clkin, hinst3/clkin, hinst4/clkin,hinst5/clkin, hinst6/clkin, hinst1/clkout

Inside module 1 there would be a netclknet connecting :

Clkout, clkbuf/Z, flop1/CK, ,flopN/CK

clkin

clkin

clkin

clkin

clkin

clknet

clknet


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After splitting the clock output port

The split port feature should generate 4 moreclock output ports ( clkout[2-5]).

A a result, the top level connectivity wouldchange as follows:

the net clknet would now connect onlyhinst6/clkin, hinst1/clkout

Net clknet2 : hinst2/clkin, hinst1/clkout2




Inside module 1 there would be a net clknet connecting :Clkout, clkout[2-5]), clkbuf/Z, flop1/CK, ..,flopN/CK

After running cts for the peripheral modulesthe macro model definition can be attachedto the clock generator output port andeventually the clock tree for the centralmodule can be built

mod5

mod6

mod2

mod3

mod4

clkout

clkin

clkin

clkin

clkin

clkin

clknet

clknet3

clkout3

clknet4

clknet5

clknet

clknet2

clkout4

clkout2

clkout5


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Clock optimization techniques for abutted channelless floorplanningmethodologies

2) H tree push down

Encounter 3.3 has the possibility of pushing down special routing made on a flat toplevel design.If a piece of routing crosses a boundary of a partition a physical equivalent pin is created, unlessthe partition is connected to the net and the wire crosses the boundary only once

For example if the clock input pin in partition A is called CLK1_OUT and the wire crosses the ptn Aboundary 3 times the PIN section of the block level def would look like:

- CLK1_OUT + NET CLK1_OUT + SPECIAL + DIRECTION OUTPUT + USE SIGNAL+ LAYER Metal3 ( -2000 -240 ) ( 2000 240 ) + FIXED ( 71440 74116 ) W ;

- CLK1_OUT.extra1 + NET CLK1_OUT + SPECIAL + DIRECTION OUTPUT + USE SIGNAL+ LAYER Metal4 ( -2000 -240 ) ( 2000 240 ) + FIXED ( 29216 240 ) N ;

- CLK1_OUT.extra2 + NET CLK1_OUT + SPECIAL + DIRECTION OUTPUT + USE SIGNAL+ LAYER Metal3 ( -2000 -240 ) ( 2000 240 ) + FIXED ( 59120 17650 ) W ;

This feature can be used to build a H tree at the toplevel in a semiautomatic way and then push it down inside eachblock, so that the first level of the clock tree has a even delay to each termination point across the whole chip.Each termination point can be hooked up to a buffer and the block level clock tree built using such buffer as theclock source


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Example of H tree at the toplevel

CLK1_OUT.extra1

CLK1_OUT.extra2

CLK1_OUT

CLK1_OUT.extra3

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Cts Design