CSEE 3827: Fundamentals of Computer Systemsmartha/courses/3827/sp09/slides/lecture6.pdf · CSEE 3827: Fundamentals of Computer Systems Lecture 6 February 9, 2009 Martha Kim [email protected]

CSEE 3827: Fundamentals of Computer Systems

Lecture 6

February 9, 2009

Martha [email protected]

mailto:[email protected]

mailto:[email protected]

CSEE 3827, Spring 2009 Martha Kim

Combinational circuits

• Combinational circuits are stateless

• The outputs are functions only of the intputs

2

Combinational circuit OutputsInputs


Sequential circuits

• Sequential circuits have state

• The outputs are functions of both the current inputs and the current state of the circuit

3

Sequential circuit

OutputsInputs Combinational circuit

Storage elements

next state

current state


Design procedure

1.Specification

(define desired behavior)

2.Formulation

(derive a truth table or boolean equations that relate outputs to inputs)

3.Optimization

4.Technology Mapping

(transform circuit to use available gates (e.g., NANDs))

5.Verification

(verify that final design behaves correctly)

4


Hierarchical design

5

© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e

3-4

(a)

A0 N0MX

MX

MX

MX

ME

N1

N2

N3

E

B0

A1

B1

A2

B2

A3

B3

Ai

Ni

MXBi

N0N1 E

MEN2N3

(b) (c)

(4-bit equality comparator)

Enabling


Enabled circuits

7


3-15

XF

EN

(a)

ENX

F

(b)

Output is enabled only when input ‘ENABLE’ signal is asserted


Enabling example: Car control

• Inputs:

• IG (ignition switch)

• LS (light switch)

• RS (radio switch)

• WS (power window switch)

8

• Outputs

• L (lights)

• R (radio)

• W (power windows)

What are the enabling relationships?

What is the truth table for this system?

Decoding


Decoder (1:2)

10

Converts n-bit input to m-bit output, where n <= m <= 2n


3-17

A D0 D1

0 1 01 0 1

(a) (b)

D1 AA

D0 A


Decoder (2:4)

11

n


3-18

A1

0011

A0

0101

D0

1000

D1

0100

D2

0010

D3

0001

(a)

D0 A1 A0

D1 A1 A0

D2 A1 A0

D3 A1 A0

(b)

A1

A0


Decoder (3:8)

12


3-19

3-to-8 Line decoder

1-to-2-Line decoders

4 2-input ANDs 8 2-input ANDs

2-to-4-Linedecoder

D0A0

A1

A2

D1

D2

D3

D4

D5

D6

D7

Hierarchical design: use small decoders to build bigger decoder


Decoder-based circuits

• If decoders produce minterms...

13

3:8decoder

AB

C

‘A’B’C‘A’BC‘AB’C‘ABCA’B’CA’BCAB’CABC

Encoding


Encoders

15

Inverse of a decoder: converts m-bit input to n-bit output, where n <= m <= 2n


T 3-7

TABLE 3-7Truth Table for Octal-to-Binary Encoder

Inputs Outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

00000001

00000010

00000100

00001000

00010000

00100000

01000000

10000000

00001111

00110011

01010101


Encoders

16

Inverse of a decoder: converts m-bit input to n-bit output, where n <= m <= 2n


T 3-7

TABLE 3-7Truth Table for Octal-to-Binary Encoder

Inputs Outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

00000001

00000010

00000100

00001000

00010000

00100000

01000000

10000000

00001111

00110011

01010101


Priority Encoder

17


T 3-8

Inputs Outputs

D3 D2 D1 D0 A1 A0 V

00001

0001X

001XX

01XXX

X0011

X0101

01111

TABLE 3-8Truth Table of Priority Encoder

Code conversion


General code conversion

19


3-3

(a) Segment designation

a

bf

e cg

d(b) Numeric designation for display

Multiplexers


Multiplexers

• Combinational circuit that selects binary information from one of many input lines and directs it to one output line

21

(2 inputs)n

(n selection bits)

(1 output)


Truth table for a 4:1 mux

22

i0i1i2i3

s1 s0

o


Internal mux organization

23


3-26

S1Decoder

S0

Y

S1Decoder

S0

Y

S1Decoder

4 2 AND-ORS0

Y

I2

I3

I1

I0


Multibit multiplexing

24

Documents

CSEE 3827: Fundamentals of Computer Systemsmartha/courses/3827/sp09/slides/lecture6.pdf · CSEE 3827: Fundamentals of Computer Systems Lecture 6 February 9, 2009 Martha Kim [email protected]