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CS/ECE755 VLSI Design Prof. Karu Sankaralingam TA: Jungseob Lee Instruction to change technology library from 350nm to 180nm for miniproject1 (from NCSU_Techlib_tsmc04_4M2P to NCSU_Techlib_tsmc02d) I think most of you already started schematic design and simulation. This instruction is for those who already made some cell views and symbols. If you didn’t make so much cell view or symbols, it might be better to start design with new schematic and layout editing tutorials on web pages. For the new cell view and future project, please follow the new tutorials also. If you already start to draw layouts, please let professor Karu and me know how you proceed for layout design. 1. Library change 1) We are trying to change library files to newer technology (from 350nm to 180nm). The new library name is NCSU_Techlib_tsmc02d. Please don’t confuse with tsmc02. The NCSU_Techlib_tsmc02d is already installed in CAE.

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Page 1: CS/ECE755 VLSI Design

CS/ECE755 VLSI Design Prof. Karu Sankaralingam

TA: Jungseob Lee

Instruction to change technology library from 350nm to 180nm for miniproject1

(from NCSU_Techlib_tsmc04_4M2P to NCSU_Techlib_tsmc02d)

I think most of you already started schematic design and simulation. This instruction is for those who already made some cell views and symbols. If you didn’t make so much cell view or symbols, it might be better to start design with new schematic and layout editing tutorials on web pages. For the new cell view and future project, please follow the new tutorials also. If you already start to draw layouts, please let professor Karu and me know how you proceed for layout design. 1. Library change 1) We are trying to change library files to newer technology (from 350nm to 180nm). The new library name is NCSU_Techlib_tsmc02d. Please don’t confuse with tsmc02. The NCSU_Techlib_tsmc02d is already installed in CAE.

Page 2: CS/ECE755 VLSI Design

2) Most of your working library’s name would be cs755 or csece755. Please select the working library. In this instruction, the working library is cs755.

3) Go to Edit properties.

Page 3: CS/ECE755 VLSI Design

4) Change techLibName to ‘NCSU_TechLib_tsmc02d’

2. Schematic Editing part 1) Open all the basic cell views which you made so far. You don’t need to change anything in symbol view because symbol is based on cell view. If you change the library for cell view, it automatically effects to every symbol which is using the cell views. Following schematic is inverter cell view. Click the PMOS and type ‘q’ which is short key of property.

Page 4: CS/ECE755 VLSI Design

2) You will see Edit object properties of PMOS. Change Model name to ‘tsmc18dP, Width to ‘540n’, Length to ‘180n’.

Page 5: CS/ECE755 VLSI Design

3) For NMOS, change Model name to ‘tsmc18dN’, Width to ‘270n’, Length to ‘180n’.

4) These PMOS, NMOS property change must be done for every mosfet in all your cell views. Don’t change property individually. Make modified PMOS and NMOS pair, and then duplicate the modified PMOS and NMOS by copy command. Short-key for copy is ‘C’.

Page 6: CS/ECE755 VLSI Design

2. Simulation part On simulation part, most steps are same with ones in previous tutorial except following. 1) Model library setup Open ‘virtuoso analog design environment’. After change simulator to ‘spectre’, go to setup model libraries. Browse and add ‘modelfile18’ from the directory downloaded the modelfile18. You can download the file from course webpage. http://pages.cs.wisc.edu/~karu/courses/cs755/fall2008/wiki/index.php/Main/Tools You don’t need to add tsmc35N.m and tsmc35P.m anymore.

Page 7: CS/ECE755 VLSI Design

2) Simulation stimuli change In 180nm technology, we need to use lesser Vdd and assume lesser rising and falling transition time. Go to setup stimuli and change Vmax from 3.3 to 1.8, rinsing & falling time from 0.1n to 0.05n. Also set up Global Sources(Vdd) to 1.8 DC voltage. Also new Threshold voltage is Vdd/2 = 0.9 (V) for delay calculation by calculator.