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ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected])
Tutorial FTL
Prof. Jinkyu Jeong ([email protected])
TA -- Minwoo Ahn ([email protected])
TA -- Donghyun Kim ([email protected])
Computer Systems Laboratory
Sungkyunkwan University
http://csl.skku.edu
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 2
Contents
• Deep dive to the Jasmine
– NAND flash memory
• NAND flash memory configuration
• NAND flash memory layout
– Flash memory abstraction in Jasmine
– Flash interface layer in Jasmine
• NAND flash controller
• Intro. to Tutorial FTL
– Read / Write in Tutorial FTL
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected])
Deep Dive to the Jasmine
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 4
NAND Flash Memory
• K9LCG08U1M (Dual die)
– Samsung 35 nm 2-bit MLC flash
– Configuration
• 16 sectors per page (8 KB + 640 B)
• 128 pages per block (1 MB + 80 KB)
• 4096 + 56 blocks per die
– Average performance
• Page read : 250 us
• Page program : 1.3 ms
• Block erase : 1.5 ms
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 5
NAND Flash Memory(cont’d)
0
1
2
…
127
Data (8KB) Spare (640B)
Block (1MB + 80KB)
Page (8KB + 640B)
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 6
NAND Flash Operations
• Page read
– Cell -> Page Buffer -> RAM
• Page program
– RAM - > Page Buffer -> Cell
• Page copy-back
– Cell (src) -> Page Buffer -> Cell (dst)
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 7
NAND Flash Physical Layout
Ch A/B
Bank 0(4)
Ch C/D
Bank 3(7)
Ch A/B
Bank 2(6)
Ch C/D
Bank 1(5)
Ch A/B
Bank 1(5)
Ch A/B
Bank 3(7)
Ch C/D
Bank 2(6)
Ch C/D
Bank 0(4)
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 8
NAND Flash Logical Layout
• Four channels + eight banks in each channel8 way
4 c
han
nel
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 9
NAND Flash Logical Layout(cont’d)
• Channel
– Banks in same channel share I/O bus
• Only single I/O operation per a channel
• Bank
– 16 bit I/O bus
– High / Low die (dual die)
– Each bank can perform cell operations in parallel
• Internal operations not using I/O bus can run parallel
– Barefoot has only 4 R/B signal inputs per channel
• (0,4) (1,5) (2,6) (3,7) chip binding in a same channel
• Maximum 4 way interleaving
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 10
Flash Memory Abstraction
• Bank interleaved operation (dual die)
– Example
• DRAM buffer data = 01 23 45 67 89 AB CD EF 01 … (512 bytes)
• ‘Low’ chip <- 01 45 89 CD 01 … (256 bytes)
• ‘High’ chip <- 23 67 AB EF … (256 bytes)
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 11
Flash Memory Abstraction(cont’d)
• 2-plane mode
– 00 11 22 33 …………………………… 88 99 AA BB
……………………….
Die 0 (Low) Die 1 (High)
Plane 0 Plane 1 Plane 0 Plane 1
... ... ... ...
88 AA .. 99 BB ..11 33 ..00 22 ..
16KB 16KB
Row0
Bank
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 12
NAND Flash Controller
• To issue NAND flash operation
– include/flash.h
FC_COL_ROW_READ_OUT
FC_COL_ROW_IN_PROG
FC_COPYBACK
FO_P
FO_E
FO_B_SATA_W
FO_B_SATA_R
Registers Offset
FCP_ISSUE 87
FCP_CMD_ID 86
FCP_DST_ROW_H 85
FCP_DST_ROW_L 84
FCP_DST_COL 83
FCP_ROW31_H 82
FCP_ROW31_L 81
… …
FCP_ROW0_H 20
FCP_ROW0_L 19
FCP_COL 18
FCP_DMA_CNT 17
FCP_DMA_ADDR 16
FCP_OPTION 15
FCP_BANK 14
FCP_CMD(FCP_BASE) 13
WR_BANK 12
WR_STAT 11
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 13
NAND Flash Controller (cont’d)
• To issue NAND flash operation
– include/flash.h
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 14
Dive to the code: FCP Setting
void nand_page_ptread_to_host(UINT32 const bank, UINT32 const vblock,UINT32 const page_num, UINT32 const sect_offset, UINT32 const num_sectors){…
row = (vblock * PAGES_PER_BLK) + page_num;
SETREG(FCP_CMD, FC_COL_ROW_READ_OUT);SETREG(FCP_DMA_ADDR, RD_BUF_PTR(g_ftl_read_buf_id));SETREG(FCP_DMA_CNT, num_sectors * BYTES_PER_SECTOR);
SETREG(FCP_COL, sect_offset);#if OPTION_FTL_TEST == TRUE
SETREG(FCP_OPTION, FO_P | FO_E);…
SETREG(FCP_ROW_L(bank), row);SETREG(FCP_ROW_H(bank), row);
g_ftl_read_buf_id = (g_ftl_read_buf_id + 1) % NUM_RD_BUFFERS;
…flash_issue_cmd(bank, RETURN_ON_ISSUE);
}
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 15
Dive to the code: FCP Issue
void flash_issue_cmd(UINT32 const bank, UINT32 const sync){
UINT32 rbank = REAL_BANK(bank);
SETREG(FCP_BANK, rbank);
while ((GETREG(WR_STAT) & 0x00000001) != 0);
SETREG(FCP_ISSUE, NULL);
if (sync == RETURN_ON_ISSUE)return;
while ((GETREG(WR_STAT) & 0x00000001) != 0);
if (sync == RETURN_ON_ACCEPT)return;
while (_BSP_FSM(rbank) != BANK_IDLE);}
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 17
Tutorial FTL: Overview
• ./ftl_tutorial
– ftl.c, ftl.h
• Page Mapping FTL
– Write data from DRAM to NAND
– Read data from NAND to DRAM
– No garbage collection
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 18
Tutorial FTL: Page Mapping Table
• LPN to PPN map
– LPN (Logical Page Number)
= LBA (from host) / Sectors per Page
– PPN (Physical Page Number)
Index (=LPN) 0 1 2 3 … 209715
Value (=PPN) 100 256 0 INVALID … 20000
ICE3028: Embedded System Design, Fall 2018, Jinkyu Jeong ([email protected]) 19
Assignment
• Describe functions in target_spw/flash_wrapper.c within
three sentences
– functions
• nand_page_read
• nand_page_program
– Send it to [email protected]
– Due: Until next lab class
