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VGS - Gate-to-Source Voltage (V)
RD
S(o
n) -
On-
Sta
te R
esis
tanc
e (m:
)
0 2 4 6 8 10 12 14 16 18 200
1
2
3
4
5
6
7
8
D007
TC = 25°C, I D = 30 ATC = 125°C, I D = 30 A
Qg - Gate Charge (nC)
VG
S -
Gat
e-to
-Sou
rce
Vol
tage
(V
)
0 5 10 15 20 25 30 35 40 45 50 550
2
4
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8
10
D004
ID = 30 AVDS = 20 V
1 D
2 D
3 D
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D5G
6S
7S
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P0093-01
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD18502Q5BSLPS320B –NOVEMBER 2012–REVISED MAY 2017
CSD18502Q5B 40 V N-Channel NexFET™ Power MOSFET
1
1 Features1• Ultra-Low Qg and Qgd
• Low Thermal Resistance• Avalanche Rated• Logic Level• Pb-Free Terminal Plating• RoHS Compliant• Halogen-Free• SON 5 mm × 6 mm Plastic Package
2 Applications• DC-DC Conversion• Secondary Side Synchronous Rectifier• Motor Control
3 DescriptionThis 40-V, 1.8-mΩ, 5 mm × 6 mm NexFET™ powerMOSFET is designed to minimize losses in powerconversion applications.
Top View
Product SummaryTA = 25°C TYPICAL VALUE UNIT
VDS Drain to source voltage 40 V
Qg Gate charge total (4.5 V) 25 nC
Qgd Gate charge gate to drain 8.4 nC
RDS(on) Drain to source on resistanceVGS = 4.5 V 2.5 mΩ
VGS = 10 V 1.8 mΩ
VGS(th) Threshold voltage 1.8 V
Ordering Information(1)
DEVICE QTY MEDIA PACKAGE SHIP
CSD18502Q5B 2500 13-Inch Reel SON 5 mm × 6 mmPlastic Package
Tape andReelCSD18502Q5BT 250 7-Inch Reel
(1) For all available packages, see the orderable addendum atthe end of the datasheet.
Absolute Maximum RatingsTA = 25°C VALUE UNIT
VDS Drain to source voltage 40 V
VGS Gate to source voltage ±20 V
ID
Continuous drain current (package limited) 100
AContinuous drain current (silicon limited), TC= 25°C 204
Continuous drain current(1) 26
IDM Pulsed drain current(2) 400 A
PDPower dissipation(1) 3.2
WPower dissipation, TC = 25°C 156
TJ Operating junction temperature –55 to 150 °C
Tstg Storage temperature –55 to 150 °C
EASAvalanche energy, single pulseID = 88 A, L = 0.1 mH, RG = 25 Ω 387 mJ
(1) Typical RθJA = 40°C/W on a 1 inch2 , 2 oz. Cu pad on a 0.06inch thick FR4 PCB.
(2) Max RθJC = 0.8°C/W, pulse duration ≤100 μs, duty cycle ≤1%
RDS(on) vs VGS Gate Charge
2
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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 35.2 Thermal Information .................................................. 35.3 Typical MOSFET Characteristics.............................. 4
6 Device and Documentation Support.................... 76.1 Receiving Notification of Documentation Updates.... 7
6.2 Community Resources.............................................. 76.3 Trademarks ............................................................... 76.4 Electrostatic Discharge Caution................................ 76.5 Glossary .................................................................... 7
7 Mechanical, Packaging, and OrderableInformation ............................................................. 87.1 Q5B Package Dimensions ........................................ 87.2 Recommended PCB Pattern..................................... 97.3 Recommended Stencil Pattern ................................. 97.4 Q5B Tape and Reel Information ............................. 10
4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2015) to Revision B Page
• Added Receiving Notification of Documentation Updates section. ....................................................................................... 7• Changed the dimension between pads 3 and 4 from 0.028 inches: to 0.050 inches in the Recommended PCB
Pattern section diagram ......................................................................................................................................................... 9
Changes from Original (November 2012) to Revision A Page
• Added part number to title. .................................................................................................................................................... 1• Added 7-inch reel to Ordering Information. ........................................................................................................................... 1• Added power dissipation at TC = 25°C to Absolute Maximum Ratings. ................................................................................ 1• Updated pulsed drain current conditions in Absolute Maximum Ratings. ............................................................................. 1• Updated Figure 1 to normalized RθJC curves. ........................................................................................................................ 4• Updated SOA in Figure 10. ................................................................................................................................................... 6• Added Community Resources. .............................................................................................................................................. 8• Updated mechanical drawings to show additional dimensions. ............................................................................................ 8
3
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5 Specifications
5.1 Electrical Characteristics(TA = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITSTATIC CHARACTERISTICSBVDSS Drain to source voltage VGS = 0 V, ID = 250 μA 40 VIDSS Drain to source leakage current VGS = 0 V, VDS = 32 V 1 μAIGSS Gate to source leakage current VDS = 0 V, VGS = 20 V 100 nAVGS(th) Gate to source threshold voltage VDS = VGS, ID = 250 μA 1.5 1.8 2.2 V
RDS(on) Drain to source on resistanceVGS = 4.5 V, ID = 30 A 2.5 3.3 mΩVGS = 10 V, ID = 30 A 1.8 2.3 mΩ
gfs Transconductance VDS = 20 V, ID = 30 A 143 SDYNAMIC CHARACTERISTICSCiss Input capacitance
VGS = 0 V, VDS = 20 V, ƒ= 1 MHz3900 5070 pF
Coss Output capacitance 900 1170 pFCrss Reverse transfer capacitance 21 27 pFRG Series gate resistance 1.2 2.4 ΩQg Gate charge total (4.5 V)
VDS = 20 V, ID = 30 A
25 33 nCQg Gate charge total (10 V) 52 68 nCQgd Gate charge gate to drain 8.4 nCQgs Gate charge gate to source 10.3 nCQg(th) Gate charge at Vth 6.9 nCQoss Output charge VDS = 20 V, VGS = 0 V 59 nCtd(on) Turn on delay time
VDS = 20 V, VGS = 10 V,IDS = 30 A, RG = 0 Ω
5.3 nstr Rise time 6.8 nstd(off) Turn off delay time 23 nstf Fall time 4 nsDIODE CHARACTERISTICSVSD Diode forward voltage ISD = 30 A, VGS = 0 V 0.8 1 VQrr Reverse recovery charge VDS= 20 V, IF = 30 A,
di/dt = 300 A/μs88 nC
trr Reverse recovery time 44 ns
(1) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm ×3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
5.2 Thermal Information(TA = 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNITRθJC Junction-to-case (top of package) thermal resistance (1) 0.8 °C/WRθJA Junction-to-ambient thermal resistance (1) (2) 50 °C/W
GATE Source
DRAIN
N-Chan 5x6 QFN TTA MAX Rev3
M0137-01
GATE Source
DRAIN
N-Chan 5x6 QFN TTA MIN Rev3
M0137-02
4
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Max RθJA = 50°C/Wwhen mounted on1 inch2 (6.45 cm2) of 2oz. (0.071 mm thick)Cu.
Max RθJA = 125°C/Wwhen mounted on aminimum pad area of 2oz. (0.071 mm thick)Cu.
5.3 Typical MOSFET Characteristics(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
TC - Case Temperature (°C)
VG
S(t
h) -
Thr
esho
ld V
olta
ge (
V)
-75 -50 -25 0 25 50 75 100 125 150 1750.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
D006 VGS - Gate-to-Source Voltage (V)
RD
S(o
n) -
On-
Sta
te R
esis
tanc
e (m:
)
0 2 4 6 8 10 12 14 16 18 200
1
2
3
4
5
6
7
8
D007
TC = 25°C, I D = 30 ATC = 125°C, I D = 30 A
Qg - Gate Charge (nC)
VG
S -
Gat
e-to
-Sou
rce
Vol
tage
(V
)
0 5 10 15 20 25 30 35 40 45 50 550
2
4
6
8
10
D004 VDS - Drain-to-Source Voltage (V)
C -
Cap
acita
nce
(pF
)
0 5 10 15 20 25 30 35 4010
100
1000
10000
5000050000
D005
Ciss = Cgd + CgsCoss = Cds + CgdCrss = Cgd
VDS - Drain-to-Source Voltage (V)
I DS -
Dra
in-t
o-S
ourc
e C
urre
nt (
A)
0 0.2 0.4 0.6 0.8 10
20
40
60
80
100
120
140
160
180
D002
VGS = 4.5 VVGS = 6.5 VVGS = 10 V
VGS - Gate-to-Source Voltage (V)
I DS -
Dra
in-t
o-S
ourc
e C
urre
nt (
A)
1 1.5 2 2.5 3 3.5 4 4.5 50
20
40
60
80
100
120
140
160
180
200
D003
TC = 125°CTC = 25°CTC = -55°C
5
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Typical MOSFET Characteristics (continued)(TA = 25°C unless otherwise stated)
Figure 2. Saturation Characteristics
VDS = 5 V
Figure 3. Transfer Characteristics
ID = 30 A VDS = 20 V
Figure 4. Gate Charge Figure 5. Capacitance
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage
TC - Case Temperature (°C)
I DS -
Dra
in-t
o-S
ourc
e C
urre
nt (
A)
-50 -25 0 25 50 75 100 125 150 1750
20
40
60
80
100
120
D012
VDS - Drain-to-Source Voltage (V)
I DS -
Dra
in-t
o-S
ourc
e C
urre
nt (
A)
0.01 0.1 1 10 1000.01
0.1
1
10
100
1000
5000
D010
100 ms10 ms
1 ms100 µs
TAV - Time in Avalanche (ms)
I AV -
Pea
k A
vala
nche
Cur
rent
(A
)
0.01 0.1 110
100
200
D011
TC = 25q CTC = 125q C
TC - Case Temperature (°C)
Nor
mal
ized
On-
Sta
te R
esis
tanc
e
-75 -50 -25 0 25 50 75 100 125 150 1750.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
D008
VGS = 4.5 VVGS = 10 V
VSD - Source-to-Drain Voltage (V)
I SD -
Sou
rce-
to-D
rain
Cur
rent
(A
)
0 0.2 0.4 0.6 0.8 10.0001
0.001
0.01
0.1
1
10
100
D009
TC = 25°CTC = 125°C
6
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Typical MOSFET Characteristics (continued)(TA = 25°C unless otherwise stated)
ID = 30 A
Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
Single Pulse, Max RθJC = 0.8°C/W
Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching
Figure 12. Maximum Drain Current vs Temperature
7
CSD18502Q5Bwww.ti.com SLPS320B –NOVEMBER 2012–REVISED MAY 2017
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6 Device and Documentation Support
6.1 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.
6.2 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.
6.3 TrademarksNexFET, E2E are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
6.5 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
D1
Top View
E
c1
E1
41
23
Side View Bottom View
Front View
14
b (
8x)
32
e
L
K
H
D2
85
67
85
67
D3
d1
d2
8
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7 Mechanical, Packaging, and Orderable Information
7.1 Q5B Package Dimensions
DIMMILLIMETERS
MIN NOM MAXA 0.95 1.00 1.05b 0.36 0.41 0.46c 0.15 0.20 0.25
c1 0.15 0.20 0.25c2 0.20 0.25 0.30D1 4.90 5.00 5.10D2 4.12 4.22 4.32d 0.20 0.25 0.30E 4.90 5.00 5.10E1 5.90 6.00 6.10E2 3.48 3.58 3.68e 1.27 TYPL 0.46 0.56 0.66θ 0° — —K 1.40 TYP
4.318(0.170)
2.186
6.586
0.350
(0.014)
1.294
x 8
(0.051)
0.746 x 8
(0.029)
(0.259)
1.072
(0.042)
1.270
0.562 x 4
(0.022)
0.300(0.012)
(0.086)
(0.050)
1.525(0.060)
0.508
x4
(0.020)
1.270 (0.050)
0.286(0.011)
0.766
(0.030)
9
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7.2 Recommended PCB Pattern
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques(SLPA005).
7.3 Recommended Stencil Pattern
Ø 1.50+0.10–0.00
4.00 ±0.10 (See Note 1)
1.7
5 ±
0.1
0
R 0.30 TYP
Ø 1.50 MIN
A0
K0
0.30 ±0.05
R 0.30 MAX
A0 = 6.50 ±0.10B0 = 5.30 ±0.10K0 = 1.40 ±0.10
M0138-01
2.00 ±0.05
8.00 ±0.10
B0
12.0
0 ±
0.3
0
5.5
0 ±
0.0
5
10
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7.4 Q5B Tape and Reel Information
Notes:1. 10-sprocket hole-pitch cumulative tolerance ±0.22. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm3. Material: black static-dissipative polystyrene4. All dimensions are in mm (unless otherwise specified)5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket
PACKAGE OPTION ADDENDUM
www.ti.com 18-May-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
CSD18502Q5B ACTIVE VSON-CLIP DNK 8 2500 Pb-Free (RoHSExempt)
CU NIPDAU | CU SN Level-1-260C-UNLIM CSD18502
CSD18502Q5BT ACTIVE VSON-CLIP DNK 8 250 Pb-Free (RoHSExempt)
CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 150 CSD18502
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-May-2017
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
CSD18502Q5B VSON-CLIP
DNK 8 2500 330.0 12.4 6.3 5.3 1.2 8.0 12.0 Q1
CSD18502Q5B VSON-CLIP
DNK 8 2500 330.0 12.4 6.3 5.3 1.2 8.0 12.0 Q1
CSD18502Q5BT VSON-CLIP
DNK 8 250 178.0 12.4 6.3 5.3 1.2 8.0 12.0 Q1
CSD18502Q5BT VSON-CLIP
DNK 8 250 180.0 12.4 6.3 5.3 1.2 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Feb-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CSD18502Q5B VSON-CLIP DNK 8 2500 335.0 335.0 32.0
CSD18502Q5B VSON-CLIP DNK 8 2500 367.0 367.0 35.0
CSD18502Q5BT VSON-CLIP DNK 8 250 210.0 210.0 52.0
CSD18502Q5BT VSON-CLIP DNK 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Feb-2018
Pack Materials-Page 2
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Designers mustensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products inlife-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., lifesupport, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, allmedical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applicationsand that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatoryrequirements in connection with such selection.Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-compliance with the terms and provisions of this Notice.
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