Problems on digital circuits and systems

Francesc J. Robert

Josep Jordana

2016

Contents

Contents

Preface...............................................................................9Combinational circuits.......................................................13

1.1 List of concepts and topics....................................................131.1.1 The course organization and goals.............................131.1.2 Logic gates and equations..........................................141.1.3 Standard logic and arithmetic circuits.........................141.1.4 VHDL, technology, EDA tools and design flow.............14

1.2 Circuits using logic gates.......................................................161.2.1 Logic equations (PoS, SoP, maxterms, minterms).......161.2.2 Circuit analysis, truth tables and maxterms and minterms...............................................................................171.2.3 A variation: SoP and PoS.............................................191.2.4 Circuits using only NOR or only NAND.........................20

1.3 Standard logic circuits...........................................................211.3.1 Designing a priority-high 10-to-4 encoder (ENC10:4)..211.3.2 Designing a priority-high 8-to-3 encoder (ENC8:3)......23

1.4 Arithmetic circuits: Comparators, adders, subtractors, etc....241.4.1 Two’s complement (2C)..............................................24

1.5 Other combinational circuits..................................................251.5.1 Designing an 6-bit comparator using VHDL................25

Sequential systems...........................................................312.1 List of concepts and topics....................................................31

2.1.1 1-bit memory cells......................................................312.1.2 Finite state machines FSM..........................................312.1.3 Dedicated processors..................................................31

2.2 1-bit memory cells.................................................................322.2.1 Toggle flip flop (T-FF)..................................................322.2.2 Set-Reset flip flop (RS-FF)...........................................33

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Contents

2.2.3 Asynchronous counter (type 7493).............................342.2.4 Next problem..............................................................35

Microcontroller applications...............................................373.1 List of concepts and topics....................................................37

3.1.1 Polling inputs and driving outputs...............................373.1.2 Interrupt-driven inputs................................................37

3.2 Combinational circuit solved using a microcontroller.............383.2.1 4-bit adder..................................................................383.2.2 Dual MUX4..................................................................383.2.3 Gfdg............................................................................38

3.3 dgdfsgdfsg.............................................................................38References........................................................................39

4 394.1 Sadfasfdasf............................................................................39

Index................................................................................415 415.1 Dfasdfdsf...............................................................................41

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Preface

Preface

This publication is the initial draft of a collection of problems and exercises from the former ED and SED subjects and also from past editions of the CSD course to which this learning resource is aimed. This publication, now under construction, will assemble the reviewed versions of design exercises from the three chapters in which CSD is organised: combinational circuits, finite state machines (FSM) and dedicated processors, and microcontrollers.

The aim of this publication is to help students to develop the telecommunications engineering degree competencies associated to the CSD course listed below:

CE 14 TELECOM. Capacidad de análisis y diseño de circuitos combinacionales y secuenciales, síncronos y asíncronos, y de utilización de microprocesadores y circuitos integrados.

CE 15 TELECOM. Conocimiento y aplicación de los fundamentos de lenguajes de descripción de dispositivos de hardware.(CIN/352/2009, BOE 20.2.2009.)

PROJECT MANAGEMENT - Level 1: To know project management tools carrying out the different phases of the project established by the professor

EFFICIENT USE OF EQUIPMENT AND INSTRUMENTS - Level 1: Using instruments, equipment and software from the laboratories of general or basic use. Realising experiments and proposed practices and analysing obtained results.

SELF-DIRECTED LEARNING - Level 1. Completing set tasks within established deadlines. Working with recommended information sources according to the guidelines set by lecturers.

EFFICIENT ORAL AND WRITTEN COMMUNICATION - Level 1. Planning oral communication, answering questions properly

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Preface

and writing straightforward texts that are spelt correctly and are grammatically coherent.

TEAMWORK - Level 1. Working in a team and making positive contributions once the aims and group and individual responsibilities have been defined. Reaching joint decisions on the strategy to be followed.

THIRD LANGUAGE. Learning a third language, preferably English, to a degree of oral and written fluency that fits in with the future needs of the graduates of each course.

We will appreciate your commends so that we can enhance the process of fining errors and making improvements.

10

Preface

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Problems on Digital Circuits and Systems

12

1

Problems on Digital Circuits and Systems

Combinational circuits1.1 List of concepts and topics

After studying the content of this chapter on combinational circuit, you will be able to:

1.1.1 The course organization and goals

Be aware of the learning objectives of the course and what is expected from the students and the instructors.

Use your official UPC e-mail address to communicate with your instructors. For these reasons.

Use and manage an e-mail client like Thunderbird or Outlook. Organise and share a cloud file system like Dropbox,

Onedrive, GoogleDrive, etc. to develop projects and assignments.

Use an SFTP client like WinSCP to remotely access your network disk drive “L”. Or instead, run the application “Repositori the fitxers” from the CBL AT.

Explain the five elements to achieve effective cooperative learning: 1) positive interdependence; 2) face-to-face interaction; 3) individual accountability and personal responsibility; 4) use of interpersonal and small-group skills; and 5) group processing or reflection.

Analyse your own individual and group study time. Be aware that 6 ECTS are 150 hours of study time.

Produce a quality written solution (in sheets of paper) using the template. Basically, (1) Specifications, (2) Plan, (3) Development, (4) Test, (5) Report, and sometimes (6) prototyping.

Assess the own or the group learning progression and the quality of the deliverables using the given rubric.

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Problems on Digital Circuits and Systems

Use Google sites to build your cooperative group ePortfolio (with this template) with the aim of publishing your projects, results and reflection.

1.1.2 Logic gates and equations

Use and explain the functionality of logic gates AND, NAND, OR, NOR, XOR, NXOR, NOT.

Find the datasheets of the Small and Medium Scale of Integration (SSI and MSI) integrated circuits.

Analyse a logic circuit built using logic gates (deduce its truth table).

Explain and relate the following concepts for designing a logic circuit: truth table, canonical algebraic equations: minterms and maxterms, Boolean algebra and logic functions, minimisation: SoP (sum of products) and PoS (product of sums).

Simplify or minimize logic function using software like Minilog.exe.

Use the application WolframAlpha to verify logic equations and determine the truth table of a combinational circuit.

Use the HADES JAVA-based platform or Deeds to visualise and analyse the operation of digital circuits.

Capture and simulate a schematic using the virtual laboratory software Proteus-ISIS or Multisim.

1.1.3 Standard logic and arithmetic circuits

Design and use standard combinational logic and arithmetic blocks: multiplexers (or data selectors), demultiplexers (or data distributors), decoders, encoders, hexadecimal to seven-segment LED displays adapters, code converters, adders, comparators, etc.

Design basic arithmetic circuits in two’s complement format (2C).

Explain the concepts of flat and hierarchical designs and implement simple projects involving several components.

1.1.4 VHDL, technology, EDA tools and design flow

Search books and the Internet to find information on the basics of VHDL language and explain the differences between the VHDL design styles: structural and behavioural.

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Combinational circuits

Use the register transfer level (RTL) and the technology schematic views to inspect the results of the synthesis process.

Explain the basic technological details of a sPLD (22V10), CPLD or FPGA and how to program them to implement logic functions.

Install EDA tools (Lattice Semiconductor ispLEVER Classic or Diamond, Altera Quartus II or Prime, and Xilinx ISE or Vivaldo), and run its design flow to implement VHDL projects for sPLD/CPLD/FPGA chips. Essentially: (1) VHDL source files, (2) synthesis, (3) functional simulation, (4) pin assignment, (5) gate-level simulation, (5) target device programming, and (6) prototype verification.

Simulate a logic circuit using EDA tools: ActiveHDL Lattice edition, ModelSim Altera edition or Xilinx ISim.

Use a sPLD/CPLD/FPGA training or development board to prototype and verify the course projects.

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Problems on Digital Circuits and Systems

1.2 Circuits using logic gates

1.2.1 Logic equations (PoS, SoP, maxterms, minterms)

The Fig. 1 shows the block diagram and the truth table of the encoder device to be designed. It provides priority encoding in binary code of the inputs to ensure that only the highest order data line is encoded when several inputs are active when high at the same time. The symbol “-” means a “don’t care” value which is represented other times by “x”.

- Represent the output Y2 = f(X7..X0) using a PoS.

- Represent the output Y1 using a SoP.

- Represent the output GS using maxterms. How many minterms will the function have?

- Write down the VHDL code using either structural or behavioural style. Explain the differences between the two different coding styles.

Fig. 1The symbol and truth table of a combinational circuit.

16

Combinational circuits

1.2.2 Circuit analysis, truth tables and maxterms and minterms

The aim of this exercise is firstly, to analyse the circuits A and B in Fig. 2 to obtain their truth tables, and secondly, to draw another equivalent circuit using the canonical logic equations (maxterms and minterms).

Fig. 2Circuit A and

Circuit B composed of a

network of logic gates.

Let us layout a plan to solve this problem:

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Problems on Digital Circuits and Systems

1. Deduce the logic equations that exactly match the circuits.2. Apply Boolean algebra to determine the truth table (which is

equivalent to the sum of minterms and the product of maxterms). The numerical engine WolframAlpha can be used to verify the truth table typing directly the general equation and analysing the computer results.

3. Draw the circuits of the outputs P and Q and capture the schematics in Proteus and run simulations to verify the whole truth table.

4. Or, instead, run a VHDL design flow using EDA tools (a single-file structural project, circuit synthesis and test bench simulation) to generate a circuit and verify it by means of a timing diagram from which to annotate a truth table that has to be identical to the one deduced in 2).

The Fig. 3 represents several ways to plan the exercise of determining the truth table of a given simple combinational circuit composed of logic gates.

Fig. 3Multiple planning paths to analyse a circuit of logic gates.

Some ideas on the solution of this problem can be found here.

18

Combinational circuits

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Problems on Digital Circuits and Systems

1.2.3 A variation: SoP and PoS

Design the Problem 1.2.2 using sum of products (SoP) and product of sums (PoS) which are the minimised equations obtained from the truth table using an application like Minilog.exe.

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Combinational circuits

1.2.4 Circuits using only NOR or only NAND

Given the following Boolean expression:

Q=f ( x , y , z )=x·y+ y ' · z

a) Draw the circuit’s truth table and symbol. Represent the circuit using only NAND logic gates.

b) Express the output as a sum of minterms and a product of maxterms.

c) Using the equation obtained in b), represent the circuit using only-NOR logic gates.

d) If the propagation delays tPHL and tPLH of a gate of this kind, for instance, 74HCT technology is 21 ns, calculate the maximum frequency of operation of this circuit.

e) How would you use the VHDL simulator to verify the truth table of this digital circuit?

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Problems on Digital Circuits and Systems

1.3 Standard logic circuits

1.3.1 Designing a priority-high 10-to-4 encoder (ENC10:4)

The idea of the problem is to develop the VHDL code for the 10 to 4 encoder (ENC10:4) component represented in Fig. 4 which can be interfaced to a standard 10-key numeric keypad. We can plan the project in several ways:

- Behavioural (flat design with a single VHDL file), using the high level description of the specifications.

- Structural (flat design with a single VHDL file), using the truth table logic equations.

- Structural (hierarchical design with multiple VHDL files), building the project using an architecture consisting of smaller components of the same kind like ENC4:2.

a)0123456789

R910k VCC

GAL22V10

ENCODER_10_4

K0_LK1_LK2_LK3_LK4_LK5_LK6_LK7_LK8_LK9_L

GS

X3X2X1X0

(priority high)

0000

0

b)

Fig. 4a) A typical 10-key keypad, b) Interface circuit which gives the binary code of the pressed key.

a) Fill in the truth table using the names and the variable order depicted in the following table. GS has to be high (‘1’) when any key is pressed and low (‘0’) otherwise. How many combination will it have in case of not using “don’t care” (“-“) terms?

22

Combinational circuits

K0_L

K1_L

K2_L

K3_L

K4_L

K5_L

K6_L

K7_L

K8_L

K9_L

X3

X2

X1

X0

GS

Comments

b) How many minterms will X3 have? How many maxterms will X2 have?

c) By inspection of the truth table or using Minilog, represent the five output functions either as sum of products (SoP) or product of sums (PoS).

d) Write down the structural VHDL code which is derived from the equations deduced in c).

e) Search Internet or find in books on the subject the high-level or behavioural VHDL code for the component in Fig. 4b.

f) Figure out how can be designed an ENC10:4 using components like ENC4:2 and other circuits if necessary.

g) Create a design project for a sPLD, CPL or FPGA target chip, using EDA tools (ispLEVER Classic, Quartus, ISE).

h) Translate timing diagram sketch into a VHDL test bench file to simulate the circuit using ActiveHDL, ModelSim or ISIm.

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Problems on Digital Circuits and Systems

1.3.2 Designing a priority-high 8-to-3 encoder (ENC8:3)

In Fig. 5 there is the internal circuit of the classic chip HEF4532B and its truth table as specified by Philips.

Fig. 5 The HEF4532B manufactured by Philips. When Ein is low the chip is disabled. Group select (GS) is assessed when there is any input active. Enable output Eout is active only when the chip is enabled and there is not a single input active. The outputs O(2..0) generates the binary code of the input being active knowing that the highest input prevails when more than one input is active at the same time.

1) Redraw the truth table using ‘0’ and ‘1’ and explain which is the circuit’s function using a pair of examples. How many binary combinations does this table have?

2) Write Eout = f( Ein, I7, ..., I0) using minterms. And draw the equivalent circuit using gates.

3) Write GS as a product of sums (PoS). How many minterms does this function have? Draw the circuit using gates.

4) Write O2 as a sum of products (SoP). How many maxterms does this function have? Write O1 and O0 as a product of sums (PoS).

5) Describe the circuit in VHDL in a behaviour or structural fashion. 6) Draw a sketch of a timing diagram and translate it into a test

bench to be able to verify the circuit using an EDA tool. Optional questions related to further understanding the problem and designing the project encoder_3_to_8.vhd into a programmable device. 7) Write the .tbl format file so that it can be used to obtain the PoS

or the SoP in Minilog software. Find and write down the link to a similar circuit in HADES which can be executed using the JAVA applet. Simulate the circuit in Proteus and check if it works as expected.

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Combinational circuits

8) Start a VHDL-based synthesis project and a testbench-based simulation using EDA tools for target CPLD or FPGA programmable chips.

1.4 Arithmetic circuits: Comparators, adders, subtractors, etc.

1.4.1 Two’s complement (2C)

Basic operations in two’s complement (2C) and 6 bits. Indicate the value of the overflow flag after performing the operations

Addition: (+6) + (-22) Subtraction: (-13) - (-27) Addition: (-9) + (+26)

Draw an entity named Adder_Subtractor_6bit and propose its internal architecture using components and logic. Explain with example vectors how your architecture works.

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Problems on Digital Circuits and Systems

1.5 Other combinational circuits.

1.5.1 Designing an 6-bit comparator using VHDL

The idea is to develop and produce a cascadable COMP6 component for our library of VHDL modules. Fig. 6 shows the entity’s symbol and the proposed internal architecture for and structural planning.

Fig. 6a) Entity for the 6-

bit expandable comparator. b) Example of an

internal architecture based on a structure of

smaller elements of the same kind.

a)

B[2..0]

A[2..0]

B[5..3]

A[5..3]

W1

W2

W3

GT

EQ

LT

GiEiLi

CI1

COMP3

X[2..0]GT

Y[2..0] EQ

LT

GiEiLi

CI2

COMP3

X[2..0]GT

Y[2..0] EQ

LT

GiEiLi

b)

Fig. 7Function table for the cascadable 3-

bit comparator COMP3 which is used as a basic

component.

X[2..0] Y[2..0] Gi Ei Li GT EQ LT

X > Y x x x 1 0 0 X is greater than Y

X < Y x x x 0 0 1 X is lesser than Y

1 0 0 1 0 0 GI input decides

X = Y 0 1 0 0 1 0 EI input decides

0 0 1 0 0 1 LI input decides

Part A: Implementation of a behavioural design in a sPLD

a) Explain the design flow you will follow to produce your circuit using Lattice ispLEVER Classic / Altera Quartus II / Xilinx ISE.

b) Write down the high level or behavioural VHDL code directly as a single block as in Fig. 6a planning writing first an algorithm or a flowchart.

c) Create a single-file VHDL project in Lattice ispLEVER Classic / Altera Quartus II / Xilinx ISE for a simple programmable logic device (sPLD) GAL22V10 (24 pins) or a CPLD or a FPGA chip.

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Combinational circuits

Print and comment the RTL and the technology views of the synthesised circuits.

d) Test and simulate your design using Proteus and its EasyHDL scripting language (in case of a sPLD), or the ActiveHDL / ModelSim / ISim simulators by means of a VHDL test bench. First of all draw a timing diagram sketch to be able to compare it with your results from the simulator.

Part B: Implementation of a structural design in a CPLD or a FPGA

e) Explain the design flow you will follow to produce your circuit using Lattice ispLEVER Classic / Altera Quartus II / Xilinx ISE.

f) Write down a structured design as in Fig. 6b using several components. For instance, Fig. 7 shows the truth table for a 3-bit cascadable comparator.

g) Implement the elemental COMP1 using the logic equations derived from Minilog.exe (single output mode, sum of products, table output format). Verify your equations using WolframAlpha.

h) Create a multiple-file VHDL-based project in ispLEVER Classic / Quartus II / ISE for a CPLD target chip Lattice ispMACH4128V TQFP100, or the Altera MAX EPM7128SLC84-7, or the Xilinx CoolRunner II XC2C256-TQ144 - 7. Print the RTL and technology views of the synthesised circuit, so that it can be compared to the initial block diagram proposed in Fig. 6b.

i) Test and simulate your design using Proteus and its EasyHDL scripting language (in case of a sPLD), or the ActiveHDL / ModelSim / ISim simulators by means of a VHDL test bench. First of all draw a timing diagram sketch to be able to compare it with your results from the simulator

j) Assign pins and generate the output configurations files if the circuit has to be prototyped in a board (Lattice HWD-LC4128V, Altera UP2 or Xilinx CoolRunner-II CPLD Starter Board).

k) Write down a report to document your design using the stabilised quality standards and templates. Upload it to your web portfolio along with all the project files and pictures nd drawings before the due date.

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Problems on Digital Circuits and Systems

We will appreciate your commends so that we can enhance the process of fining errors and making improvements.

28

Combinational circuits

29

Problems on Digital Circuits and Systems

30

2

Problems on Digital Circuits and Systems

Sequential systems2

2.1 List of concepts and topics

After studying the content of this chapter on combinational circuit, you will be able to:

2.1.1 1-bit memory cells

Use and explain the functionality of logic gates AND, NAND, OR, NOR, XOR, NXOR, NOT.

2.1.2 Finite state machines FSM

Explain the concepts of flat and hierarchical designs and implement simple projects involving several components.

2.1.3 Dedicated processors

and verify the course projects.

31

Problems on Digital Circuits and Systems

2.2 1-bit memory cells

2.2.1 Toggle flip flop (T-FF)

and verify the course projects.

32

Sequential sytems

2.2.2 Set-Reset flip flop (RS-FF)

and verify the course projects.

33

Problems on Digital Circuits and Systems

2.2.3 Asynchronous counter (type 7493)

Analyse the circuit Fig. 9 and represent the waveforms in a diagram like the one represented in the Fig. 10. Be aware that the circuit is asynchronous because chips’ CLK inputs are not connected at the same signal. A VHDL design tutorial of a similar circuit can be found here. Remember that a T-type flip-flop behaves like indicated in Fig.8.

Fig. 8Symbol and

function table of a synchronous

toggle T-type flip-flop.

Fig. 9This is the clocked

circuit to be analysed. Here,

there is a Proteus version of this

circuit that can be simulated.

Fig. 10Output

waveforms to be

deduced from the

circuit in Fig.9.

34

Sequential sytems

Which is the circuit function? What will be the circuit applied for? Which is the circuit’s main problem, so that it has to be discarded for precision applications?

35

Problems on Digital Circuits and Systems

2.2.4 Next problem

Analyse the t

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Problems on Digital Circuits and Systems

38

3

Problems on Digital Circuits and Systems

Microcontroller applications

3

3.1 List of concepts and topics

After studying the content of this chapter on combinational circuit, you will be able to:

3.1.1 Polling inputs and driving outputs

Explain the concepts of flat and hierarchical designs and implement simple projects involving several components.

3.1.2 Interrupt-driven inputs

Course projects.

39

Problems on Digital Circuits and Systems

3.2 Combinational circuit solved using a microcontroller

3.2.1 4-bit adder3.2.2 Dual MUX4 3.2.3 Gfdg

3.3 dgdfsgdfsg

40

References

References

4

4.1 Sadfasfdasf

41

References

42

Index

Index5

5.1 Dfasdfdsf

43

Index

6

44