CS/COE0447Computer Organization & Assembly LanguageChapter 5 Part 3In-Class Exercises

For ReferenceThe following slides contain a subset of Chapter 5 Part 3 the essentials, without the animations, discussion, and so on.You will get a copy of Figure 5.28 on Exam3 and the FinalRather than trying to memorize the other slides, try to reconstruct them while looking at Figure 5.28 and thinking about how the instructions are executed

Multi-Cycle Execution: R-typeInstruction fetchIR

Multi-cycle Execution: lwInstruction fetchIR

Multi-cycle Execution: swInstruction fetchIR

Multi-cycle execution: beqInstruction fetchIR

Multi-cycle execution: jInstruction fetchIR

Fig 5.28 Our final multicycle datapath

A Finite State Machine to generate the control signals wrong; RegDst = 0; MemtoReg = 1

QuestionIn terms of the datapath in Figure 5.28, how is the branch target address calculated, and where is it stored?In other words, fill in the following:

______

AnswerIn terms of the datapath in Figure 5.28, how is the branch target address calculated, and where is it stored?ALUOut

QuestionFor which instruction(s) is the branch target address calculated? During which cycle(s)?Ans: It is calculated during cycle 2 for all instructions. If the current instruction turns out to not be a branch, then the value was calculated for nothing. But, doing this means that branch instructions take 3 rather than 4 cycles. Go back and look at the instruction execution steps for beq (slide 6). The ALU is not being used for anything else that cycle, so we can use it for this. The things added are the PC and information from the IR, both of which are available during this cycle.Note: the hardware is decoding the instruction during this cycle, but the various fields ARE available, in the IR. The hardware HAS the current instruction; it just doesnt understand it yet.

QuestionWhat happens during the 3rd cycle for a memory access instruction?Well, which are the memory access instructions? lw, sw in the subset covered in this chapter. [Others are lbu, lhu, lui]_____

AnswerWhat happens during the 3rd cycle for a memory access instruction?ALUOut

QuestionWhat happens during the first cycle for all instructions?

Ans: IR

QuestionIs the ALU needed to execute a j instruction?No: its execution is PC

QuestionWhy does the j instruction require 3 cycles, since it doesnt require rs, rt, or rd and does not require the ALU?Cycle 1: instruction fetchCycle 2: decode instructionCycle 3: It is only by here that the instruction has been decoded, and the hardware knows it is a j (see slide 7)

QuestionFor a LW, what is ALUSrcB on each cycle? (Figure 5.28 is on slide 8)Cycle 1: PC = PC+4, so ans = 01Cycle 2: Compute branch target address, so ans = 3 0b11Cycle 3: Compute effective address, so ans = 2 0b10Cycle 4: No use of ALU, so XCycle 5: No use of ALU, so X

QuestionFor a BEQ, what is ALUSrcB on each cycle? (Figure 5.28 is on slide 8)Cycle 1: PC = PC+4, so ans = 01Cycle 2: Compute branch target address, so ans = 3 0b11Cycle 3: Perform A B, so ans = 00

QuestionFor which instructions, during which cycles, is ALUSrcA = 0?Well, it is 0 whenever something is added to the PCAll instructions, Cycle 1 PC = PC + 4All instructions, Cycle 2ALUOut

QuestionFor which instructions, during which cycles, is ALUSrcA = 01? (not X)Whenever the ALU is used to compute something and the top input is A (rs)R-type, cycle 3 ALUOut

QuestionIs there any instruction, cycle where one of ALUSrcA and ALUSrcB is X and the other one isnt?Nope. If the ALU is needed for something, it needs 2 operands. These two control signals choose the operands.

QuestionIn the FSM for generating the control signals, not all of the signals are shown in each state. Look at the machine, and figure out when a signal is not shown.Hint: there are two casesCase 1: a signal that is X (MUXs and ALU Op)Case 2: a signal that is essentially an on/off switch whose value is 0 (and cannot be X)PCWriteCond,PCWrite,MemWrite,IRWrite, RegWrite (cant be X: incorrect writes!)MemRead (cant be X: we dont want unneeded memory reads)

QuestionIn the FSM, which instruction, cycle is state 8?Beq, cycle 3How about state 1?All instructions, cycle 2How about state 7?R-type, cycle 4

QuestionIn the FSM, when is the transition made from state 4 to state 0?After a lw instruction finishes: we start over again in state 0 for the next instruction. Note that this is an unconditional transition: After state 4 finishes, we always transition to state 0.

QuestionIn the FSM, where do we transition from state 1?It depends on the opcode:2 if opcode == 0x23 or 0x2b6 if opcode = 0b0000008 if opcode = 0x49 if opcode = 0x2

Remember this from the single-cycle datapath?

And this (from single-cycle datapath)?Control UnitALU Control UnitThis needs to change.The signals depend onopcode plus which cycleit is. And, it is underthe control of the clock.We wont look at furtherdetails of the FSMimplementation.

from the single-cycle datapathWhat we do want to do is figure out what values ALUOp1 and ALUOp0have for each instruction, and for each cycleNote: they are X if the ALU is not used during a cycle.

from the single-cycle datapathThe ALU is used during cycles 1 and 2 for all instructionsPC = PC+4 (c1); Calculate the branch target address (c2)It is used to calculate the effective address for lw,sw on cycle 3It is used to perform the op for R-type instructions on cycle 3It is used to perform the comparison for beq instructions on cycle 3

Remember this from the single-cycle datapath?It is used to perform the op for R-type instructions on cycle 3. So, what shouldALUOp1 and ALUOp2 be for R instructions on cycle 3?They should be 10, so that the funct field determines what the ALU does.

from the single-cycle datapathALU is used to calculate the effective address for lw,sw on cycle 3. So,on cycle 3, ALUOp1 and ALUOp0 should be 00

from the single-cycle datapathWhat should ALUOp1 and ALUOp0 be for a beq instruction (in the multicycle datapath?)Bad question! You should ask me, during which cycle? Ill turn things around: during which cycle should they have the 01 value listed in the table above for BEQ?During cycle 3! that is when the subtraction is performed to do the comparison

from the single-cycle datapathThe ALU is used during cycles 1 and 2 for all instructionsPC = PC+4 (c1); Calculate the branch target address (c2)Which value should ALUOp have during cycles 1 and 2?In both cases: 00. Then, the ALU will perform addition.

from the single-cycle datapathThe ALU is used during cycles 1 and 2 for all instructionsIn both cases: 00. Then, the ALU will perform addition.Is the R-type ADD an option? No! The funct field is the bottom 6 bitsof the IR, whatever they happen to be!