Cs6211 - Digital Lab Manual

7/23/2019 Cs6211 - Digital Lab Manual

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Pin Details of Digital Logic Gates:


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7476

7474


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Postulates and Theorems of Boolean algebra:

S.No Postulate/Theorem Duality Remarks

1. X + 0 = X X.1 = X -

2. X + X = 1 X.X = 0 -

3.

X + X = X X.X = X -

4. X + 1 = 1 X.0 = 0 -

5. (X) = X - Involution

6. X + Y = Y + X X.Y = Y.X Commutative

7. X + (Y + Z) = (X + Y) + Z X.(Y.Z) = (X.Y).Z Associative

8. X.(Y + Z) = X.Y + X.Z X + (Y.Z) = (X + Y)(X + Z) Distributive

9. (X + Y) = XY (XY) = X + Y DeMorgans

Theorem

10.

X + XY = X X.(X + Y) = X Absorption

Bit Grouping:

Bit - A single, bivalent unit of binary.

Equivalent to a decimal "digit."

Crumb, Tydbit, or Tayste - Two bits.

Nibble or Nybble - Four bits.

Nickle - Five bits.

Byte - Eight bits.

Deckle - Ten bits.

Playte - Sixteen bits.

Dynner - Thirty-two bits.

Word - (system dependent).

Arithmetic Notations:

Augend + Addend = Sum

Minuend Subtrahend = Difference

Multiplicand X Multiplier = Product

Dividend / Divisor = Quotient


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FLIP FLOPS

JK FLIP FLOP

SR FLIP FLOP

D FLIP FLOP

T FLIP FLOP


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Verification of Logic Gates:


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EXPT NO. :1 VERIFICATION OF BOOLEAN THEOREMS USING

DATE : DIGITAL LOGIC GATES

Aim:

To verify the truth table of basic Boolean algebric laws by using logic gates.

Components Required:

S.NO COMPONENTS RANGE QUANTITY

1Digital IC trainer

kit- 1

2 IC

7400 1

7402 1

7404 1

7408 1

7432 1

7486 13 Bread board - 1

4 Connecting wires - As required

Theory:

Demorgans Theorems

First Theorem:

It states that the complement of a product is equal to the sum of the complements.

(AB)=A+B

Second Theorem:

It states that the complement of a sum is equal to the product of the complements.

(A+B)=A.B

Boolean Laws:

Boolean algebra is a mathematical system consisting of a set of two or more distinc

elements, two binary operators denoted by the symbols (+) and (.) and one unary operato

denoted by the symbol either bar (-) or prime (). They satisfy the commutative, associative

distributive and absorption properties of the Boolean algebra.

Commutative Property:

Boolean addition is commutative, given by

A+B=B+A

Boolean algebra is also commutative over multiplication, given by

A.B=B.A


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De-Morgans Theorem:

Truth Table:

Input Output

A B (A+B) A. B

0 0 1 1

0 1 0 0

1 0 0 0

1 1 0 0

Commutative Law:

Truth Table:

Input Output

A B A+B B+A

0 0 0 0

0 1 1 1

1 0 1 1

1 1 1 1


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Associative Property:

The associative property of addition is given by

A+ (B+C) = (A+B) +C

The associative law of multiplication is given by

A. (B.C) = (A.B).C

Distributive Property:

The Boolean addition is distributive over Boolean multiplication, given by

A+BC = (A+B) (A+C)

Boolean multiplication is also distributive over Boolean addition given by

A. (B+C) = A.B+A.C

Realization of circuits for Boolean expression after simplification:

A binary variable can take the value of 0 or 1. A Boolean function is an expressio

formed with binary operator OR, AND and a unary operator NOT, parenthesis function can be

or 1.

For example, consider the function

The prime implicants are found by using the elimination of complementary function. The circui

diagram for the function is drawn using AND.OR and NOT gates. The output for thcorresponding input of A1, A0, B1, BOis calculated and the truth table is drawn.

Procedure:

1. Test the individual ICs with its specified verification table for proper working.

2. Connections are made as per the circuit/logic diagram.

3. Make sure that the ICs are enabled by giving the suitable Vccand ground connections.

4. Apply the logic inputs to the appropriate terminals of the ICs.

5. Observe the logic output for the inputs applied.

6. Verify the observed logic output with the verification/truth table given.


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Associative Law:

Truth Table:

Input Output

A B C A+B (A+B)+C B+C A+(B+C)

0 0 0 0 0 0 0

0 0 1 0 1 1 1

0 1 0 1 1 1 1

0 1 1 1 1 1 1

1 0 0 1 1 0 1

1 0 1 1 1 1 1

1 1 0 1 1 1 1

1 1 1 1 1 1 1

Distributive Law:


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Truth Table:

Input Output

A B C B+C A.(B+C) A.B A.C A.B+A.C

0 0 0 0 0 0 0 0

0 0 1 1 0 0 0 0

0 1 0 1 0 0 0 0

0 1 1 1 0 0 0 0

1 0 0 0 0 0 0 0

1 0 1 1 1 0 1 1

1 1 0 1 1 1 0 1

1 1 1 1 1 1 1 1


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VIVA QUESTION:

1.Define logic gates?Give examples with symbols.

2.What are universal gates? Why it is called so?

3.What are special type of gates with examples?

4.Explain positive and negative logic.

5.Explain duality theorem.

6.State De-Morgans theorem.

7.What are the basic rules used in Boolean expressions?

8.What are the differences between Boolean and Ordinary Algebra?

9.What are the Boolean postulates?

10.State inversion law.

APPLICATIONS:

EXOR gate can be used for communication transmission and reception.

AND gate is used in Electronic door.

NOT gate is used in House alarm and Traffic lights.

EXNOR gate is used in Warning lights.

All basic gates can be used for signal processing and communication.

RESULT:

Thus the truth table of basic Boolean algebraic laws by using basic logic gates are verified


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Truth Table for Arbitrary Function:

Input Output

A1 A0 B1 B0 F

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 1

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 0

1 0 1 1 0

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 0

Realization of simplified Boolean expression using K-Map:


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EXPT NO. :2 DESIGN AND IMPLEMENTATION OF COMBINATIONAL

DATE : CIRCUITS USING BASIC GATES FOR ARBITRARY

FUNCTIONS,CODE CONVERTERS,ETC

Aim:

To design and implement a combinational circuit using basic gates for arbitrary function

and code converters.



1Digital IC Trainer

kit- 1

2 IC

7404 1

7408 2

7432 1

7486 1

3 Connecting wires - As required4 Bread board - 1

Theory:

Adder:

Digital computers perform various arithmetic operations. The most basic operation is the

addition of two binary digits. The simple addition consists of four possible elementary operations

namely

A B Sum Carry

0 0 0 00 1 1 0

1 0 1 0

1 1 0 1

The logic circuit which performs the addition of two binary digits which results a sum and carr

output is called a half adder. In the above operations the first three operations result with zero

carry but fourth operation has carry 1. The circuit which performs addition of three bits is called

a full adder. A full adder is a combinational circuit that forms the arithmetic sum of three inpu

bits. It consists of three inputs and two outputs. Two of the input variables are denoted by A and

B represents the two significant bits to be added. The third input represents the carry from th

previous lower significant position.

Subtractor:

The subtraction consists of four possible elementary operations, namely

A B Difference Borrow

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1


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Logic Diagram for Arbitary Function:


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In all operations each subtrahend bit is subtracted from the minuend bit. In case of secon

operation the minuend bit is smaller than the subtrahend bit hence 1 is borrowed.

Binary to GrayVice versa:

The binary coded decimal (BCD) code is one of the early computer codes. Each decima

digit is independently converted to a 4 bit binary number. A binary code will have som

unassigned bit combinations if the number of elements in the set is not a multiple power of 2The 10 decimal digits form such a set. A binary code that distinguishes among 10 elements mus

contain at least four bits, but 6 out of the 16 possible combinations remain unassigned. Differen

binary codes can be obtained by arranging four bits in 10 distinct combinations. The code mos

commonly used for the decimal digits is the straight binary assignment. This is called binar

coded decimal.

The gray code is used in applications where the normal sequence of binary numbers may

produce an error or ambiguity during the transition from one number to the next. If binarynumbers are used, a change from 0111 to 1100 may produce an intermediate erroneous numbe

1001 if the rightmost bit takes longer to change in value than the other three bits. The gray cod

eliminates this problem since only one bit changes in value during any transition between tw

numbers.

BCD to Excess 3Vice versa:

Excess 3 code is a modified form of a BCD number. The excess 3 code can be derived from

the natural BCD code by adding 3 to each coded number. For example, decimal 6 can b

represented in BCD as 0110. Now adding 3 to the given number yield equivalent excess 3 cod

i.e., 6 + 3 = 9 0110 + 0011 = 1001. Thus for the entire sequence of BCD value (i.e., 0 to 9

excess 3 equivalent table should be made so that the realization of Boolean expression for th

circuit implementation is feasible. In the reverse process of designing a code converter from

excess 3 to BCD the same procedure is followed. Here are the general steps to be followed whil

going for a code converter design,

start with the specification of the circuit to be designed.

Identify the inputs and outputs

Derive truth table

Obtain simplified Boolean equations

Draw the logic diagram

Check the design to verify correctness with the truth/verification table.


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Truth Table (Binary to Gray):

Binary (Input) Gray (Output)

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

Realisation of Boolean Expression for Binary to Gray Code Converter:


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Procedure:








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Logic Diagram for Binary to Gray Code Converter:

Truth Table (Gray to Binary):

Gray (Input) Binary (Output)

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

1 0 0 0 1 1 1 1

1 0 0 1 1 1 1 0

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 0 1 0


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Realisation of Boolean Expression for Gray to Binary Code Converter:

Logic Diagram for Gray to Binary Code Converter:


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Truth Table(BCD to Excess 3):

Decimal

Value

BCD Input Excess 3 output

A B C D W X Y z

0 0 0 0 0 0 0 1 1

1 0 0 0 1 0 1 0 0

2 0 0 1 0 0 1 0 1

3 0 0 1 1 0 1 1 0

4 0 1 0 0 0 1 1 1

5 0 1 0 1 1 0 0 0

6 0 1 1 0 1 0 0 1

7 0 1 1 1 1 0 1 0

8 1 0 0 0 1 0 1 1

9 1 0 0 1 1 1 0 0

Realization of Boolean Expression for BCD to Excess 3 Converter:


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Circuit Diagram for BCD to Excess 3 Converter:

Truth Table(Excess 3 to BCD):

Decimal

Value

Excess 3 Input BCD Output

W X Y z A B C D

0 0 0 1 1 0 0 0 0

1 0 1 0 0 0 0 0 1

2 0 1 0 1 0 0 1 0

3 0 1 1 0 0 0 1 1

4 0 1 1 1 0 1 0 0

5 1 0 0 0 0 1 0 1

6 1 0 0 1 0 1 1 0

7 1 0 1 0 0 1 1 1

8 1 0 1 1 1 0 0 0

9 1 1 0 0 1 0 0 1


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Realization of Boolean Expression for Excess 3 to BCD Converter:

Circuit Diagram Excess 3 to BCD Converter:


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VIVA QUESTIONS:

1.Define Combinational Circuit.Give examples.

2.Define fan in and fan out.

3.Explain K-map.

4.Define code converter.

5.What are the code converters used?6.What is packed BCD?

7.What is the special feature of gray code?

8.List out the applications of gray code.

9.Obtain XS-3 code for (458)10.

10.Encode the decimal number 46 to gray code.

APPLICATONS:

Gay code is used as encoders for position sensor.

An example of code converter is a simple hand-held calculator,which is composed of a

input device called a keyboard.

Result:

Thus the combinational circuit for an arbitrary function, code converter using logic gates

was designed, implemented and tested its performance with truth table.


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Truth Table (Half Adder):

A B S (Sum)

C

(Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Realization of Boolean Expression:

Circuit Diagram:


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EXPT NO. :3 DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDER /

DATE : SUBTRACTOR USING BASIC GATES AND MSI DEVICES

AIM:

To design and implement 4-bit binary adder and subtractor using basic gates and MS

devices.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1

2. EX-OR GATE IC 7486 1

3. NOT GATE IC 7404 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 40

THEORY:

Adder:

Digital computers perform various arithmetic operations. The most basic operation is the

addition of two binary digits. The simple addition consists of four possible elementary operations

namely

A B Sum Carry

0 0 0 0

0 1 1 01 0 1 0

1 1 0 1

The logic circuit which performs the addition of two binary digits which results a sum and carr

output is called a half adder. In the above operations the first three operations result with zero

carry but fourth operation has carry 1. The circuit which performs addition of three bits is called

a full adder. A full adder is a combinational circuit that forms the arithmetic sum of three inpu

bits. It consists of three inputs and two outputs. Two of the input variables are denoted by A and

B represents the two significant bits to be added. The third input represents the carry from thprevious lower significant position.

Subtractor:

The subtraction consists of four possible elementary operations, namely


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Truth Table (Full Adder):

A B Cin S (Sum)C

(Carry)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1


Circuit Diagram:


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A B Difference Borrow

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

In all operations each subtrahend bit is subtracted from the minuend bit. In case of second

operation the minuend bit is smaller than the subtrahend bit hence 1 is borrowed.

A half subtractor is a combinational circuit that subtracts two bits and produces thei

difference. It also has an output to specify if 1 is borrowed. Let A and B are the input variable

for the half subtractor, then the result produced from the operation is difference and borrow.

A full subtractor is a combinational circuit that performs the subtraction between two bits

taking into account borrow of the lower significant stage. Thus the full subtractors operate on

three inputs A, B and borrow from the lower significant stage and results in two outputs i.e

difference and borrow.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one common

binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit

When M=1, it becomes subtractor.


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Truth Table (Half Subtractor):

A B D(Difference) B( Borrow)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0


Circuit diagram:


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Truth Table (Full Subtractor):

A B Cin D(Difference) B( Borrow)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1


Circuit Diagram:


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PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM of 4-BIT BINARY ADDER/SUBTRACTOR:-


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TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1


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VIVA QUESTION :

1 .What is binary adder?Give its types.

2.What is priority encoder?.

3.What is parallel adder?.

4.Explain how single IC worked as a Adder/Subtractor.

5.How to perform the subtraction operation.

6.What is binary subtractor?Give its types.

7.What is look ahead carry adder?

8.What is half adder and full adder?Give their Boolean expression.

9.What is half subtractor and full subtractor?Give their Boolean expression.

10.What are the applications of full adder?

APPLICATIONS:

The Full adder acts as the building block of the 4bit/8bit binary/BCD adder ICs such as

7483.

It is used in the digital library.

It is used in digital computers.

It is used in arithmetic logic unit(ALU). One major application of subtractor is it is used in computers.It is used in ALU.

RESULT:

Thus the 4-bit binary adder/sub tractor is constructed using basic gates and MSI devices

and truth tables are verified.


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Truth Table for Parity Generator / Checker Using Basic Gates:

K Map Simplication for Parity Generator / Checker Using Basic Gates

EVEN PARITY ODD PARITY

Logic Diagram for Parity Generator / Checker Using Basic Gates

A B C EP OP

0 0 0 0 1

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 0


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EXPT NO. :4 DESIGN AND IMPLEMENTATION OF PARITY GENERATOR /

DATE : CHECKER USING BASIC GATES AND MSI DEVICES

Aim:

To design and implement the parity generator/checkerusing basic gates and MSI devices

and verify its performance with the verification table.



1Digital IC Trainer

kit- 1

2 IC

7486 2

74180 2

7404 1


4 Bread board - 1

Theory:

A parity bit is used for detecting errors during transmission of binary information. A

parity bit is an extra bit included with a binary message to make the number is either even o

odd. The message including the parity bit is transmitted and then checked at the receiver end

for errors. An error is detected if the checked parity bit doesnt correspond to the on

transmitted. The circuit that generates the parity bit in the transmitter is called a paritgenerator and the circuit that checks the parity in the receiver is called a parity checker.

In even parity, the added parity bit will make the total number is even amount. In od

parity, the added parity bit will make the total number is odd amount. The parity checker circui

checks for possible errors in the transmission. If the information is passed in even parity, then

the bits required must have an even number of 1s. An error occur during transmission, if th

received bits have an odd number of 1s indicating that one bit has changed in value durin

transmission.


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PIN DIAGRAM FOR IC 74180:

FUNCTION TABLE:

INPUTS OUTPUTS

Number of High Data

Inputs (I0I7)PE PO E O

EVEN 1 0 1 0

ODD 1 0 0 1

EVEN 0 1 0 1

ODD 0 1 1 0

X 1 1 0 0

X 0 0 1 1


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Procedure:




4.

Apply the logic inputs to the appropriate terminals of the ICs.5. Observe the logic output for the inputs applied.



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Logic Diagram :

Truth Table:

I7 I6 I5 I4 I3 I2 I1 I0 Active E O

0 0 0 0 0 0 0 1 1 1 0

0 0 0 0 0 1 1 0 0 1 0

0 0 0 0 0 1 1 0 1 0 1

Logic Diagram :

Truth Table:

I7 I6 I5 I4 I3 I2 I1 I0 Active E O

1 1 0 0 0 0 0 0 1 1 0

1 1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 0 1 0


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Result:

Thus the Parity Generator/Checker was designed & implemented using logic gates and

MSI devices and its performance was verified.


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Truth Table (2Bit magnitude Comparator):

Input Output

A1 A0 B1 B0 Ai= Bi Ai> Bi Ai< Bi

0 0 0 0 1 0 0

0 0 0 1 0 0 1

0 0 1 0 0 0 1

0 0 1 1 0 0 1

0 1 0 0 0 1 0

0 1 0 1 1 0 0

0 1 1 0 0 0 1

0 1 1 1 0 0 1

1 0 0 0 0 1 0

1 0 0 1 0 1 0

1 0 1 0 1 0 0

1 0 1 1 0 0 1

1 1 0 0 0 1 0

1 1 0 1 0 1 0

1 1 1 0 0 1 0

1 1 1 1 1 0 0

Realization of Boolean Expression for 2Bit magnitude Comparator


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EXPT NO. :5 DESIGN AND IMPLEMENTATION OF MAGNITUDE

DATE : COMPARATOR

AIM:

To design and implement a 2-bit magnitude comparator using logic gates.

COMPONENTS REQUIRED:S.NO COMPONENTS RANGE QUANTITY

1 Digital Trainer Kit - 1

2 ICs

7404 1

7486 1

7408 3

7432 1

3Connecting Wires /

Patch Cords- As required

4. Bread board - 1

THEORY:

The comparison of two numbers is an operation that determines if one number is greate

than, less than, or equal to the other number. A magnitude comparator is a combinational circui

that compares the two numbers, A and B, and determines their relative magnitude.

The circuit for comparing two n-bit numbers has 2nentries in the truth table and become

too cumbersome even with n=3. On the other hand comparator circuits possess a certain amoun

of regularity. The algorithm is a direct application of the procedure a person uses to compare threlative magnitudes of two numbers. Consider two numbers, A and B, with four digits each

consider

A=A3A2A1A0

B=B3B2B1B0

The two numbers are equal if all pairs of significant digits are equal: A3=B3, A2=B2, A1=B1an

A0=B0. When the numbers are binary, the digits are either 0 or 1, and the equality relation o

each pair of bits can be expressed logically with an EX-OR functionxi=Ai Bi+ Ai

Bi

for i=0,1,2,3

The binary variables A=B=X1X0=1.

A>B= AiBi+ X1A0B0

A


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Procedure:








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Logic Diagram:

8 Bit Magnitude Comparator

Truth Table:

A B A>B A=B A


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RESULT:

Thus the magnitude comparator was constructed using logic gates and verified with it

truth table.


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Truth Table of Multiplexer:

Data Select

Lines

Output

S1 S2 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

Circuit Diagram:


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EXPT NO. :6 DESIGN AND IMPLEMENTATION OF APPLICATION

DATE : USING MULTIPLEXERS/DEMULTIPLEXERS

Aim:

To design and implement a 4 to 1 multiplexer and 1 to 4 demultiplexer using logic gates.

Components Required:S.NO COMPONENTS RANGE QUANTITY

1 Digital Trainer kit - 1

2 ICs

7408 3

7432 1

7404 1


4 Bread board - 1

Theory:

Multiplexer:

The term multiplex means many into one. Multiplexing is the process of transmitting

large number of information over a single line. A digital multiplexer is a combinational circui

that selects one digital information from several sources and transmits the selected information

on a single output line. A multiplexer is also called a data selector since it selects one of many

inputs and steers the information to the output.

The 4 to 1 multiplexer has 4 input lines (D0-D3), a single output line (Y) and two selec

lines (S1and S2) to select one of the four input lines. From the truth table, a logical expression fo

the output in terms of the data input and the select inputs.

The data output Y = Data input D0, if S1=0 and S2=0

Therefore Y= D0S1S2

Similarly Y= D1S1S2; Y=D1when S1=0 and S2=1.

Demultiplexer:

A demultiplexer is a circuit that receives information on a single line and transmits thi

information on one of 2npossible output lines. The selection of specific output line is controlled b

the values of n selection lines.

The single input variable Din has a path to all four outputs, but the information is directe

to only one of the output lines decided by the selection lines A and B.


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Truth Table of Demultiplexer:

Enable

Selection

Lines

Data

InputOutput Line

A B Din Y0 Y1 Y2 Y3

0 X X X 0 0 0 0

1 0 0 0 0 0 0 0

1 0 0 1 1 0 0 0

1 0 1 0 0 0 0 0

1 0 1 1 0 1 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 1 0

1 1 1 0 0 0 0 01 1 1 1 0 0 0 1

Circuit Diagram:


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Procedure:





5.

Observe the logic output for the inputs applied.6. Verify the observed logic output with the verification/truth table given.

VIVA QUESTIONS:

1.What is mux?Why mux is called data selector?

2.What is the necessity of mux?

3.What are the types of mux?

4.What are the features of 8:1 mux?

5.What is multiplexer tree?6.What is demux?What are the types of demux?

7.What is demultiplexer tree?

8.What are the features of 4 line to 16 line Decoder/Demux?

9.Compare mux and demux.

10.What is the use of mux for logic design and combinational circuit design?

APPLICATIONS:

MULTIPLEXER:

It is used as a data selector to select one out of many data inputs.

It is used for simplification of logic design.

It is used in the data acquisition system.

It is used in designing the combinational circuits.

It is used in the D/A converters.

It is used to minimize the number of connections.

It is used in time division multiplexing at the sending end.

DEMULTIPLEXER:

We can implement some combinational circuit.

It is used in TDM system at receiving end.

Result:

Thus the combinational circuit, 4:1 multiplexer and 1:4 demultiplexer were designed

implemented and verified with their truth table.


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PIN DIAGRAM:

LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK

Serial in Serial out

1 1 02 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1


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EXPT NO. :7 DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS

DATE :

Aim:

To design, implement and verify the functioning of shift right registers (all types) using D

flip-flop.Components Required:


1Digital IC trainer

kit- 1

2 IC

7474 2

7408 2

7404 1

7432 1

3 Connecting wires - -

4 Bread Board - 1

Theory:

A register that is used to store binary information is known as a memory register. A

register capable of shifting binary information either to the right or the left is called a shif

register. Shift registers are classified into four types,

1. Serial-in Serial-out (SISO)

2. Serial-in Parallel-out (SIPO)3. Parallel-in Serial-out (PISO)

4. Parallel-in Parallel-out (PIPO)

Serial-in Serial-out (SISO):

This type of shift registers accepts data serially, i.e., one bit at a time on a single inpu

line. It produces the stored information on its single output also in serial output also in seria

form. Data may be shifted left (from low to high order bits) using shift-left register or shifte

right (from high to low order bits) using shift-right register.Serial-in Parallel-out (SIPO):

It consists of one serial input, and outputs are taken from all the flip-flop simultaneousl

in parallel. In this register, data is shifted in serially but shifted out in parallel. In order to shif

the data out in parallel, it is necessary to have all the data available at the outputs at the sam

time. Once the data is stored, each bit appears on its respective output line and all the bits are

available simultaneously, rather than on a bit by bit basis as with the serial output.


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SERIAL IN PARALLEL OUT:

TRUTH TABLE:

CLK DATA

OUTPUT

QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1

PARALLEL IN SERIAL OUT:


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Parallel-in Serial-out (PISO):

This type of shift register accepts data parallel, i.e., the bits are entered simultaneousl

into their respective flip-flops rather than a bit-by-bit basis on one line.

In this type of register, data inputs can be shifted either in or out of the register in parallel.

Procedure:1. Test the individual ICs with its specified verification table for proper working.




5.

Observe the logic output for the inputs applied.



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TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

CLK

DATA INPUT OUTPUT

DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0


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VIVA QUESTIONS:

1.What is shift register?

2.What are the modes of operation of a shift register?

3.How many clock pulses required in SISO mode to store a n-bit word?

4.What are the modes available in SISO and PISO?5.What is bidirectional shift register and universal shift register?

6.What are the capabilities of a universal shift register?

7.What is delay line?

8.What are the features of serial adder?

9.What is sequence generator?

10.What is shift register counters?Why it is called so?Give examples.

APPLICATIONS:

It is used for temporary data storage.

It is used for multiplication and division.

It is used as a delay line.

It is used as serial to parallel converter.

It is used as parallel to serial converter.

It is used as ring counter.

It is used as Twisted ring counter or Johnson counter.

Result:

Thus the shift registers using D flip-flop were implemented and studied their operation in

4 different modes.


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JK Excitation Table:

Qn Qn+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

State Table (3 bit synchronous binary UP counter)

Present State Next State JK Flip-Flop Inputs

A B C A

+

B

+

C

+

JA KA JB KB JC KC

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 0 1 1 0 X X 0 1 X

0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 1 1 0 X 0 1 X X 1

1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 0 0 0 X 0 X 1 X 1


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EXPT NO. :8(a) DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTERS

DATE :

Aim:

To design and implement a 3-bit synchronous binary up and down and up/down counte

using JK flip-flop.



1Digital Trainer

Kit- 1

2 ICs

7476 2

7408 1

7432 1


4 Bread Board - 1

Theory:

A Synchronous counter is also called parallel counter. In this counter the clock inputs o

all the flip-flops are connected together so that the input clock signal is applied simultaneousl

to each flip-flop. Also, only the LSB flip-flop C has its J and K inputs connected permanently t

Vcc while the J and K inputs of the other flip-flops are driven by some combination of flip-flo

outputs.

3Bit Synchronous Binary UP Counter:

The J and K inputs of the flip-flop B are connected to with QC. The J and K inputs of th

flip-flop A, are connected with AND operated output of QCand QB. The flip-flop C changes it

state when with the occurrence of negative transition at each clock pulse. The flip-flop B change

its state when QC= 1 and when there is negative transition at clock input. Flip-flop A changes it

state when QC= QB= 1 and when there is negative transition at clock input.

3Bit Synchronous Binary DOWN Counter:

The J and K inputs of the flip-flop B are connected to with QC. The J and K inputs of th

flip-flop A, are connected with AND operated output of QC and QB. The flip-flop C changes it

state when with the occurrence of negative transition at each clock pulse. The flip-flop B change

its state when QC= 1 and when there is negative transition at clock input. Flip-flop A change

its state when QC= QB= 1 and when there is negative transition at clock input.


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Realization of JK inputs for 3 Bit Synchronous Binary Up Counter:

Circuit Diagram Of 3 Bit Synchronous Binary Up Counter:


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Procedure:





5.



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State Table (3 bit synchronous binary DOWN counter)

Present State Next State JK Flip-Flop Inputs

A B C A+ B+ C+ JA KA JB KB JC KC

0 0 0 1 1 1 1 X 1 X 1 X

0 0 1 0 0 0 0 X 0 X X 1

0 1 0 0 0 1 0 X X 1 1 X

0 1 1 0 1 0 0 X X 0 X 1

1 0 0 0 1 1 X 1 1 X 1 X

1 0 1 1 0 0 X 0 0 X X 1

1 1 0 1 0 1 X 0 X 1 1 X

1 1 1 1 1 0 X 0 X 0 X 1

Realization of JK inputs for 3 Bit Synchronous Binary Down Counter:


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Circuit Diagram Of 3 Bit Synchronous Binary Down Counter:

State Diagram of 3 Bit Synchronous Up/Down Counter:


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Truth Table For Bit Synchronous Up/Down Counter:

Input

Up/Down

Present State

QA QB QC

Next State

QA+1 QB+1 QC+1

A

JA KA

B

JB KB

C

JC KC

0 0 0 0 1 1 1 1 X 1 X 1 X

0 1 1 1 1 1 0 X 0 X 0 X 1

0 1 1 0 1 0 1 X 0 X 1 1 X

0 1 0 1 1 0 0 X 0 0 X X 1

0 1 0 0 0 1 1 X 1 1 X 1 X

0 0 1 1 0 1 0 0 X X 0 X 1

0 0 1 0 0 0 1 0 X X 1 1 X

0 0 0 1 0 0 0 0 X 0 X X 1

1 0 0 0 0 0 1 0 X 0 X 1 X

1 0 0 1 0 1 0 0 X 1 X X 1

1 0 1 0 0 1 1 0 X X 0 1 X

1 0 1 1 1 0 0 1 X X 1 X 1

1 1 0 0 1 0 1 X 0 0 X 1 X

1 1 0 1 1 1 0 X 0 1 X X 1

1 1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 1 0 0 0 X 1 X 1 X 1

Realization of JK inputs for 3 Bit Synchronous Binary Up/Down Counter


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Circuit Diagram Bit Synchronous Up/Down Counter


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Result:

Thus the synchronous up, down and up/down counters were designed using JK flip-flo

and verified with their state table.


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Verification Table (4 bit binary ripple up counter):

Clock

PulseQ3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

Circuit Diagram:


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EXPT NO. :8(b) DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS COUNTERS

DATE :

Aim:

To design and implement a 4-bit asynchronous binary up and down counter using JK flip

flop.

Components Required:S.NO COMPONENTS RANGE QUANTITY

1Digital IC trainer

kit- 1

2

IC

7476 2

3 7400 1

4 - 1

5 Bread board - 1


Theory:

A counter, by function, is a sequential circuit consisting of a set of flip-flops connected in

suitable manner to count the sequence of the input pulses presented to it digital form. A

asynchronous counter, each flip-flop is triggered by the output from the previous flip-flop whic

limits its speed of operation. The settling time in asynchronous counters, is the cumulative sum

of the individual settling times of flip-flops. It is also called a serial counter.

The asynchronous counter is the simplest in terms of logical operations, and is therefor

the easiest to design. In this counter, all the flip-flops are not under the control of a single clock

Here, the clock pulse is applied to the first flip-flop, i.e. the least significant bit stage of th

counter, and the successive flip-flop is triggered by the output is constructed using clocked JK

flip-flops. The system clock, a square wave, drives flip-flop A (LSB). The output of A drives flip

flop B, the output of B drives flip-flop C. all the J and K inputs connected to Vcc (High (1)), whic

means that each flip-flop toggles on the edge (-ve) clock pulse.

Consider initially all flip-flops to be in the logical 0 state (i.e. QA=QB=QC=QD=0). A

negative transition in the clock input which drives flip-flop A causes QAto change from 0 to 1

Flip-flop B doesnt change its state since it is also requires negative transition at its clock inpu

i.e. it requires its clock input (QA) to change from 1 to 0. With arrival of second clock pulse to flip

flop A, QAgoes from 1 to 0. This change of state creates the negative going edge needed to trigge

flip-flop B, and thus QBgoes from 0 to 1. Before the arrival of the 16thclock pulse, all the flip

flops are in the logical 1 state. Clock pulse 16 causes QA, QB, QC and QD to go logical 0 state i

turn.


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Verification Table (4 bit binary ripple down counter):

Clock

PulseQ3 Q2 Q1 Q0

0 1 1 1 1

1 1 1 1 0

2 1 1 0 1

3 1 1 0 0

4 1 0 1 1

5 1 0 1 0

6 1 0 0 1

7 1 0 0 0

8 0 1 1 1

9 0 1 1 0

10 0 1 0 1

11 0 1 0 0

12 0 0 1 113 0 0 1 0

14 0 0 0 1

15 0 0 0 0

Circuit Diagram:


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Procedure:





5.



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TRUTH TABLE For MOD - 10 Ripple Counter:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 0 0 0

Logic Diagram for MOD - 10 Ripple Counter:


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TRUTH TABLE for MOD - 12 Ripple Counter:

:CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 0 0

Logic Diagram for MOD 12 Ripple Counter:


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Result:

Thus the asynchronous up, down and MOD counters were constructed and tested th

operations with the help of their verification tables.


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PROGRAM:

MULTIPLEXER:

library ieee;use ieee.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Mux is

port( I3: in std_logic_vector(2 downto 0);I2: in std_logic_vector (2 downto 0);

I1: in std_logic_vector(2 downto 0);I0: in std_logic_vector(2 downto 0);

S: in std_logic_vector(1 downto 0);O: out std_logic_vector(2 downto 0)

);end Mux;

architecture behv2 of Mux isbegin

O


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EXPT NO. :9(a) SIMULATION OF COMBINATIONAL CIRCUITS USING

DATE : HARDWARE DESCRIPTION LANGUAGE

Aim:

To design and implement combinational circuits using VHSIC Hardware Descriptio

Language (VHDL).



1 Computer - 1

2 ModelSim Software 1

Theory:

The ModelSim debug environments broad set of intuitive capabilities for Verilog,VHDL

and SystemC make it the choice for ASIC and FPGA design.

ModelSim eases the process of finding design defects with an intelligently engineere

debug environment. The ModelSim debug environment efficiently displays design data fo

analysis and debug of all languages.

ModelSim allows many debug and analysis capabilities to be employed post-simulation on

saved results, as well as during live simulation runs. For example, the coverage viewer analyze

and annotates source code with code coverage results, including FSM state and transition

statement, expression, branch, and toggle coverage.

Signal values can be annotated in the source window and viewed in the waveform viewereasing debug navigation with hyperlinked navigation between objects and its declaration an

between visited files.

Race conditions, delta, and event activity can be analyzed in the list and wave windows

User-defined enumeration values can be easily defined for quicker understanding of simulation

results. For improved debug productivity, ModelSim also has graphical and textual dataflow

capabilities.

Procedure:

Open ModelSim Simulator. Change the directory to the desired location.

Open a new VHDL source from file menu.

Type and Save the program with proper name in the specified directory.

Compile the program by clicking compile button in the menu bar.

Select the target program from the work space and stimulate.

Add wave form for the signals.

Force the signals to assign input values.

Run the program by clicking Run button in menu bar.

Check the wave form to obtain results.


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WAVE FROMS:

MULTIPLEXER

ADDER


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PROGRAM:

HALF ADDER

module ha(a,b,sum,carry);

input a,b;

output sum,carry;

xor(sum,a,b);

and(carry,a,b);

endmodule

FULL ADDER

module fa(a,b,cin ,s,cout);

input a;

input b;

input cin;

output s;

output cout;

wire s1,c1,c2;

xor(s1,a,b);

and(c1,a,b);

and(c2,cin,s1);

or(cout,c1,c2);

endmodule


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EXPT NO. :9(b) SIMULATION OF COMBINATIONAL CIRCUITS USING

DATE : HARDWARE DESCRIPTION LANGUAGE

Aim:

To design and implement combinational circuits using Verilog Hardware Descriptio

Language (HDL).



1 Computer - 1


Theory:

The ModelSim debug environments broad set of intuitive capabilities for Verilog, VHDL, an

SystemC make it the choice for ASIC and FPGA design.

ModelSim eases the process of finding design defects with an intelligently engineere

debug environment. The ModelSim debug environment efficiently displays design data fo






Signal values can be annotated in the source window and viewed in the waveform viewereasing debug navigation with hyperlinked navigation between objects and its declaration an





capabilities.

Procedure:

Open ModelSim Simulator.

Change the directory to the desired location.

Open a new Verilog HDL source from file menu.









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HALF SUBTRACTOR

module hs(a,b,s,diff,borrow);

input a,b;

output diff,borrow;

xor(diff,a,b);

not(nota,a);

and(borrow,nota,b);

endmodule

FULL SUBTRACTOR

module fs(a,b,c,diff,borrow);

input a,b,c;

output diff,borrow;

wire b1,b2,b3,abar;

not(abar,a);

xor(diff,a,b,c);

and(b1,b,c);

and(b2,abar,c);

and(b3,abar,b);

or(borrow,b1,b2,b3);

endmodule


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MULTIPLEXER: (2:1)

module mux2to1 (a,b,s,y);

input a,b,s;

output y;

assign y=s?a:b;

endmodule

DEMULTIPLEXER: (1:2)

module demux1to2(a,s,y1,y2);

input a,s;

output y1,y2

reg y1,y2;

always@(a,s)

begin

case(s)

0:y1=a;

default: y2=a;

endcase

end

endmodule


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APPLICATIONS:

Used in designing and simulating the digital circuits.

used in writing the test benches for exercising and verifying the correctness of a design.

VIVA QUESTIONS:

1.

What is Verilog HDL?2. What are the three basic description styles supported by Verilog HDL?

3. Define module.

4. What is logic synthesis in HDL?

5. What is gate level modeling?

6. Mention any two uses of HDL.

7. What is data flow modeling?

RESULT:

Thus the combinational circuits are tested and implemented using Verilog


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PROGRAM:

JK FLIP FLOP:

library ieee;use ieee.std_logic_1164.all;

entity jkff is

port(j,k,clk:in std_logic;q,q1,z:inout std_logic);end jkff;

architecture arc of jkff isbegin

process(clk)

begin

if clk='1' thenz


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EXPT NO. :10(a) SIMULATION OF SEQUENTIAL CIRCUITS USING HDL

DATE :

Aim:

To design and implement Sequential circuits using VHSIC Hardware Description

Language (VHDL).



1 Computer - 1


Theory:

The ModelSim debug environments broad set of intuitive capabilities for Verilog, VHDL

and SystemC make it the choice for ASIC and FPGA design.

ModelSim eases the process of finding design defects with an intelligently engineeredebug environment. The ModelSim debug environment efficiently displays design data fo






Signal values can be annotated in the source window and viewed in the waveform viewer

easing debug navigation with hyperlinked navigation between objects and its declaration an





capabilities.

Procedure:


Change the directory to the desired location. Open a new VHDL source from file menu.









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temp(1)


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Result:

Thus the Sequential circuits are tested and implemented using VHDL.


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RIPPLE CARRY COUNTER:

module counter(count,clk,clr);

input clk,clr;

output[3:0] count;

wire[3:0] q,qbar;

tflp ff1(count[0],q[0],clk,clr,1b1);

tflp ff1(count[1],q[1],count[0],clr,1b1);



endmodule

MOD 10 COUNTER:

module mod10(reset,clk,a,z);

input clk,reset;

input[3:0] a;

output[3:0] z;

reg[3:0] z;

reg[3:0] count;

always@(posedge clk,reset)

begin

if(reset==1b1)

begin

z=4b0000;

count=4b0000

end

else

begin

z=count;

count=count+4b0001;

if(count==4b1010)


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EXPT NO. :10(b) SIMULATION OF SEQUENTIAL CIRCUITS USING HDL

DATE :

Aim:

To design and implement combinational circuits using Verilog Hardware Description

Language (HDL).



1 Computer - 1


Theory:

The ModelSim debug environments broad set of intuitive capabilities for Verilog, VHDL, an

SystemC make it the choice for ASIC and FPGA design.

ModelSim eases the process of finding design defects with an intelligently engineeredebug environment. The ModelSim debug environment efficiently displays design data fo






Signal values can be annotated in the source window and viewed in the waveform viewer

easing debug navigation with hyperlinked navigation between objects and its declaration an





capabilities.

Procedure:


Change the directory to the desired location.

Open a new Verilog HDL source from file menu.









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count = 4b0000;

end

end

endmodule

SERIAL IN SERIAL OUT:

module siso(sout,sin,clk);

input sin,clk;

output sout;

reg sout;

always@(posedge clk)

begin

sout


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out


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PARALLEL IN PARALLEL OUT:

module pipo(sout,sin,clk);

input [3:0]pin;

input clk;

output [3:0]pout;

reg[3:0] pout;

always@(posedge clk)

begin

pout


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APPLICATIONS:

Used in designing and simulating the digital circuits.

used in writing the test benches for exercising and verifying the correctness of a design.

VIVA QUESTIONS:

1.

What is Verilog HDL?2. What are the three basic description styles supported by Verilog HDL?

3. Define module.

4. What is logic synthesis in HDL?

5. What is gate level modeling?

6. Mention any two uses of HDL.

7. What is data flow modeling?

Documents

Cs6211 - Digital Lab Manual