CS4315A. Berrached:CMS:UHD1 Operating Systems and Computer Organization Chapter 4

CS4315 A. Berrached:CMS:UHD 1

Operating Systems and Computer Organization

Chapter 4


Operating System and Computer Organization

• Organization of Conventional Computers• The ALU• The Control Unit• The Memory Unit• I/O Devices• Interrupts• Hardware protection


Conventional Computer Organization


The ALU

Status Registers

Operands

Result

MDR MAR

To/from main memory

R1R2

Rn….

Functional Unit

CMD


Memory Data Access

Main Memory


Program Specification


Machine Language


Control Unit


Control Unit Operation

• Instruction Fetch Phase: instruction is retrieved from memory

• Instruction Decode Phase: instruction is decoded and control signals generated

• Instruction Execute Phase: ALU op, memory data access, or I/O op is executed.


Control Unit Operation

PC = <Machine-Start-Address> ;

IR = Memory[PC] ;

haltFlag = CLEAR ;

Decode(IR);

while (haltFlag not SET) {

Execute(IR);

PC = PC + InstructionSize;

IR = Memory[PC] ;

Decode(IR);

}


How does it all start?• When the computer is started, the control unit branches to a

fixed memory location; e.g. initial PC value hardwired.• The fixed location is a ROM address that contains a the BIOS

loader.• The BIOS loader loads a “bootstrap loader” from the disk

“boot sector” into memory and branches to the bootstrap loader program.

• The bootstrap loader may be comprehensive enough to load the nucleus of the OS; Otherwise, it loads a loader program that does so.

• Once bootstrap phase is done, any program can be run by loading it in memory and loading its initial address in the PC (fetch-decode-exec algorithm)


Bootstrapping

Bootstrap loader (“boot sector”)

Primary Memory

1

0x0001000

Fetch UnitFetch Unit

Decode UnitDecode Unit

Execute UnitExecute Unit

00001000000100

……

PC

IR

BIOS loader 0x0000100


BootstrappingBootstrap loader (“boot sector”)

Primary Memory

Loader

1

2




00010000001000

……

PC

IR

BIOS loader 0x00001000x0001000

0x0008000


BootstrappingBootstrap loader (“boot sector”)

Primary Memory

Loader

OS

12

3Fetch UnitFetch Unit



00080000008000

……

PC

IR


0x0008000

0x000A000


Bootstrapping

Bootstrap loader (“boot sector”)

Primary Memory

Loader

OS

12

3

4. Initialize hardware5. Create user environment6. …




000A000000A000

……

PC

IR


0x0008000

0x000A000


Primary Memory Unit• Main (Primary) Memory holds both program and

data while they are being executed by CPU.• The main memory interface consists of the

registers: MAR, MDR, CMD.• Unit of information accessed depends on the width

of memory and width of data bus.• Max. addressing space depends on width of

address bus.• One request at a time.• CPU and I/O devices may contend for memory

access.


Primary Memory Unit

MAR

MDR

Command

012

n-1

1234 98765Read Op:

1234

1. Load MAR with address

read

2. Load Command with “read”

98765

3. Data will then appear in the MDR


I/O devices• Each I/O device consists of a device controller and

the physical device itself.• Devices:

- storage devices: for permanent storage (e.g. disk, tape)

- communication devices: to transfer data from the computer to another machine (e.g.

keyboard, a terminal display, or a serial port to a modem or a network).


I/O Devices (cont.)

• Device controller: hardware that connects the device to the computer.– continuously monitors and controls the

operation of the device.– provides an interface to the computer.

• Device Manager: program (part of the OS) that manages device controllers


The Device-Controller-Software Relationship

Application Program

Device ControllerDevice Controller

DeviceDevice

Sof

twar

e in

the

CP

U

Abstract I/O Machine

•Device manager: Program to manage device controllers


Device Controller Interface

CommandCommand StatusStatusData 0Data 0

Data 1Data 1

Data n-1Data n-1LogicLogic

busy done Error code . . .. . .busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined)


I/O Devices (cont.)• How does the computer communicate with an I/O device?

– device controller has a set of registers: Command reg., Status reg., Data regs., Address regs, etc.

– Status reg.: tells the computer the status of device: idle, busy, non functional, etc.

– A process can request an operation from device by placing a command in device’s Command reg.

– Data regs. Are used to exchange data

– Address regs: used to indicate address of source/destination


Performing a Write Operation

while(deviceNo.busy || deviceNo.done) <waiting>;deviceNo.data[0] = <value to write>deviceNo.command = WRITE;while(deviceNo.busy) <waiting>;deviceNo.done = TRUE;

• Devices much slower than CPU• CPU waits while device operates• Would like to multiplex CPU to a different

process while I/O is in process


CPU-I/O Overlap

CPUCPU

DeviceDevice

…

Rea

dy P

roce

sses

CPUCPU

DeviceDevice

…

Rea

dy P

roce

sses

I/O Operation

CPUCPU

DeviceDevice

…

Rea

dy P

roce

sses

Uses CPU


I/O Devices (cont.)• How does the computer operate on device

controller registers? How does it identify each device?

1. Instruction set of the CPU may have special instructions to operate on I/O devices. E.g.

Input DeviceN, DeviceRegisterN, Rn Output Rn, DeviceN, DeviceRegisterN

etc.

2. Memory Mapped I/O


Memory Mapped I/O

• A set of memory addresses are reserved for I/O devices. E.g: 0000 to 3FF in Intel 8086 – each device is assigned a sub-set of memory

addresses.– A memory address is assigned to each register

of each device controller• regular CPU instructions are used to interact with

device controller.


I/O Devices (cont.)How does the CPU know when a device controller has

completed the requested operation?

• 1. Polling: CPU continually check status register of device controller

• 2. Interrupt driven I/O: device controller sends a signal to CPU through the bus.

– bus must support interrupts

– CPU must include an interrupt flag

– CPU instruction set must include instructions to test and set/clear interrupt flag.


Determining When I/O is Complete

CPUCPU

DeviceDevice DeviceDevice DeviceDevice

Interrupt Pending

• CPU incorporates an “interrupt pending” flag• When device.busy FALSE, interrupt pending flag is set• Hardware “tells” OS that the interrupt occurred• Interrupt handler part of the OS makes process ready to run


Fetch-Execute Cycle with InterruptPC = <Machine-Start-Address> ;

IR = Memory[PC] ;

haltFlag = CLEAR ;

Decode(IR);

while (haltFlag not SET) {

Execute(IR);

PC = PC + InstructionSize;

if (InterruptFlag) {

save current PC; // (e.g. in system stack)

PC = AddressOfInterruptHandler;

reset InterruptFlag;

}

IR = Memory[PC] ;

Decode(IR);

}


Hardware Protection

• Dual-Mode Operation

• I/O Protection

• Memory Protection


Dual-Mode Operation

• Sharing system resources requires that the operating system ensures a level of protection to the users:– an incorrect program can not cause other

programs to execute incorrectly– that a user program cannot have access

resource for it does not have permission– some operations should not be performed by

user programs


Dual-Mode Operation (Cont.)

• Provide hardware support to differentiate between at least two modes of operations:

1. User mode - execution done on behalf of the user

2. Supervisor mode (also called monitor mode or privileged mode or protected mode or system mode etc.) - execution done on behalf of the operating system



• Mode bit is added to computer hardware (to CPU) to indicate the current mode.

Supervisor mode (0) user mode (1)• Instruction set: privileged instructions and non-

privileged instructions - privileged instructions can be executed only in supervisor mode.

• Operating system can execute any instruction.• Must insure that a user program can not execute

privileged instructions directly.


Going from User Mode to Supervisor Mode

• When a user program need service from the OS (e.g. open a file, read, write, allocate memory etc.), it makes a system call: i.e. a call to one of the OS functions.

• OS functions must run in supervisor mode. • User processes run in user mode. • computer designers had to come up with some kind of

approach that would allow a user process to miraculously change the CPU mode to supervisor and branch to one of these OS functions simultaneously. The trap instruction is just the ticket.


Trap Instruction

• A trap instruction is a machine-level instruction that:

– Switches the CPU mode to supervisor

– Looks up the address of the target function in a kernel-space trap table

– Branches to the entry point of the kernel-space function using the address from the trap table

• The trick is that the instruction does all three of these steps rather than just one or two. And trap is the only instruction that sets the CPU mode bit to supervisor.


• The system call is translated into a trap instruction– the trap instruction is a machine level

instruction that is part of the instruction set of the processor

• The trap instruction will do the following:– change mode-bit to supervisor mode– jump to a trap handler which will determine

which OS function is being requested etc.



Processor must provide the following:• A Mode-bit flag• Instruction set: privileged instructions and non-

privileged instructions• A trap instruction


I/O protection• Instruction to change the mode must be privileged• I/O operation are privileged instructions• How can user program perform I/O?• It makes a system call to OS. • When a system call is made a trap instruction is

executed: – sets the mode to supervisor mode– OS function verifies that parameters are correct and

legal, executes the request, sets mode to user mode, and returns control to user program


Memory Protection


Example of Memory Protection


Protection Hardware

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CS4315A. Berrached:CMS:UHD1 Operating Systems and Computer Organization Chapter 4