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Interrupts. CS318 Project #3. Credits. Google http://www.beyondlogic.org/interrupts/interupt.htm. On a Interrupt Request. Processor finishes current instruction Pushes stuff on stack Think of only EFLAGS and EIP for now Invokes appropriate Interrupt Service Routine - PowerPoint PPT Presentation
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CS318 Project #3
Interrupts
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Credits Google http://www.beyondlogic.org/interrupts/
interupt.htm
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On a Interrupt Request Processor finishes current
instruction Pushes stuff on stack
Think of only EFLAGS and EIP for now
Invokes appropriate Interrupt Service Routine
iret – pops stuff off of stack
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How many Interrupts ? 256 total Most of them software interrupts 15 hardware interrupts The Programmable Interrupt
Controller (PIC) handles hardware interrupts
INT (Hex) IRQ Common Uses
00 - 01 Exception Handlers -
02 Non-Maskable IRQ Non-Maskable IRQ (Parity Errors)
03 - 07 Exception Handlers -
08 Hardware IRQ0 System Timer
09 Hardware IRQ1 Keyboard
0A Hardware IRQ2 Redirected
0B Hardware IRQ3 Serial Comms. COM2/COM4
0C Hardware IRQ4 Serial Comms. COM1/COM3
0D Hardware IRQ5 Reserved/Sound Card
0E Hardware IRQ6 Floppy Disk Controller
0F Hardware IRQ7 Parallel Comms.
10 - 6F Software Interrupts -
70 Hardware IRQ8 Real Time Clock
71 Hardware IRQ9 Redirected IRQ2
72 Hardware IRQ10 Reserved
73 Hardware IRQ11 Reserved
74 Hardware IRQ12 PS/2 Mouse
75 Hardware IRQ13 Math's Co-Processor
76 Hardware IRQ14 Hard Disk Drive
77 Hardware IRQ15 Reserved
78 - FF Software Interrupts -
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Hardware Interrupts Two 8259 PIC IC chips Base addresses 0x20h and
0xA0h
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PIC
IRQ 0 is asserted
Control logic
Check if IRQ is masked
Interrupt Mask
Register (IMR)
Control logic
Hold in IRR until processed
Interrupt Mask
Register (IMR)
Interrupt Request Register
(IRR)
Control logic
Send INT to processor
Interrupt Mask
Register (IMR)
Interrupt Request Register
(IRR)
Control logic
Priority Resolver
After finishing current instruction, checks if interrupts disabled in
EFLAGS
Processor replies with INTA
Interrupt Mask
Register (IMR)
Interrupt Request Register
(IRR)
Control logic
Priority Resolver
Store in ISR, reset bit in IRR
Interrupt Mask
Register (IMR)
Interrupt Request Register
(IRR)
Control logic
Priority Resolver
In Service Register
(ISR)
Processor asks for data
Interrupt Mask
Register (IMR)
Interrupt Request Register
(IRR)
Control logic
Priority Resolver
In Service Register
(ISR)
PIC supplies data
Interrupt Mask
Register (IMR)
Interrupt Request Register
(IRR)
Control logic
Priority Resolver
In Service Register
(ISR)
Processor sends EOI
Interrupt Mask
Register (IMR)
Interrupt Request Register
(IRR)
Control logic
Priority Resolver
In Service Register
(ISR)
PIC resets ISR
Interrupt Mask
Register (IMR)
Interrupt Request Register
(IRR)
Control logic
Priority Resolver
In Service Register
(ISR)
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Small matter of cascading PICs
2nd PIC at 0xA0 was a later addition Setup in master-slave configuration
to preserve compatibility You don’t need to worry about it
IRQ 2 routed via IRQ9
INT of PIC2 via IRQ2
All interrupts from PIC2 routed via PIC1 to
processor
EOI for interrupts from PIC2 must be sent to
both PICs
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The End Questions?
