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CS252 Graduate Computer Architecture Lecture 16 Multiprocessor Networks (con’t) March 29 th , 2010. John Kubiatowicz Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~kubitron/cs252. Review: The Routing problem: Local decisions. - PowerPoint PPT Presentation
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CS252Graduate Computer Architecture
Lecture 16
Multiprocessor Networks (con’t)March 29th, 2010
John Kubiatowicz
Electrical Engineering and Computer Sciences
University of California, Berkeley
http://www.eecs.berkeley.edu/~kubitron/cs252
3/29/2010 cs252-S10, Lecture 16 2
Review: The Routing problem: Local decisions
• Routing at each hop: Pick next output port!
Cross-bar
InputBuffer
Control
OutputPorts
Input Receiver Transmiter
Ports
Routing, Scheduling
OutputBuffer
3/29/2010 cs252-S10, Lecture 16 3
• Problem: Low-dimensional networks have high k– Consequence: may have to travel many hops in single dimension– Routing latency can dominate long-distance traffic patterns
• Solution: Provide one or more “express” links
– Like express trains, express elevators, etc» Delay linear with distance, lower constant» Closer to “speed of light” in medium» Lower power, since no router cost
– “Express Cubes: Improving performance of k-ary n-cube interconnection networks,” Bill Dally 1991
• Another Idea: route with pass transistors through links
Reducing routing delay: Express Cubes
3/29/2010 cs252-S10, Lecture 16 4
Review: Virtual Channel Flow Control
• Basic Idea: Use of virtual channels to reduce contention– Provided a model of k-ary, n-flies
– Also provided simulation
• Tradeoff: Better to split buffers into virtual channels– Example (constant total storage for 2-ary 8-fly):
3/29/2010 cs252-S10, Lecture 16 5
When are virtual channels allocated?
• Two separate processes:– Virtual channel allocation– Switch/connection allocation
• Virtual Channel Allocation– Choose route and free output virtual channel – Really means: Source of link tracks channels at destination
• Switch Allocation– For incoming virtual channel, negotiate switch on outgoing pin
OutputPorts
Input Ports
Cross-BarHardware efficient designFor crossbar
3/29/2010 cs252-S10, Lecture 16 6
Deadlock Freedom• How can deadlock arise?
– necessary conditions:» shared resource» incrementally allocated» non-preemptible
– channel is a shared resource that is acquired incrementally» source buffer then dest. buffer» channels along a route
• How do you avoid it?– constrain how channel resources are allocated– ex: dimension order
• Important assumption: – Destination of messages must always remove messages
• How do you prove that a routing algorithm is deadlock free?
– Show that channel dependency graph has no cycles!
3/29/2010 cs252-S10, Lecture 16 7
Consider Trees
• Why is the obvious routing on X deadlock free?– butterfly?
– tree?
– fat tree?
• Any assumptions about routing mechanism? amount of buffering?
3/29/2010 cs252-S10, Lecture 16 8
Up*-Down* routing for general topology• Given any bidirectional network
• Construct a spanning tree
• Number of the nodes increasing from leaves to roots
• UP increase node numbers
• Any Source -> Dest by UP*-DOWN* route– up edges, single turn, down edges
– Proof of deadlock freedom?
• Performance?– Some numberings and routes much better than others
– interacts with topology in strange ways
3/29/2010 cs252-S10, Lecture 16 9
Turn Restrictions in X,Y
• XY routing forbids 4 of 8 turns and leaves no room for adaptive routing
• Can you allow more turns and still be deadlock free?
+Y
-Y
+X-X
3/29/2010 cs252-S10, Lecture 16 10
Minimal turn restrictions in 2D
West-first
north-last negative first
-x +x
+y
-y
3/29/2010 cs252-S10, Lecture 16 11
Example legal west-first routes
• Can route around failures or congestion
• Can combine turn restrictions with virtual channels
3/29/2010 cs252-S10, Lecture 16 12
General Proof Technique• resources are logically associated with channels
• messages introduce dependences between resources as they move forward
• need to articulate the possible dependences that can arise between channels
• show that there are no cycles in Channel Dependence Graph
– find a numbering of channel resources such that every legal route follows a monotonic sequence no traffic pattern can lead to deadlock
• network need not be acyclic, just channel dependence graph
3/29/2010 cs252-S10, Lecture 16 13
Example: k-ary 2D array• Thm: Dimension-ordered (x,y) routing
is deadlock free
• Numbering– +x channel (i,y) -> (i+1,y) gets i
– similarly for -x with 0 as most positive edge
– +y channel (x,j) -> (x,j+1) gets N+j
– similary for -y channels
• any routing sequence: x direction, turn, y direction is increasing
• Generalization: – “e-cube routing” on 3-D: X then Y then Z
1 2 3
01200 01 02 03
10 11 12 13
20 21 22 23
30 31 32 33
17
18
1916
17
18
3/29/2010 cs252-S10, Lecture 16 14
Channel Dependence Graph
1 2 3
01200 01 02 03
10 11 12 13
20 21 22 23
30 31 32 33
17
18
1916
17
18
1 2 3
012
1718 1718 1718 1718
1 2 3
012
1817 1817 1817 1817
1 2 3
012
1916 1916 1916 1916
1 2 3
012
3/29/2010 cs252-S10, Lecture 16 15
More examples:• What about wormhole routing on a ring?
• Or: Unidirectional Torus of higher dimension?
012
3
45
6
7
3/29/2010 cs252-S10, Lecture 16 16
Breaking deadlock with virtual channels
• Basic idea: Use virtual channels to break cycles– Whenever wrap around, switch to different set of channels
– Can produce numbering that avoids deadlock
Packet switchesfrom lo to hi channel
3/29/2010 cs252-S10, Lecture 16 17
General Adaptive Routing• R: C x N x -> C• Essential for fault tolerance
– at least multipath
• Can improve utilization of the network• Simple deterministic algorithms easily run into bad
permutations
• fully/partially adaptive, minimal/non-minimal• can introduce complexity or anomalies • little adaptation goes a long way!
3/29/2010 cs252-S10, Lecture 16 18
Paper Discusion: Linder and Harden “An Adaptive and Fault Tolerant Wormhole”
• General virtual-channel scheme for k-ary n-cubes– With wrap-around paths
• Properties of result for uni-directional k-ary n-cube:– 1 virtual interconnection network
– n+1 levels
• Properties of result for bi-directional k-ary n-cube:– 2n-1 virtual interconnection networks
– n+1 levels per network
3/29/2010 cs252-S10, Lecture 16 19
Example: Unidirectional 4-ary 2-cube
Physical Network• Wrap-around channels
necessary but cancause deadlock
Virtual Network• Use VCs to avoid deadlock• 1 level for each wrap-around
3/29/2010 cs252-S10, Lecture 16 20
Bi-directional 4-ary 2-cube: 2 virtual networks
Virtual Network 1 Virtual Network 2
3/29/2010 cs252-S10, Lecture 16 21
Use of virtual channels for adaptation• Want to route around hotspots/faults while avoiding deadlock• Linder and Harden, 1991
– General technique for k-ary n-cubes» Requires: 2n-1 virtual channels/lane!!!
• Alternative: Planar adaptive routing– Chien and Kim, 1995– Divide dimensions into “planes”,
» i.e. in 3-cube, use X-Y and Y-Z
– Route planes adaptively in order: first X-Y, then Y-Z» Never go back to plane once have left it» Can’t leave plane until have routed lowest coordinate
– Use Linder-Harden technique for series of 2-dim planes» Now, need only 3 number of planes virtual channels
• Alternative: two phase routing– Provide set of virtual channels that can be used arbitrarily for routing– When blocked, use unrelated virtual channels for dimension-order
(deterministic) routing– Never progress from deterministic routing back to adaptive routing
3/29/2010 cs252-S10, Lecture 16 22
Administrative• Midterm I: Still grading
– I’ve posted solutions, so you can look at them
– I hope to have exams graded soon (by end of week at latest)» Sorry about this – two proposals and a root-canal got in the way
• Should be working full blast on project by now!– I’m going to want you to submit an update next week on
Wednesday
– We will meet shortly after that
3/29/2010 cs252-S10, Lecture 16 23
Midterm Problem 2 solution: Bypassing
…
Reg
iste
r L
ooku
p
EX2
MEM1
EX3
MEM2
Reo
rder
Bu
ffer
and
Rea
dy I
nstr
uctio
nS
ele
ctio
n Lo
gic
EX1
FP1
EX2
FP2
EX3
FP3
…
FP5
…
FP4
EX1
Addr
Rea
dyIn
stru
ctio
ns
…
ROB D
Reg
iste
r W
riteb
ack
[I,L,G]
[I,L,G]
[I,L,G][I
][I]
[I] [A
] [G,M] [D]
[I][I,A]
[I,A,G,M]
[I,A,G,M]
[I,A,G,M,D]
[L,G]
All bypass results available for either pipeline. Also,results bypassed to end ofregister lookup stage.
Bypass for Stores
3/29/2010 cs252-S10, Lecture 16 24
Paper Discussion: Tiled CMP On-Chip Networks• James Balfour and William Dally:
“Design Tradeoffs for Tiled CMP On-Chip Networks”• Detailed model of 64-node network
– Wire model from “Future of Wires” paper– Explicit layout on 6-metal technology
» Partitioned crossbar» Worry about VIAs
Input BufferPartitionedCrossbar
3/29/2010 cs252-S10, Lecture 16 25
CMP Network paper (con’t)
• 5-different network topologies
• Results
3/29/2010 cs252-S10, Lecture 16 26
Message passing• Sending of messages under control of
programmer– User-level/system level?
– Bulk transfers?
• How efficient is it to send and receive messages?– Speed of memory bus? First-level cache?
• Communication Model:– Synchronous
» Send completes after matching recv and source data sent
» Receive completes after data transfer complete from matching send
– Asynchronous» Send completes after send buffer may be reused
3/29/2010 cs252-S10, Lecture 16 27
Synchronous Message Passing
• Constrained programming model.
• Deterministic! What happens when threads added?
• Destination contention very limited.
• User/System boundary?
Source Destination
Time
Send Pdest, local VA, len
Send-rdy req
Tag check
(1) Initiate send
(2) Address translation on Psrc
(4) Send-ready request
(6) Reply transaction
Wait
Recv Psrc, local VA, len
Recv-rdy reply
Data-xfer req
(5) Remote check for posted receive (assume success)
(7) Bulk data transferSource VA Dest VA or ID
(3) Local/remote check
Processor Action?
3/29/2010 cs252-S10, Lecture 16 28
Asynch. Message Passing: Optimistic
• More powerful programming model
• Wildcard receive => non-deterministic
• Storage required within msg layer?
Source Destination
Time
Send (Pdest, local VA, len)
(1) Initiate send
(2) Address translation
(4) Send data
Recv Psrc, local VA, len
Data-xfer req
Tag match
Allocate buffer
(3) Local /remote check
(5) Remote check for posted receive; on fail, allocate data buffer
3/29/2010 cs252-S10, Lecture 16 29
Asynch. Msg Passing: Conservative
• Where is the buffering?
• Contention control? Receiver initiated protocol?
• Short message optimizations
Source Destination
Time
Send Pdest, local VA, len
Send-rdy req
Tag check
(1) Initiate send
(2) Address translation on Pdest
(4) Send-ready request
(6) Receive-ready request
Return and compute
Recv Psrc, local VA, len
Recv-rdy req
Data-xfer reply
(3) Local /remote check
(5) Remote check for posted receive (assume fail); record send-ready
(7) Bulk data replySource VA Dest VA or ID
3/29/2010 cs252-S10, Lecture 16 30
Features of Msg Passing Abstraction• Source knows send data address, dest. knows receive
data address– after handshake they both know both
• Arbitrary storage “outside the local address spaces”– may post many sends before any receives– non-blocking asynchronous sends reduces the requirement
to an arbitrary number of descriptors» fine print says these are limited too
• Optimistically, can be 1-phase transaction– Compare to 2-phase for shared address space– Need some sort of flow control
» Credit scheme?
• More conservative: 3-phase transaction– includes a request / response
• Essential point: combined synchronization and communication in a single package!
3/29/2010 cs252-S10, Lecture 16 31
Discussion of Active Messages paper
• Thorsten von Eicken, David E. Culler, Seth Copen Goldstein, Laus Erik Schauser:
– “Active messages: a mechanism for integrated communication and computation”
• Essential idea?– Fast message primitive
– Handlers must be non-blocking!
– Head of message contains pointer to code to run on destination node
• Could be compiled from Split-C into TAM runtime
• Much better balance of network and computation on existing hardware!
3/29/2010 cs252-S10, Lecture 16 32
Active Messages
• User-level analog of network transaction– transfer data packet and invoke handler to extract it from the network and
integrate with on-going computation
• Request/Reply
• Event notification: interrupts, polling, events?
• May also perform memory-to-memory transfer
Request
handler
handler
Reply
3/29/2010 cs252-S10, Lecture 16 33
Common Challenges• Input buffer overflow
– N-1 queue over-commitment => must slow sources
• Options:– reserve space per source (credit)
» when available for reuse? • Ack or Higher level
– Refuse input when full» backpressure in reliable network
» tree saturation
» deadlock free
» what happens to traffic not bound for congested dest?
– Reserve ack back channel
– drop packets
– Utilize higher-level semantics of programming model
3/29/2010 cs252-S10, Lecture 16 34
Spectrum of Designs• None: Physical bit stream
– blind, physical DMA nCUBE, iPSC, . . .
• User/System– User-level port CM-5, *T, Alewife,
RAW
– User-level handler J-Machine, Monsoon, . . .
• Remote virtual address– Processing, translation Paragon, Meiko CS-2
• Global physical address– Proc + Memory controller RP3, BBN, T3D
• Cache-to-cache– Cache controller Dash, Alewife, KSR,
FlashIncreasing HW Support, Specialization, Intrusiveness, Performance (???)
3/29/2010 cs252-S10, Lecture 16 35
Net Transactions: Physical DMA
• DMA controlled by regs, generates interrupts
• Physical => OS initiates transfers
• Send-side– construct system “envelope” around user data in kernel area
• Receive– receive into system buffer, since no interpretation in user space
PMemory
Cmd
DestData
Addr
Length
Rdy
PMemory
DMAchannels
Status,interrupt
Addr
Length
Rdy
sender auth
dest addr
3/29/2010 cs252-S10, Lecture 16 36
nCUBE Network Interface
• independent DMA channel per link direction– leave input buffers always open
– segmented messages
• routing interprets envelope– dimension-order routing on hypercube
– bit-serial with 36 bit cut-through
Processor
Switch
Input ports
Output ports
Memory
Addr AddrLength
Addr Addr AddrLength
AddrLength
DMAchannels
Memorybus
Os 16 ins 260 cy13 us
Or 18 200 cy15 us
- includes interrupt
3/29/2010 cs252-S10, Lecture 16 37
Conventional LAN NI
NIC Controller
DMAaddr
len
trncv
TX
RX
Addr LenStatusNext
Addr LenStatusNext
Addr LenStatusNext
Addr LenStatusNext
Addr LenStatusNext
Addr LenStatusNext
Data
Host Memory NIC
IO Busmem bus
Proc
• Costs: Marshalling, OS calls, interrupts
3/29/2010 cs252-S10, Lecture 16 38
User Level Ports
• initiate transaction at user level
• deliver to user without OS intervention
• network port in user space– May use virtual memory to map physical I/O to user mode
• User/system flag in envelope– protection check, translation, routing, media access in src CA
– user/sys check in dest CA, interrupt on system
PMem
DestData
User/system
PMemStatus,interrupt
Virtual address space
Status
Net outputport
Net inputport
Program counter
Registers
Processor
3/29/2010 cs252-S10, Lecture 16 39
Example: CM-5
• Input and output FIFO for each network
• 2 data networks
• tag per message– index NI mapping
table
• context switching?
• Alewife integrated NI on chip
• *T and iWARP also
Diagnostics network
Control network
Data network
Processingpartition
Processingpartition
Controlprocessors
I/O partition
PM PM
SPARC
MBUS
DRAMctrl
DRAM DRAM DRAM DRAM
DRAMctrl
Vectorunit DRAM
ctrlDRAM
ctrl
Vectorunit
FPU Datanetworks
Controlnetwork
$ctrl
$SRAM
NI
Os 50 cy 1.5 us
Or 53 cy 1.6 us
interrupt 10us
3/29/2010 cs252-S10, Lecture 16 40
RAW processor: Systolic Computation
• Very fast support for systolic processing– Streaming from one processor to another
» Simple moves into network ports and out of network ports
– Static router programmed at same time as processors
• Also included dynamic network for unpredictable computations (and things like cache misses)
3/29/2010 cs252-S10, Lecture 16 41
User Level Handlers
• Hardware support to vector to address specified in message
– On arrival, hardware fetches handler address and starts execution
• Active Messages: two options– Computation in background threads
» Handler never blocks: it integrates message into computation– Computation in handlers (Message Driven Processing)
» Handler does work, may need to send messages or block
U ser /sy s te m
PM e m
D e stD ata A d dress
PM e m
3/29/2010 cs252-S10, Lecture 16 42
J-Machine
• Each node a small mdg driven processor
• HW support to queue msgs and dispatch to msg handler task
3/29/2010 cs252-S10, Lecture 16 43
Alewife Messaging• Send message
– write words to special network interface registers
– Execute atomic launch instruction
• Receive– Generate interrupt/launch user-level
thread context
– Examine message by reading from special network interface registers
– Execute dispose message
– Exit atomic section
3/29/2010 cs252-S10, Lecture 16 44
Sharing of Network Interface• What if user in middle of constructing message and
must context switch???– Need Atomic Send operation!
» Message either completely in network or not at all» Can save/restore user’s work if necessary (think about single
set of network interface registers– J-Machine mistake: after start sending message must let
sender finish» Flits start entering network with first SEND instruction» Only a SENDE instruction constructs tail of message
• Receive Atomicity– If want to allow user-level interrupts or polling, must give
user control over network reception» Closer user is to network, easier it is for him/her to screw it
up: Refuse to empty network, etc» However, must allow atomicity: way for good user to select
when their message handlers get interrupted– Polling: ultimate receive atomicity – never interrupted
» Fine as long as user keeps absorbing messages
3/29/2010 cs252-S10, Lecture 16 45
The Fetch Deadlock Problem• Even if a node cannot issue a request, it must sink
network transactions!– Incoming transaction may be request generate a
response.
– Closed system (finite buffering)
• Deadlock occurs even if network deadlock free!
NETWORKNETWORK
3/29/2010 cs252-S10, Lecture 16 46
Solutions to Fetch Deadlock?• logically independent request/reply networks
– physical networks
– virtual channels with separate input/output queues
• bound requests and reserve input buffer space– K(P-1) requests + K responses per node
– service discipline to avoid fetch deadlock?
• NACK on input buffer full– NACK delivery?
• Alewife Solution:– Dynamically increase buffer space to memory when
necessary
– Argument: this is an uncommon case, so use software to fix
3/29/2010 cs252-S10, Lecture 16 47
Example Queue Topology: Alewife• Message-Passing and
Shared-Memory both need messages
– Thus, can provide both!
• When deadlock detected, start storing messages to memory (out of hardware)
– Remove deadlock by increasing available queue space
• When network starts flowing again, relaunch queued messages
– They take loopback path to be handled by local hardware
3/29/2010 cs252-S10, Lecture 16 48
Summary #1• Routing Algorithms restrict the set of routes within
the topology– simple mechanism selects turn at each hop
– arithmetic, selection, lookup
• Virtual Channels – Adds complexity to router
– Can be used for performance
– Can be used for deadlock avoidance
• Deadlock-free if channel dependence graph is acyclic
– limit turns to eliminate dependences
– add separate channel resources to break dependences
– combination of topology, algorithm, and switch design
• Deterministic vs adaptive routing
3/29/2010 cs252-S10, Lecture 16 49
Summary #2• Many different Message-Passing styles
– Global Address space: 2-way
– Optimistic message passing: 1-way
– Conservative transfer: 3-way
• “Fetch Deadlock”– RequestResponse introduces cycle through network
– Fix with: » 2 networks
» dynamic increase in buffer space
• Network Interfaces– User-level access
– DMA
– Atomicity