CS250 VLSI Systems Designcs250/fa20/files/lec02-history.pdfLecture 02, History CS250, UC Berkeley Fall ‘20 At Berkeley (1) 1980-1988: VLSI course continues to be taught by Professors

CS250, UC Berkeley Fall ‘20Lecture 02, History

CS250VLSISystemsDesign

Fall2020

JohnWawrzynek

with

AryaReais-Parsi


WhyisitCS250andnotEE250?

2

‣ Weanswerthatwithacoursehistory(withafewembeddedlessons).

Warning: What follows is principally from memory. I’ve done my best to be accurate, but some errors or misinterpretations might exist.

Starts in 1958 with the invention of the Integrated Circuit independently by Robert Noyce (co-founder of Fairchild Semiconductor Corporation) and Jack Kilby (engineer at Texas Instruments).

Jack Kilby, Texas Instruments

Bob Noyce, Fairchild


ICDesigninthe70’sandearly80’s

The Intel 4004 microprocessor, which was introduced in 1971. The 4004 contained 2300 transistors and performed 60,000

calculations per second. Courtesy: Intel.

Introducedtohelpsellmemory

chips!

FedericoFaggin,TedHoff,

StanMazor

‣ Movefrom“LSI”to“VLSI”

‣ Circuitdesign,layout,andprocessingtightlylinked.

‣ Logicdesignandlayoutwas“random”

‣ Chipdesignwasthedomainofindustry(Fairchild,Intel,TexasInstruments,…).ThesewereICprocessingcompanies.Thosewhocontrolledthephysicscontrolledthecreativeagenda!

3


"Listentothetechnology;findoutwhatit'stellingyou."

MeanwhileatCaltech…‣ CarverMeadwasdesigningandbuilding

prototypeICs(withhelpfromhisfriendsatIntel)

‣ Hisbackgroundwasinphysicalelectronics(inventedseveralsemiconductordevicessuchastheGaAsMESFET)butwasdeeplyinterestedintheinteractionofphysicalimplementationandthehigherleveldesignofelectronicsystems:

4


CSAtCaltech‣ IvanSutherlandbecamefoundingheadofthecomputersciencedivisionatin

1974(afterleavingE&S)

‣ HeandMeadteameduptogetthedivisionoffthegroundmakingICdesign(IntegratedSystems)akeycomponentoftheresearchandteaching.

‣ Mytake:

‣ ThesetwobelievedthatICdesignwasattheheartofcomputersciencebecauseCSwaslargelyaboutinventingandbuildingcomputingdevices.

‣ Thefutureofcomputingwasintegratedcircuits:

‣ Veryflexible,“boundless”growthpotential(GordonMoorehadpredictedanexponentialgrowcurvewithnoendinsight!)

‣ Closeto“purethought”withfewconstraintsand“nastyrealities”

‣ ThepotentialofVLSIwasnotgoingtobereachedwiththestatusquoinindustry.

‣ Workedtogetheroverthenext10yearstoestablishthefaculty,industrialties,curriculum,researchprojectswithsiliconstructuresasakeycomponent.

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Pushingforward(1)‣ Therealityofintegratedcircuits:

‣ Wiresareexpensive(area,delay,power),transistorsarecheap.

‣ Pre-ICs,theoppositewastrue.

‣ Therefore,planthecommunicationandthelayout

‣ Exploitlocality,thinkaboutthe“geometry”oftheproblemfromthebeginning.Choosealgorithms/designsaccordingly.

‣ Algorithms/designsrepresentedascommunicationgraphsinalargenumberofdimensions,notagoodidea.

6


PushingForward(2)‣ Traditionally,ICdesignhadbeenstratified:

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Algorithm /

architecture

Micro-

architecture

Circuit

design Layout

‣ PutICdesignexpertiseintothehandsofthosebestqualifiedtotakeadvantageofitspotential:

‣ Thosewithintimateknowledgeofcomputationandalgorithms:computerscientists!

‣ Emergenceofthe“tallthindesigner”.Spansalllevelsofthedesignandimplementationstack.

‣ Wouldleadtomoresuccessfulinnovationandhighlyoptimizeddesigns.


PushingForward(3)‣ Howtoenablesystemarchitects:

‣ Managingthecomplexitywasthekeychallenge.Manipulatingmultiplelevelsofdesigncomplexitywasdifficultandprojectedtogetmuchworselookingforward(rememberMoore’sLaw).

‣ ProvidinguniversalaccesstoICfabrication.

‣ Solutions:

1. Ideasfromsoftware

2. Newdesignrepresentations

3. Computeraideddesigntools

4. Silicon“foundries”5. Education

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Allinter-linked


IdeasfromSoftware (helpmanagecomplexity)

‣ “StructuredProgramming”wasgettingpopular(Dijstra,el.al.)

‣ Nogotostatements

‣ Blockorganization.

‣ Useofhierarchy,abstraction(sub-routines).

‣ “StructuredDesign”forICs:

‣ Exploitregularityandsymmetry

‣ Useandreusecommonsub-blocks(flip-flops,gates,arithmetic,etc.)

‣ Representdesignshierarchically

9


DesignRepresentations(1)‣ Previously,togeneratethemaskinformationforfabrication,the

designedneededintimateknowledgeofthemanufacturingprocess.Evenoncethisknowledgewasdistilledtoasetof“GeometricDesignRules”,thissetofruleswasvoluminouswithmanyspecialcases.

‣ Meadandassociatescomeupwithamuchsimplifiedsetofdesignrules(singlepagedescription).Asortof“API”orabstractionoftheprocess(back-endprocessingcouldautomaticallyconvertthisinformationintomasks).

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‣ Sufficientlysmallsetthatdesignerscouldmemorize.

‣ Sufficientlyabstracttoallowprocessengineerstoshrinktheprocessandpreserveexistinglayouts.

‣ Processresolutionbecomesa“parameter”,λ.


ScalableCMOSDesignRules‣ Createdwiththe

transitionfromnMOStoCMOS(amuchnicertechnology),around1985.

‣ Littlechangedovertheyears.

11


DesignRepresentations(2)‣ CaltechIntermediateForm(CIF)

‣ Capturelayoutinformation,neededtogeneratemasksandprocess.

‣ ASCIItextfilewithgeometricprimitivesandhierarchicaldefinitions.

‣ Simpleandhumanreadable.

‣ Easytogenerateandparse.

‣ Commonsub-blockscouldbereusedfromonedesigntothenext(outputpaddrivers,etc.)

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A sample CIF "wire" statement. The statement is: W25 100 200 100 100 200 200 300 200;


DesignRepresentations(3)‣ Previously,designedwererepresentedbyhand

drawings.Thenmaskswheremadebytransferringdrawingstorubylith.

‣ BaselayerofheavytransparentdimensionallystableMylar.Athinfilmofdeepredcellophane-likematerialcoversthebaselayer.Patternsformedbycutting(oftenbyhand)thetransparentcovering.

13

‣ Usinganelectronicformat(CIF)meant:

‣ Layoutseasilystoredandtransmitted

‣ Writtentotapeandtransferredtomanufacturer(tapeout).

‣ Transmittedoverthenetwork(newideabackthen).

‣ Softwarecouldautomaticallycheckforlayouterrors.

‣ Generatedfromaprogram-hugeidea.


DesignRepresentations(3)‣ “Simplified”approachextended

upward.

‣ “Sticks”diagramsforlayout:

‣ Simultaneouslycapturescircuittopologyandgeometry.

‣ Backendtool“fleshesout”realgeometryandcompactsaccordingtogeometricdesignrules.

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‣ Forfunctionalcircuitdescriptions,transistorsas“switches”.

‣ SimpleRC-basedand“tau”timingmodels(laterleadto“logicaleffort”)

‣ Standardsimplecircuitsforcommonfunctions.Previously,designershadmanytricks,andmanyalternativecircuits.


ComputerAidedDesign(1)‣ Severaladvancesleadtothedevelopmentofinteractive

toolsforgeneratinglayout:

‣ Computerbasedlayoutrepresentation(CIF).

‣ Advancesincomputergraphics(thankstoIvanSutherlandandfriends)anddisplaydevices.

‣ Personal“workstation”(XeroxAlto-ChuckThacker).“Backroom”computersdidn’thavethenecessarybandwidthtothedisplay.

‣ ICARUS(firstsuchsystem?)

‣ Berkeleyversion-MAGIC

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Early’80’sDesignMethodologyandFlow

‣ Schematic+Full-CustomLayout

SPICEforcriticalpath,

switch-levelsimulationforoverallfunctionality,

handlayout,

nopoweranalysis,

layoutverifiedwithLVSandGDRC

Transistor Schematics

switch simulator

hand layout

layout vs.

schematic

CIF file

geometric design rule

checker

SPICE

Specification

16


ComputerAidedDesign(2)‣ ForsometimeafterCIFwasinvented.Layoutwasgeneratedby

hand,thentypedinasaCIFfilewithatexteditor.

‣ Layoutcompilers

‣ SoonsomedesignersstartedembeddingCIFprimitivesinconventionalprogramminglanguages:LISP,pascal,fortran,(later)C.

‣ Thisallowsdesignerstowriteprogramsthatgeneratedlayout.Suchprogramscouldbeparameterized:

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define GENERATE_RAM(rows, columns) { for I from 1 to rows for J from 1 to columns (GENERATE_BITCELL)} GENERATE_RAM(128, 32);

‣ Leadtocircuit/layoutgenerationfromhigherleveldescriptions:

‣ Bristle-blocks(first“siliconcompiler”,DaveJohanssen).Generatedprocessorarchitectures(datapaths)fromhighlevelspecification

‣ Eventually,CadenceandSynopsysformedoutofBerkeley

‣ LeveragedHDLtolayout


SIliconFoundries‣ Separatethedesignerfromthefabricator:Modeledaftertheprinting

industry.(Veryfewauthorsactuallyownandrunprintingpresses!)

‣ Simplestandardgeometricdesignruleswherethekey:theseformthe“contract”betweenthedesignerandmanufacturer.

‣ Designersendsthelayout(inCIFformat),foundrymanufacturesthechipandsendback.Designerpromisesnottoviolatethedesignrules.Foundrypromisestoaccuratelyfollowlayout.

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‣ Ascalablemodelfortheindustry:

‣ ICfabisexpensiveandcomplex

‣ Amortizestheexpenseovermanydesigners(batchprocessingwithdeepqueueshelp).

‣ Designersandcompaniesnotheldbackbyneedtodevelopandmaintainlargeexpensivefactories.

‣ “fabless”semiconductorcompanies-lotsoftheseandveryfewfoundries.


Multi-projectChips&“Shuttle”Runs‣ Siliconprocessingisoptimizedforhigh-volume.

‣ Largeminimumorder,highfixed-price(overhead),lowperunitcost.

‣ Whiledesigningandcharacterizingnewdesigns(prototyping),whatisneededislow-volumelow-costproduction.

‣ Multi-projectchipsallowedmultipledesignerstoshareonesetofmasks,onesetofwafers.Bringscostofproductiondowntolevelsappropriateforprototyperuns.

‣ ShuttleRunsareregularlyscheduledfabricationofmulti-projectwafers.

‣ Thesedaysmulti-projectwafersinsteadofchips.

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“MOSimplementationService”‣ Formanyyears(1980-1996)fabricationwasavailable(mostlyin

theformofMPCs)toUSuniversitiesforfree(paidbyNSFandDARPA.

‣ Interestingly,DARPAoriginallysawthisasausefulapplicationoftheARPAnet(latertobeknownastheInternet).ARPAhadinvestedtoputthisnetworktogether-world-wide-webandemailhadn’thappenedyet,soARPAwaslookingforawaytojustifytheirinvestment.

‣ TheMOSISprojectatUSC/ISIcollecteddesignsfromaroundthecountry.DesignswereFTPedtoMOSIS,thenbrokeredtheirmanufacturingwithsiliconfoundries.

‣ BecomeTHEwaytodoprojectsinclasses(likeCS250)andresearch.

‣ Over50,000designsprototypedforuniversities,industry,andgovernmentagencies.

‣ Continuestoday,subsidizedbypayingcustomers,withsparespaceofferedforfreetouniversities.

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Education‣ Thenewsimpledesignrepresentationsmadeiteasytoteachandlearn

(evenforcomputerscientists-remembertheoriginaltargets)

‣ TextbookbyCarverMeadandLynnConway,1980.

21

‣ Presentedelegantcleartreatmentofphysics,processing,circuits,anddesignmethodologyfornMOSchips.

‣ Continuedasthestandardtext,evenlongafterCMOSsupplantednMOS(sadlyneverrevised).

‣ Keytoitssuccesswasthelargedesignexample

‣ OM2designbecomesthemodelforallmicroprocessordesigns.


OM2

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SpreadingtheWord‣ Limitedprinting(ofchapters1-3)wereusedascoursenotes

in1977byMeadatCaltechandCarloSequinatUCBerkeley.

‣ Chapters1-51978byIvanSutherlandandAmrMohsenatCaltech,byBobSproullatCMU,Frohman-BentchkowskyatHebrewUniversity,Jerusalem,andbyFredRosenbergeratWashingtonUniversity.

‣ Prepublicationofentirebook,infallof1978,incoursesatCaltechandUCBerkeley,andbyKentSmithattheUniversityofUtah,andbyLynnConway,whilevisitingMIT.

‣ Withinafewyears,thisseminaltextwasadoptedforchipdesigncoursesatover100universitiesthroughouttheworld.

23


AtBerkeley(1)1980-1988:VLSIcoursecontinuestobetaught

byProfessorsSequin,Patterson,&Katz.

~1985:StudentsinadvancedversionofthecoursewithSequinandPatterson,designfirsttwoRISCprocessors.Workingcloselywithdesigners,Prof.OusterhoutdevelopsMAGICICdesigntools.

Late80’s.Pattersonreturnstoarchitecturefocus,KatztoOS/Networking,Sequintographics.

1988:BerkeleyhiresCaltechgrad(studentofC.Mead)totakeoverVLSIcourse.Offerscoursemanytimesthroughthe90’s.

24


AtBerkeley(2)‣ Throughthe1990’s…

‣ EE141,EE241developtocovermuchofthesamematerial(processing,CMOSdevices,circuits,sub-systems)however,250continuestobeapracticalhands-on,experience-with-real-CAD-tools,design-a-real-chipcourse.

‣ VLSIchipsstarttogrowincomplexitypastpracticallimitsofuniversity1-semesterprojects(super-scalarOOO,etc.).

‣ Late90’s.Academicteaching/design/researchfocusshiftstoFPGAs.Muchshorter“turn-around”time.FPGAsgetlargeandpracticalforwiderangeofapplications.

‣ 1999:LasttimeCS250offeredasadesigncourse.

‣ Spring2007:Offeredasasurveycourse,nodesignproject.

‣ 2009:Asanovic,WawrzynekreviveCS250asadesigncourse.FocusonVerilogsynthesisanddesignspaceexploration.Strongconnectionstoresearchagenda.

‣ Alothaschangedin30years!Manynewchallenges/opportunitiesontheway!

‣ WhatoftheMead/Sutherlandmethodologyandideasfrom1980still 25


Sowhathaschangedin30years?

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CS250, UC Berkeley Fall ‘20Lecture 02, History 27

CS250, UC Berkeley Fall ‘20Lecture 02, History44

MooreMoore’’s Law - 2005s Law - 2005

40044004

8080808080868086

8028680286386386™™ Processor Processor

486486™™ Processor ProcessorPentiumPentium® ® ProcessorProcessor

PentiumPentium®® II ProcessorII Processor

PentiumPentium®® III Processor III Processor

PentiumPentium®® 4 Processor 4 ProcessorItaniumItanium™™ ProcessorProcessor

TransistorsTransistors

Per DiePer Die

101088

101077

101066

101055

101044

101033

101022

101011

101000

101099

10101010

80088008

ItaniumItanium™™ 22 ProcessorProcessor

1K1K

4K4K

64K64K

256K256K

1M1M

16M16M4M4M

64M64M

256M256M512M512M

1G1G 2G2G

128M128M

16K16K

1965 Data (Moore)1965 Data (Moore)

MicroprocessorMicroprocessor

MemoryMemory

19601960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

Source: IntelSource: Intel

Moore’sLawforCPUsandDRAMs

From: “Facing the Hot Chips Challenge Again”, Bill Holt, Intel, presented at Hot Chips 17, 2005. 28


88

Processed Wafer CostProcessed Wafer Cost

Wafer size conversions offset trend ofWafer size conversions offset trend of

increasing wafer processing costincreasing wafer processing costSource: IntelSource: Intel

Secondarydriver:Wafersize

From: “Facing the Hot Chips Challenge Again”, Bill Holt, Intel,

presented at Hot Chips 17, 2005.

29


Processingadvances

4µm 45nm

30


ICTechnologyStuff(1)‣ Featuresize:

then:~4µm now:~.015µm

‣ Interconnect:

then:2layersnow:~10layers, then:aluminum now:copper

‣ Transistors:

then:planarMOSFET now:FinFET

‣ LayoutandGDRs:

Essentiallyunchanged.Morecomplex.Densityandareafillrules.

‣ Circuits:

then:clockedstaticCMOSnow:same(lotsofcrazystuffinbetween)

MostCMOScircuitsandlayoutsdesignedin1980wouldworkiffabricatedontoday’sICprocess.

31


ICTechnologyStuff(2)‣ Transistors:

then:nearperfectswitchnow:leaky,fast/leakyorslow/not

‣ Powerconsumption:

then:dynamic(switching)energynow:approaching50%staticleakage(backtothefuture-nMOShassimilarproblem)

‣ Newimproveddevices:FinFETs

‣ ChipInput/Output

then:parameterpadsnow:usuallyareapads

‣ LithographicMaskCosts:

then:few$know:$M(fulldie,65)

32


ICTechnologyStuff(3)‣ Devicereliability:

then:devicesnearlyneverfailfuture (<65nm): highsoftandharderrorrates

‣ Processvariationsacrossdie,die-to-die:

‣ Statisticalvariationsinprocessing(wirewidths/resitivity,transistordimensions/strengths,dopinginconsistencies)becomeapparentatsmallergeometries.

‣ Somecircuitsfast,othersslow.Somehigh-power,somelow.

‣ Yieldonleadingedgeprocessesdroppingdramatically

‣ IBMquotesyieldsof10–20%onCellprocessor

33


DesignStuff‣ Chipfunctionality:

then:limitedbyareanow:oftenlimitedbyenergydissipation

‣ Designcost:

now:designcostsin$50Mrangeforfull-diecustomdesigns(highpercentageinverification)

‣ ImplementationAlternatives:morealternativesthattradeup-frontdesigncostsforperunitcosts.

‣ FPGAcompeteaggressivelywithcustomsilicon

then:mostcustomdesignsimplementedatsiliconlevel

now:manymorecustomdesignsimplementedwithFPGAs

‣ Standarddesignabstraction:

then:transistorscircuitsnow:RTLinHDLs,standard“cores”andstandardcells(higherproductivity,somewhatlessarea/energyefficient)-successofCADcompanies

34


ImplementationAlternatives

What are the important metrics of comparison?

Full-custom: Allcircuits/transistorslayoutsoptimizedforapplication.

Standard-cell: Arraysofsmallfunctionblocks(gates,FFs)automaticallyplacedandrouted.

Gate-array(structuredASIC):

Partiallyprefabricatedwaferscustomizedwithmetallayersorvias.

FPGA: Prefabricatedchipscustomizedwithloadablelatchesorfuses.

Microprocessor: Instructionsetinterpretercustomizedthroughsoftware.

DomainSpecificProcessor:

Specialinstructionsetinterpreters(ex:DSP,NP,GPU,TPU).

By“ASIC”,mostpeoplemean“Standard-cell”basedimplementation.


TheImportantDistinction• “Instruction” Binding Time

‣ Whendowedecidewhatoperationneedstobeperformed?

• General Principles Earlier the decision is bound, the less area, delay/energy

required for the implementation. Later the decision is bound, the more flexible the device.

A.DeHon


Full-Custom‣ Circuitstylesandtransistorsarecustomsized

anddrawntooptimizedie,size,power,performance.

‣ HighNRE(non-recurringengineering)costs

‣ Time-consuminganderrorpronelayout

‣ Optimizingforsmalldiecanresultinlowperunitcosts,extreme-low-power,orextreme-high-performance.

‣ Commonforanalogdesign.

‣ Requiresfullsetofcustommasks.

‣ HighNREusuallyrestrictsusetohigh-volumeapplications/marketsorhighly-constrainedandcostinsensitivemarkets.


Standard-Cell*‣ Basedaroundasetofpre-designed(andverified)cells

‣ Ex:NANDs,NORs,Flip-Flops,counters,buffers,…

‣ Eachcellcomescompletewith:‣ layout(perhapsfordifferenttechnologynodesandprocesses),‣ Simulation,delay,&powermodels.

‣ Chiplayoutisautomatic,reducingNREs(usuallynohand-layout).

‣ Requiresfullsetofmasks-nothingprefabricated.

‣ Non-optimaluseofareaandpower,leadingtohigherperdiecoststhanfull-custom.

‣ Commonlyusedwithotherpredesignedblocks(largememories,I/Oblocks,etc.)


Semi-CustomChipImplementations‣ Ex:standardpracticeinmicroprocessorswasthatdata-pathswerefull-

customandcontrol(instructiondecode,pipelinecontrol)instandard-cells.Nowallgeneratedwithstandardcells.

Control(“random”)logicdifficultto“regularize”.Relativelysmall

percentageofdiearea/power.Permitslatebindingofdesignchanges.


GateArray‣ Storeprefabricatedwafersof“active”&gatelayers&local

interconnect,comprising,primarily,rowsoftransistors.Customizeasneededwith“back-end”metalprocessing(contactcuts,metalwires).Coulduseadifferentfactory.

‣ CADsoftwareunderstandshowtomakegates,butalsopossibletocustomizeatthetransistorcircuitlevel.


GateArray• Shifts large portion of design and mask NRE to vendor. • Shorter design and processing times, reduced time to market. • Highly structured layout with fixed size transistors leads to large

sub-circuits (ex: Flip-flops) and higher per die costs. • Memory arrays are particularly inefficient, so often prefabricated,

also:

Sea-of-gates,structuredASIC,master-slice.


FieldProgrammableGateArrays

‣ Fuses,EPROM,orStaticRAMcellsareusedtostorethe“configuration”.

‣ Here,itdeterminesfunctionimplementedbyLUT,selectionofFlip-flop,andinterconnectionpoints.

‣ ManyFPGAsincludespecialcircuitstoaccelerateaddercarry-chainandmanyspecialcores:RAMs,MAC,Enet,PCI,SERDES,...

n Two-dimensional array of simple logic- and interconnection-blocks.

n Typical architecture: LUTs implement any function of n-inputs (n=3 in this case).

n Optional Flip-flop with each LUT.


System-on-chip(SOC)

‣ Pre-verifiedblockdesigns,standardbusinterfaces(oradapters)easeintegration-lowerNREs,shortenTTM.

• Bringstogether:standardcellblocks,customanalogblocks,processorcores,memoryblocks,embeddedFPGAs,…

• Standardizedon-chipbuses(orhierarchicalinterconnect)permit“easy”integrationofmanyblocks.– Ex:AMBA,Sonics,…

• “IPBlock”businessmodel:Hard-orsoft-coresavailablefromthirdpartydesigners.

• ARM,inc.istheshiningexample.Hard-and“synthesizable”RISCprocessors.

• ARMandothercompaniesprovide,Ethernet,USBcontrollers,analogfunctions,memoryblocks,…

Qualcomm Snapdragon


ModernASICMethodologyandFlow‣ RTLSynthesisBased

HDLspecifiesdesignascombinationallogic+stateelements

Cellinstantiationsneededforblocksnotinferredbysynthesis(typicallyRAM)

EventsimulationverifiesRTL

“Formal”verificationcompareslogicalstructureofgatenetlisttoRTL

Place&routegenerateslayout

Timingandpowercheckedstaticallyordynamically

LayoutverifiedwithLVSandGDRC

RTL (Verilog/VHDL) + cell instantiations

logic synthesis

event simulator

cell place & route

GDS timing/power

analysis

“formal” verification

Specification

gate netlist

GDRC, LVS, other checks 44


CourseFormat(1)

‣ Focusondesignandimplementationofreconfigurablefabric(s).

‣ Entireclassworksonalargeadvancedchipdesignormultiplechipdesigns.

‣ Detailsonhowwewilldivideuptobeworkedoutlater

45


CourseStructure‣ CheckWebsiteCalendar/Infofordetails

‣ Lectureson

‣ Architecture(FPGAandreconfigurablefabrics)

‣ CADtools(OpenLane)

‣ CMOSDesignBasics

‣ “Lab”exercisesforpracticewithtoolflow

‣ “private”projectmeetings:‣ Groupsmembersplusteachingstaff

‣ Studentpresentations:‣ projectproposals

‣ statusreports

‣ finalreport 46


MoreClassInfo‣ WawrzynekOfficehours:Tuesday11am-12(butnottoday)

‣ samezoomlinkasclass

‣ Piazza:makesuretoregisterASAP,http://piazza.com/berkeley/fall2020/cs250

‣ gradingwillbebasedon:

‣ classparticipation

‣ projects

47

http://piazza.com/berkeley/fall2020/cs250


EndofLecture2

48

Documents

CS250 VLSI Systems Designcs250/fa20/files/lec02-history.pdfLecture 02, History CS250, UC Berkeley Fall ‘20 At Berkeley (1) 1980-1988: VLSI course continues to be taught by Professors