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Input and Output
Chapter 14
Bus A
nd Bus A
rchitectures
CS250 -- Part IV
1D
r.Rajesh Subram
anyan, 2005
Topics
•Introduction
•D
efinition of a Bus
•Processors, I/O
devices, and Buses
•Proprietary and Standardized B
uses
•Shared B
uses and an Access Protocol
•M
ultiple Buses
•A
Parallel, Passive Mechanism
•Physical C
onnections
•B
us Interface
CS250 -- Part IV
2D
r.Rajesh Subram
anyan, 2005
Topics
•A
ddress, Control, and D
ata Lines
•T
he Fetch-store Paradigm
•Fetch-store over
aB
us
•T
he Width of a B
us
•M
ultiplexing
•B
us Width and Size of D
ata Items
•B
us Address Space
•Potential E
rrors
•A
ddress Configuration and Sockets
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Topics
•M
anyB
uses or One B
us
•U
sing Fetch-store with D
evices
•A
nE
xample of D
evice Control U
sing Fetch-store
•O
peration of an Interface
•A
symm
etric Assignm
ents
•U
nified Mem
ory and Device A
ddressing
•H
oles in the Address Space
•A
ddress Map
•Program
Interface to a Bus
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Topics
•B
ridging Betw
een Two B
uses
•M
ain and Auxillary B
uses
•C
onsequence for Programm
ers
•Sum
mary
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Introduction
•T
his chapter discusses
−external connections betw
een processor and mem
orysystem
−bus, a fundam
ental architectural feature in all computer
systems
−m
otivation for a bus, basic operations
−a
comm
on bus shared between m
emory and I/O
−how
bus defines address space
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Definition of a B
us
•D
igital comm
unication mechanism
that allows tw
oor
more
functional units to transfer control signals or data
•E
xamples
−m
emory bus connects processor and m
emory
−I/O
bus interconnects processor with I/O
devices
CS250 -- Part IV
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r.Rajesh Subram
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Definition of a B
us
bus
pro
cessor
device
Illustration of a bus used to connect a processor an externaldevice. B
uses are used for most external connections.
Abus is the digital com
munication m
echanism used w
ithin acom
puter system to interconnect functional units. A
computer
contains one or more
buses that interconnect the processors,m
emories and external I/O
devices.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Proprietary and Standardized B
uses
•Proprietary buses
−design is ow
ned by private company
via patents etc
•Standardized buses
−specifications available to any
company
−allow
s multi-vendor devices to w
ork together
−specifications, hardw
are, voltage, timing of signals,
encoding, all must be strictly adhered to.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Shared Buses and A
ccess Protocol
•Processor can connect to a set of I/O
devices, or multiple
processors can connect to single shared bus
•A
ccess protocol
−how
attached device determines if bus is available or busy
−how
devices taketurn in using the bus
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Multiple B
uses
•C
omputer System
s may contain several buses, exam
ples
−m
emory bus, I/O
bus
−special buses connecting coprocessors
•R
easons: flexibility,convenience
•Internal buses: not visible to com
puter owner
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Parallel P
assive Mechanism
•B
us usually do not contain electronic components
•D
evice connecting to bus contain circuits for comm
unication
•B
us are likeparallel w
ires to which devices attach
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Physical C
onnections
•B
us can consists of
−tiny
wires etched in silicon on a single chip
−cable containing m
ultiple wires
−set of parallel m
etal wires on circuit board
•C
omputer’s
main circuit board is also called the m
other board
−sockets on m
other board connects to the bus.
−sockets allow
devices to be plugged in or removed
CS250 -- Part IV
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Bus Interfaces
•B
us interface or bus controller
−additional circuit that attaches to bus and follow
s the busprotocol
−device interface have m
etal fingers that touch m
etalcontacts of socket
CS250 -- Part IV
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Bus Interfaces
circuit b
oard
(device in
terface)
mother board
socket
Side viewof
am
other board illustrating howa
printed circuitboard can plug directly into the socket of a bus. M
etal strips onthe circuit board press against m
etal contacts in the socket.
CS250 -- Part IV
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anyan, 2005
Logical Structure
ofa
Bus
•B
us wires are called lines.
•Functions of different lines are
−control line: control of bus
−address line: specifi
cation of address information
−data lines: transfer of data
•L
ines need not be divided equally,control need fewer lines
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Fetch-Store
Paradigm
Like
am
emory system
, a bus employs the fetch-store
paradigm;
all control or data transfer operations areperform
ed as eitherfetch
ora
store
•A
ll lines usefetch or store operation
•C
ontrol lines are used
−to
ensure only one pair of devices comm
unicate overthe
busatany tim
e
−allow
two com
municating devices to interact
•A
ddress lines are used to pass address
•D
ata lines are used to transfer a value
CS250 -- Part IV
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r.Rajesh Subram
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Fetch-Store
Paradigm
Fetch1. U
sethe control lines to obtain access to the
bus2. P
lacean address on the address lines
3. Use
the control lines to request a fetchoperation
4. Test the control lines to wait for the operation
to complete
5. Read
the value from the data lines
6. Setthe control lines to allow
another device touse the bus
Sto
re1. Use
control lines to obtain access to the bus2. P
lacean address on the address lines
CS250 -- Part IV
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3. Place
avalue on the data lines
4. Use
the control lines to specify a storeoperation
4. Test the control lines to wait for the operation
to complete
5. Setthe control lines to allow
another device touse the bus
The steps taken to perform
a fetch or store operation overa
bus,and the group of lines used in each step.
CS250 -- Part IV
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r.Rajesh Subram
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Width of a B
us
•If
abus can transfer k bits of data at a tim
e (overk
lines),w
idth of bus is k.
•E
xample 32 bit bus
•H
ow w
ide should bus be?
−increasing w
idth increases throughput
−greater w
idth, translates tom
ore space and electroniccom
ponents
−architect chooses com
promise betw
een space, cost andperform
ance
CS250 -- Part IV
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r.Rajesh Subram
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Multiplexing
•H
elps in reducing the number of lines in a bus
•D
ata multiplexing
−device divides data into blocks that are exactly as large asthe bus is w
ide.
−device uses bus repeatedly,by
sending one block at atim
e.
CS250 -- Part IV
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r.Rajesh Subram
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Address and D
ata Multiplexing
•U
se same lines for address and data
•E
xample of address and data m
ultiplexing
−send address on the line and receive data on the sam
e linelater
−store operation: send address fi
rst followed by data
•C
omm
only,few lines are kept for control and m
ost lines foreither address/data
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Advantages and D
isadvantages of Multiplexing
•A
dvantages
−architect can design a bus w
ith fewer lines
−higher overall perform
ance for the same num
ber of lines
•D
isadvantages
−m
ore time m
ay be needed, example store takes tw
obus
cycles
−m
ore sophisticated bus protocol, therefore more com
plexhardw
are
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Bus W
idth and Size of Data and A
ddress
•C
hoose a single size for all of the following
−bus w
idth
−register size
−data value
−address
Address and data values are
multiplexed over a bus. To
optimize perform
ance of the hardware, an
arc hitectchooses a single size for both data item
s and addresses.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Bus A
ddress Space
•E
xample of a bus: m
emory bus
−a
devices connected to bus via interface (here processorand m
emories)
−the interface im
plements bus protocol, handles all
comm
unication
−the interface uses control lines to gain access to the bus,sends addresses or data values as instructed by device(processor or m
emory)
−the interface alone understands bus details
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Bus A
ddress Space
bus
pro
cessor
mem
or y
1m
emo
r yN
...
businterface
Physical interconnections of a processor and mem
ory using am
emory bus. A
controller circuit in each device handles thedetails of bus access.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Bus A
ddress Space
•Program
ming interface for bus has only fetch and store
operations
•E
xample
−data to be m
ovedfrom
mem
ory to register,processorissues fetch to bus interface
−data to be m
ovedto
mem
ory,processor issues store to theinterface
•Single address space is divided am
ong different mem
ories.A
ll mem
ory controllers receive the fetch or store, but onlyone m
emory w
hose address ranges matches the request
address responds.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Bus A
ddress Space
Although an interface receives all requests that pass across the
bus, the interface only responds to requests that contain anaddress for w
hichthe interface has been configured
CS250 -- Part IV
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r.Rajesh Subram
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Potential E
rrors
•A
ddress conflict
−B
us error occurs when interfaces are m
isconfigured so
theyrespond to the sam
e address.
•Precaution: bus protocols include test for address conflicts
•U
nassigned address
−the processor attem
pts to access an address that has notbeen confi
gured into anyinterface
•Precaution: bus protocols use tim
eout mechanism
. If noresponse is received
within a certain tim
e, the processorhardw
are generates bus error
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Address C
onfiguration and Sockets
•M
emory is not installed to cover
all addresses, infact mem
orybus
are designed to accomm
odate mem
ory expansion
•U
se of special sockets helps inavoiding m
emory
configuration problem
s
•A
nother alternative isto
allowM
MU
to configure socket
addresses when the com
puter boots
To avoid mem
ory configuration problems, architects can
place mem
ory on small circuit boards that each
plug into asocketon
the mother board. A
n owner can install m
emory
without configuring the hardw
arebecause each
socketisconfigured w
ith the rangeofaddresses to w
hichthe m
emory
should respond
CS250 -- Part IV
29D
r.Rajesh Subram
anyan, 2005
Many B
uses or One B
us?
•H
igh performance com
puters have many
buses, eachoptim
ized for a specific purpose
•A
dvantage of single bus
−L
ower cost and m
ore generality
•D
isadvantage
−m
ay not be optimal for given
purpose
−m
ay become the bottleneck
CS250 -- Part IV
30D
r.Rajesh Subram
anyan, 2005
Using F
etch-Storew
ith Devices
•B
us only provides transfer mechanism
, not what the bit
means.
•D
evice can interpret bits uniquely.Exam
ple bits may m
eancontrol operation, or a data transfer .
CS250 -- Part IV
31D
r.Rajesh Subram
anyan, 2005
Using F
etch-Storew
ith Devices
•Tu
rn th
e disp
layo
n•
Turn
the d
isplay
off
•S
et the d
isplay
brig
htn
ess•
Turn
the i statu
s ligh
t on
or o
ff
An exam
ple of functionality provided by an imaginary hardw
aredevice. B
efore the unit can be attached to a bus, control functionsm
ust be implem
ented using the fetch-store paradigm.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Using F
etch-Storew
ith Devices
Ad
dress
Op
eration
Mean
ing
100 − 103sto
re n
on
zerod
ata value tu
rns th
e disp
layo
n,
and
a zerod
ata value tu
rns th
e disp
layo
ff
100 − 103fetch
return
s zeroif
disp
layis
curren
tlyo
ff,an
d n
on
zeroif
disp
layis
curren
tlyo
n
104 − 107sto
re C
han
ge
brig
htn
ess. Lo
w-o
rder fo
ur b
its of
the d
ata value sp
ecify brig
htn
ess value
from
zero(d
im) th
rou
gh
sixteen (b
righ
t)
108 − 111sto
re T
he
low
ord
er sixteen b
its eachco
ntro
l astatu
s ligh
t, wh
ere zerosets th
e corresp
on
din
glig
ht o
ff and
on
e sets it on
.
Exam
ple assignment of addresses, operations, and m
eanings forthe device control functions listed in the above fi
gure.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Operation of an Interface
•For a device address is just a set of bits
•Test is done to see if bits m
atch
•If
theym
atch, interface enables circuits to a do fetch or store
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Unified M
emory and D
evice Addressing
•A
single bus provides access to both mem
ory and I/O devices
•I/O
devices have tobe
giv enunique addresses to avoid
conflict
•M
emory obviously needs large address space, but isn’ta
single address sufficient to identify a device?
−w
hy sixteen bytes for each device?
−because, each address for device can be m
apped to adifferent function.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Unified M
emory and D
evice Addressing
bus
pro
cessor
mem
or y
1m
emo
r y2
device
1d
evice2
Illustration of a computer architecture that uses a single bus.
Both m
emories and devices attach to the bus.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Unified M
emory and D
evice Addressing
Device
Ad
dress R
ang
eM
emo
r y1
0x000000 th
rou
gh
0x0
fffffM
emo
r y2
0x100000 th
rou
gh
0x1
fffffD
evice 10x200000
thro
ug
h
0x20000bD
evice 20x20000c
thro
ug
h
0x200017
One possible assignm
ent of bus addresses for the set of devicesshow
n in the previous figure.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Holes in the A
ddress Space
•H
oles: if there are gaps in the addresses
•Typically low
est addresses reserved for mem
ory,and higherfor I/O
devices
In a typical computer,the part of the address space available
to devices is sparsely populated - only a small percentage of
the addresses areused
CS250 -- Part IV
38D
r.Rajesh Subram
anyan, 2005
Program
Interface to a Bus
Aprocessor that has m
ultiple buses provides special instructionsto access each; a processor that has one bus interprets norm
alm
emory operations as referencing locations in the bus address
space.
CS250 -- Part IV
39D
r.Rajesh Subram
anyan, 2005
Bridging B
etween T
wo B
uses
•B
ridge interconnects two
orm
ore buses
•U
nique range of addresses assigned for each bus
•B
ridge translates address for request or reply receivedon
onebus
and forwards it to the other bus
•B
ridge makes a set of address on one bus appear in the
address space of another: this is called mapping
CS250 -- Part IV
40D
r.Rajesh Subram
anyan, 2005
Main and A
uxillary buses
•To
the processor bridge is transparent, i.e. it doesn’tneed toknow
about the auxillary bus.
•H
owev er, softw
are must understand about the m
apping
Abridge
isa
hardware
device that interconnects two buses
and maps addresses betw
een them. B
ridging allows a
computer to have one or m
oreauxillary buses that are
accessed through the computer’s
main bus.
CS250 -- Part IV
41D
r.Rajesh Subram
anyan, 2005
Main and A
uxillary buses
available
for
mem
or y
0 available
for
mem
or y
available
for
devices
add
ress space
of m
ain bu
s
0
add
ress space
of au
xiliarybu
s
notm
appedm
apping thebridge
supplies
Mapping that a bridge can provide betw
een the address space ofan auxillary bus and the address space of a m
ain bus. Only som
ebus
addresses need to be mapped.
CS250 -- Part IV
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r.Rajesh Subram
anyan, 2005
Summ
ary
•B
us is a fundamental m
echanisms to interconnect m
emory,
I/O devices, and processors w
ithin a computer system
.
•E
ach bus defines a protocol that devices use to access bus.
Fetch-store paradigm form
s the basis of the protocols
•C
ontrol, data and address information is passed over
the bus,w
ires may be shared for better perform
ance
•B
us defines address space w
hich may have holes.
•M
ultiple buses may be connected by bridge w
ith addressesbeing m
apped between the m
ultiple buses or main and
auxillary bus.
CS250 -- Part IV
43D
r.Rajesh Subram
anyan, 2005
CS250 -- Part IV
44D
r.Rajesh Subram
anyan, 2005
