cs2071 new notes 2

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CMageshKumar_AP_AIHT CS2071_Computer Architecture

ANAND INSTITUTE OF HIGHER TECHNOLOGY Chennai-603 103 DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING

CS2071 COMPUTER ARCHITECTURE

Faculty Name: C.MAGESHKUMAR Class: IV EIE A&B Semester: VII

UNIT II – ARITHMETIC/LOGIC UNIT

CONTENT Page no.

I. Number Representation 2

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1. Positional Number Systems 2

2. Digit Sets and Encodings 2

3. Number-Radix Conversion 2

4. Signed Integers 2

5. Fixed-Point Numbers 2

6. Floating-Point Numbers 2

II. Design of Adders and design of simple ALUs 3

7. Simple Adders 3

8. Carry Propagation Networks 3

Design of ripple carry adder 3

Design of Carry Lookahead Adders 4

9. Counting and Incrementation 5

10. Design of Fast Adders 5

11. Logic and Shift Operations 5

12. Multifunction ALUs 6

III. Design of Multipliers and Dividers 8

13. Shift-Add Multiplication 8

Design of combinational multiplier 8

14. Booth’s algorithm 8

Combinational multiplier with carry save addition 8

15. Hardware Multipliers 8

16. Programmed Multiplication 9

17. Shift-Subtract Division 9

18. Hardware Dividers 10

19. Programmed Division 11

IV. Design of Floating-Point Arithmetic 11

20. Rounding Modes 11

21. Special Values and Exceptions 11

22. Floating-Point Addition 11

23. Other Floating-Point Operations 13

24. Floating-Point Instructions 14

REFER FROM PAGE NO. 31 TO 77 IN XEROX)

(REFER PAGE NO. 157 - 233 IN TEXT BOOK B.PARHAMI)

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I. NUMBER REPRESENTATION REFER FROM PAGE NO. 31 TO 51 IN XEROX)

1. Positional Number Systems

Fixed-radix positional representation with k digits

Value of a number: x = (xk–1xk–2 . . . x1x0)r = S xi r i

For example:

Representation Range and Overflow

Overflow regions in finite number representation systems. For unsigned representations, max – = 0.

Conventional and unconventional digit sets

Decimal digits in [0, 9]; 4-bit BCD, 8-bit ASCII

Hexadecimal, or hex: digits 0-9 & a-f

Conventional ternary digit set in [0, 2]

Conventional digit set for radix r is [0, r – 1]

Symmetric ternary digit set in [–1, 1]

Conventional binary digit set in [0, 1]

Redundant digit set [0, 2], encoded in 2 bits

( 0 2 1 1 0 )two and ( 1 0 1 0 2 )two represent 22

2. Digit Sets and Encodings

3. Number-Radix Conversion

4. Signed Integers

We dealt with representing the natural numbers

Signed or directed whole numbers = integers

{ . . . , -3, -2, -1, 0, 1, 2, 3, . . . }

Signed-magnitude representation

+27 in 8-bit signed-magnitude binary code 0 0011011

–27 in 8-bit signed-magnitude binary code 1 0011011

–27 in 2-digit decimal code with BCD digits 1 0010 0111

Biased representation

Represent the interval of numbers [-N, P] by the unsigned

interval [0, P + N]; i.e., by adding N to every number

5. Fixed-Point Numbers

6. Floating-Point Numbers

max

Finite set of representable numbers

Overflow region max Overflow region

Numbers larger than max

Numbers smaller than max

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II. DESIGN OF ADDERS AND DESIGN OF SIMPLE ALUS

7. Simple Adders, serial adder, parallel adder REFER FROM PAGE NO. 52 TO 56 IN XEROX)

8. Carry Propagation Networks REFER FROM PAGE NO. 52 TO 57 IN XEROX)

Ripple-carry binary adder with 32-bit inputs and output

Design of Ripple Carry Adders:

Arithmetic operations like addition, subtraction, multiplication, division are basic operations to be

implemented in digital computers using basic gates like AND, OR, NOR, NAND etc. Among all the arithmetic

operations if we can implement addition then it is easy to perform multiplication (by repeated addition), subtraction

(by negating one operand) or division (repeated subtraction).

Half Adders can be used to add two one bit binary numbers. It is also possible to create a logical circuit using

multiple full adders to add N-bit binary numbers.Each full adder inputs a Cin, which is the Cout of the previous

adder. This kind of adder is a Ripple Carry Adder, since each carry bit "ripples" to the next full adder. The first (and

only the first) full adder may be replaced by a half adder.The block diagram of 4-bit Ripple Carry Adder is shown here

below -

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is

relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate

delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic.In a

32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 31 * 2(for carry

propagation) + 3(for sum) = 65 gate delays.

Design Issues:

The corresponding boolean expressions are given here to construct a ripple carry adder. In the half adder circuit the

sum and carry bits are defined as

sum = A ⊕ B

carry = AB

In the full adder circuit the the Sum and Carry outpur is defined by inputs A, B and Carryin as

Sum=ABC + ABC + ABC + ABC

Carry=ABC + ABC + ABC + ABC

Having these we could design the circuit. But, we first check to see if there are any logically equivalent statements that

would lead to a more structured equivalent circuit.

With a little algebraic manipulation,

Sum= ABC + ABC + ABC + ABC

= (AB + AB) C + (AB + AB) C = (A ⊕ B) C + (A ⊕ B) C =A ⊕ B ⊕ C

Carry= ABC + ABC + ABC + ABC = AB + (AB + AB) C = AB + (A ⊕ B) C

x

s

y

c c

x

s

y

c

x

s

y

c

c out c in

0 0

0

c 0

1 1

1

1 2

31

31

31

31

FA FA FA 32

. . .

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Carry Propagation Networks -- The main part of an adder is the carry network. The rest is just a set of gates

to produce the g and p signals and the sum bits.

DESIGN OF CARRY LOOKAHEAD ADDERS :

To reduce the computation time, there are faster ways to add two binary numbers by using carry lookahead

adders. They work by creating two signals P and G known to be Carry Propagator and Carry Generator. The carry

propagator is propagated to the next level whereas the carry generator is used to generate the output carry ,

regardless of input carry. The block diagram of a 4-bit Carry Lookahead Adder is shown here below -

The number of gate levels for the carry propagation can be found from the circuit of full adder. The signal from input

carry Cin to output carry Cout requires an AND gate and an OR gate, which constitutes two gate levels. So if there are

four full adders in the parallel adder, the output carry C5 would have 2 X 4 = 8 gate levels from C1 to C5. For an n-bit

parallel adderr, there are 2n gate levels to propagate through.

Design Issues :

The corresponding boolean expressions are given here to construct a carry lookahead adder. In the carry-lookahead

circuit we ned to generate the two signals carry propagator(P) and carry generator(G),

Pi = Ai ⊕ Bi

Gi = Ai · Bi

The output sum and carry can be expressed as

Sumi = Pi ⊕ Ci and Ci+1 = Gi + ( Pi · Ci)

Having these we could design the circuit. We can now write the Boolean function for the carry output of each stage

and substitute for each Ci its value from the previous equations:

C1 = G0 + P0 · C0

C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0

C3 = G2 + P2 · C2 = G2 P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0

C4 = G3 + P3 · C3 = G3 P3 · G2 P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 · P0 · C0

Carry network

. . . . . .

x i

y i

g p

s

i i

i

c i

c i+1

c k1

c k

c k2

c 1

c 0

g p 1 1 g p

0 0

g p k2 k2

g p i+1 i+1

g p k1 k1

c 0

. . . . . .

0 0 0 1 1 0 1 1

annihilated or killed propagated generated (impossible)

Carry is: g i

p i

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Third Carry Speed-Up Method: Carry Select -- Allows doubling of adder width with a single-mux additional

delay

9. Counting and Incrementation (Refer page no. 183 - 185 in text book B.Parhami)

DESIGN OF REGISTERS AND COUNTERS :

In a sequential circuit the present output is determined by both the present input and the past output. In order

to receive the past output some kind of memory element can be used. The memory element commonly used in the

sequential circuits are time-delay devices. The block diagram of the sequential circuit-

A circuit with flip-flops is considered a sequential circuit even in the absence of combinational logic. Circuits that

include flip-flops are usually classified by the function they perform. Two such circuits are registers and counters:

1. Register is a group of flip-flops. Its basic function is to hold information within a digital system so as to make it

available to the logic units during the computing process.

2. Counter is essentially a register that goes through a predetermined sequence of states.

There are various different kind of Flip-Flops. Some of the common flip-flops are: R-S Flip-Flop, D Flip-

Flop, J-K Flip-Flop, T Flip-Flop. The block diagram of different flip-flops are shown here -

1. RS flipflop If R is high then reset state occurs and when S=1 set state.the both cannot be high simultaneouly.

this input combination is avoided.

2. JK flipflop If J and K are both low then no change occurs. If J and K are both high at the clock edge then the

output will toggle from one state to the other

3. D flipflop The D flip-flop tracks the input, making transitions with match those of the input D.

4. Tflipflop The T or "toggle" flip-flop changes its output on each clock edge,

D Q

C

_ Q

D

c out

c in

Adder

Update

/ k

k /

a (Increment

amount)

Count register k

/

1

0

Data in

k /

k /

IncrInit

c out

c in

Adder

Version 1 of sum bits 1

0

x [a, b]

c out

c in

Adder

Version 0 of sum bits

y [a, b]

s [a, b]

c a

0 1

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Design Issues:

The four different types of flip-flops are supplied here. One can easily build any register or counter using those flip-

flop and different logic gates. But the automatic clock input is under development, so to build any registers or counters

user can use the manual clock or Dip Switch which toggles on double click over the component.

10. Design of Fast Adders

11. LOGIC AND SHIFT OPERATIONS ((Refer page no. 188 to 190 in text book B.Parhami))

ARITHMETIC SHIFTS

Purpose: Multiplication and division by powers of 2

sra $t0,$s1,2 # $t0 ($s1) right-shifted by 2

srav $t0,$s1,$s0 # $t0 ($s1) right-shifted by ($s0)

12. MULTIFUNCTION ALUS

Multiplexer

0 1 2 31 32 33 62 63

5

6

Right’Left

Shift amount 0, x[31, 1]

x[31, 0]

00, x[30, 2]

00...0, x[31]

x[31, 0]

x[30, 0], 0

x[1, 0], 00...0

x[0], 00...0

. . . . . .

32

32 32 32 32 32 32 32 32

6-bit code specifying shift direction & amount

Right-shifted values

Left-shifted values

1 1

1 1

0 0 0

fn

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0

31 25 20 15 0

ALU instruction

Unused Source register

op rs rt

R

rd sh 10 5

Destination register

Shift amount

sra = 3

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

31 25 20 15 0

ALU instruction

Amount register

Source register

op rs rt

R

rd sh 10 5

fn


Unused srav = 7

7


AddSub

x y

y

x

Adder

c 32

c 0

k /

Shifter

Logic unit

s

Logic function

Amount

5

2

Constant amount

Variable amount

5

5

ConstVar

0

1

0

1

2

3

Function class

2

Shift function

5 LSBs Shifted y

32

32

32

2

c 31

32-input NOR

Ovfl Zero

32

32

MSB

ALU

y

x

s

Shorthand symbol for ALU

Ovfl

Zero

Func

Control

0 or 1

AND 00 OR 01

XOR 10 NOR 11

00 Shift 01 Set less 10 Arithmetic 11 Logic

00 No shift 01 Logical left 10 Logical right 11 Arith right

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III. DESIGN OF MULTIPLIERS AND DIVIDERS (Refer page no. 197 - 214 in text book B.Parhami)

13. SHIFT-ADD MULTIPLICATION for examples refer page no. 199 in text book b.parhami

DESIGN OF COMBINATIONAL MULTIPLIER:

Combinational Multipliers do multiplication of two unsigned binary numbers. Each bit of the multiplier is

multiplied against the multiplicand, the product is aligned according to the position of the bit within the multiplier, and

the resulting products are then summed to form the final result. Main advantage of binary multiplication is that the

generation of intermediate products is simple: if the multiplier bit is a 1, the product is an appropriately shifted copy of

the multiplicand; if the multiplier bit is a 0, the product is simply 0.

The design of a combinational multiplier to multiply two 4-bit binary number is illustrated below: If two n-bit

numbers are multiplied then the output will be less than or equals to 2n bits.

14. BOOTH’S ALGORITHM REFER PAGE NO. 61 – 70 IN XEROX

14.1 COMBINATIONAL MULTIPLIER WITH CARRY SAVE ADDITION PAGE NO. 70 IN XEROX

15. HARDWARE MULTIPLIERS ALSO REFER PAGE NO. 59 IN XEROX

Multiplicand

Partial products bit-matrix

x y

z

y x 2 0 0

y x 2 1 1

y x 2 2 2

y x 2 3 3

Multiplier

Product

Multiplier y

Mux

Adder out c

0 1

Doublewidth partial product z

Multiplicand x

Shift

Shift

(j)

j y

Add’Sub

Enable

Select

in c

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TREE MULTIPLIERS

ARRAY MULTIPLIER:

16. PROGRAMMED MULTIPLICATION

MINIMIPS INSTRUCTIONS RELATED TO MULTIPLICATION

mult $s0,$s1 # set Hi,Lo to ($s0)($s1); signed

multu $s2,$s3 # set Hi,Lo to ($s2)($s3); unsigned

mfhi $t0 # set $t0 to (Hi)

mflo $t1 # set $t1 to (Lo)

17. SHIFT-SUBTRACT DIVISION. for examples refer page no. 208 in text book B.PARHAMI

3

2

1

0

4 5 6 7

0

1

2

3

2 1 0 x x x

y

y

y

z

y

3 x

0

0

0

0

0

0

0

0

0

0

0

z

z

z

z z z z

HA FA FA

MA MA MA MA

MA MA MA MA

MA MA MA MA

MA MA MA MA

FA

0

Our original dot-notation representing multiplication

Straightened dots to depict array multiplier to the left

2 1

2

y

2

x 2

2

1

0

3

0

Subtracted bit-matrix

Divisor x Dividend z

s Remainder

Quotient y

y x 3

y x 2

y x

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SIGNED DIVISION:

Method 1 (indirect): strip operand signs, divide, set result signs

Dividend Divisor Quotient Remainder

z = 5 x = 3 y = 1 s = 2

z = 5 x = –3 y = –1 s = 2

z = –5 x = 3 y = –1 s = –2

z = –5 x = –3 y = 1 s = –2

Method 2 (direct 2’s complement): develop quotient with digits –1 and 1, chosen based on signs, convert to digits 0

and 1

Restoring division: perform trial subtraction, choose 0 for q digit if partial remainder negative

Nonrestoring division: if sign of partial remainder is correct, then subtract (choose 1 for q digit) else add (choose –1)

18. HARDWARE DIVIDERS

ARRAY DIVIDERS:

Load

Quotient y

Mux

Adder

0 1

Partial remainder z (initially z)

Divisor x

Shift

Shift

(j)

k– j

y

1

Enable

Select

Quotient

digit selector

1

out

c

in

c

Trial difference (Always subtract)

2 1 0 x x x

1 y

2 y

3 y 3 z

0 y

3 x

2 z

1 z

0 z

4 z 5 z 6 z 7 z

MS MS MS MS

MS MS MS MS

MS MS MS MS

MS MS MS MS

Our original dot-notation for division

Straightened dots to depict an array divider 2 1 0 s s s 3 s

0

0

0

0

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19. PROGRAMMED DIVISION

MiniMIPS instructions related to division

div $s0,$s1 # Lo = quotient, Hi = remainder

divu $s2,$s3 # unsigned version of division

mfhi $t0 # set $t0 to (Hi)

mflo $t1 # set $t1 to (Lo)

IV. DESIGN OF FLOATING-POINT ARITHMETIC

20. ROUNDING MODES

21. SPECIAL VALUES AND EXCEPTIONS

Zeros, infinities, and NaNs (not a number)

± 0 Biased exponent = 0, significand = 0 (no hidden 1)

± ∞ Biased exponent = 255 (short) or 2047 (long), significand = 0

NaN

Arithmetic operations with special operands

(+0) + (+0) = (+0) – (–0) = +0; (+0) * (+5) = +0

(+0) / (–5) = –0; (+∞) + (+∞) = +∞

x – (+∞) = –∞; (+∞) * x = ±∞, depending on the sign of x

x / (+∞) = ±0, depending on the sign of x

√(+∞) = +∞

22. FLOATING-POINT ADDITION

Distribution of floating-point numbers on the real line.

Denser Denser Sparser Sparser

Negative numbers

FLP FLP 0 +

–

Overflow region

Overflow region

Underflow regions

Positive numbers

Underflow example

Overflow example

Midway example

Typical example

min max min max + + – – – +

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HARDWARE FOR FLOATING-POINT ADDITION

Normalize & round

Add

Align significands

Possible swap & complement

Unpack

Control & sign logic

Pack

Input 1

Output

Significands Exponents Signs

Significand Exponent Sign

Sub

Mux

Input 2

AddSub

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23. Other Floating-Point Operations

Floating-point multiplication

(2e1

s1) (2e2

s2) = 2e1+ e2

(s1 s2)

Product of significands in [1, 4)

If product is in [2, 4), halve to normalize (increment exponent)

Floating-point division

(2e1

s1) / (2e2

s2) = 2e1– e2

(s1 / s2)

Ratio of significands in (1/2, 2)

If ratio is in (1/2, 1), double to normalize (decrement exponent)

Floating-point square-rooting

(2es)

1/2 = 2

e/2(s)

1/2 when e is even

= 2(e–1)2

(2s)1/2

when e is odd

Normalization not needed

Hardware for Floating-Point Multiplication and Division

Normalize & round

Multiply or divide

Unpack

Control & sign logic

MulDiv

Pack

Input 1

Output

Significands Exponents Signs

Significand Exponent Sign

Input 2

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24. FLOATING-POINT INSTRUCTIONS

FLOATING-POINT ARITHMETIC INSTRUCTIONS FOR MINIMIPS:

add.s $f0,$f8,$f10 # set $f0 to ($f8) +fp ($f10)

sub.d $f0,$f8,$f10 # set $f0 to ($f8) –fp ($f10)

mul.d $f0,$f8,$f10 # set $f0 to ($f8) fp ($f10)

div.s $f0,$f8,$f10 # set $f0 to ($f8) /fp ($f10)

neg.s $f0,$f8 # set $f0 to –($f8)

MINIMIPS INSTRUCTIONS FOR NUMBER FORMAT CONVERSION:

cvt.s.w $f0,$f8 # set $f0 to single(integer $f8)

cvt.d.w $f0,$f8 # set $f0 to double(integer $f8)

cvt.d.s $f0,$f8 # set $f0 to double($f8)

cvt.s.d $f0,$f8 # set $f0 to single($f8,$f9)

cvt.w.s $f0,$f8 # set $f0 to integer($f8)

cvt.w.d $f0,$f8 # set $f0 to integer($f8,$f9)

MINIMIPS INSTRUCTIONS FOR FLOATING-POINT LOAD, STORE, AND MOVE:

lwc1 $f8,40($s3) # load mem[40+($s3)] into $f8

swc1 $f8,A($s3) # store ($f8) into mem[A+($s3)]

mov.s $f0,$f8 # load $f0 with ($f8)

mov.d $f0,$f8 # load $f0,$f1 with ($f8,$f9)

mfc1 $t0,$f12 # load $t0 with ($f12)

mtc1 $f8,$t4 # load $f8 with ($t4)

MINIMIPS INSTRUCTIONS FOR FLOATING-POINT LOAD, STORE, AND MOVE:

bc1t L # branch on fp flag true

bc1f L # branch on fp flag false

c.eq.* $f0,$f8 # if ($f0)=($f8), set flag to “true”

c.lt.* $f0,$f8 # if ($f0)<($f8), set flag to “true”

c.le.* $f0,$f8 # if ($f0)($f8), set flag to “true”

x x x x 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0

31 25 20 15 0

Floating-point instruction

s = 0 d = 1

Source register 2

op ex ft

F

fs fd 10 5

fn


add.* = 0 sub.* = 1 mul.* = 2 div.* = 3 neg.* = 7

Source register 1

1 0 0 x x x x 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

31 25 20 15 0


*.w = 0

w.s = 0

w.d = 1

*.* = 1

Unused

op ex ft

F

fs fd 10 5

fn


To format: s = 32 d = 33 w = 36

Source register

0 1 1 0 0 x 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

31 25 20 15 0


s = 0 d = 1

Unused

op ex ft

F

fs fd 10 5

fn


mov.* = 6

Source register

1 1 1 0 0 0 0 x 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 25 20 15 0


mfc1 = 0 mtc1 = 4

Unused

op rs rt

R

rd sh 10 5

fn


Source register

Unused

15


1 0 0 1 1 0 0 x 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 25 20 15 0


s = 0 d = 1

Source register 2

op ex ft

F

fs fd 10 5

fn

Unused c.eq.* = 50

c.lt.* = 60

c.le.* = 62

Source register 1

x

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0

31 25 20 15 0


true = 1 false = 0

bc1? = 8

Offset

op rs rt operand / offset

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