cs-instrset.ppt

8/19/2019 cs-instrset.ppt

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Chapters 10 and 11,

William Stallings

Computer Organization and Architecture7th Edition

Instruction Sets:

Characteristics and Functions Addressing odes


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What is an Instruction Set!

" #he complete collection o$ instructions that

are understood %& a C'(

"achine language: %inar& representationo$ operations and )addresses o$*

arguments

" Assem%l& language: mnemonic

representation $or humans, e+g+,

O' A,,C )meaning A -. O'),C**


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Elements o$ an Instruction

" Operation code )opcode* / o this: A, S(, ', I2, 3OA, S#O4

" Source operand re$erence

/ #o this: )address o$* argument o$ op, e+g+register, memor& location

" 4esult operand re$erence

/ 'ut the result here )as a%o5e*" 6et instruction re$erence )o$ten implicit*

/ When &ou ha5e done that, do this: 4


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Simple Instruction Format

)using t8o addresses*


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Instruction C&cle State iagram


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esign ecisions )1*

" Operation repertoire / 9o8 man& ops!

/ What can the& do!

/ 9o8 comple are the&!" ata t&pes )length o$ 8ords, integer

representation*

" Instruction $ormats / 3ength o$ op code $ield

/ 3ength and num%er o$ addresses )e+g+, implicit

addressing*


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esign ecisions )*

" 4egisters

/ 6um%er o$ C'( registers a5aila%le

/ Which operations can %e per$ormed on 8hich

registers! ;eneral purpose and speci$ic

registers

" Addressing modes )see later*

" 4ISC 5 CISC


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Instruction #&pes

" ata trans$er: registers, main memor&,

stac< or I=O

" ata processing: arithmetic, logical

" Control: s&stems control, trans$er o$

control


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ata #rans$er " Store, load, echange, mo5e, clear, set,

push, pop" Speci$ies: source and destination )memor&,

register, stac


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Input=Output

" a& %e speci$ic instructions, e+g+ I6'(#,

O(#'(#

" a& %e done using data mo5ement

instructions )memor& mapped I=O*

" a& %e done %& a separate controller

)A*: Start I=O, #est I=O


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Arithmetic

" Add, Su%tract, ultipl&, i5ide $or signed

integer ) $loating point and pac


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3ogical

" it8ise operations: A6, O4, 6O#, @O4,

#ES#, C', SE#

" Shi$ting and rotating $unctions, e+g+

/ logical right shi$t $or unpac


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S&stems Control

" 'ri5ileged instructions: accessing control

registers or process ta%le

" C'( needs to %e in speci$ic state

/ 4ing 0 on 0>D

/ ernel mode

"For operating s&stems use


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#rans$er o$ Control

" S


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ranch Instruction


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6ested 'rocedure Calls


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(se o$ Stac


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#&pes o$ Operand

" Addresses: immediate, direct, indirect,stac<

" 6um%ers: integer or $ied point )%inar&,

t8os complement*, $loating point )sign,signi$icand, eponent*, )pac


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'entium ata #&pes" Addressing is %& %it unit

" ;eneral data t&pes: %it &te, 1D %it 8ord,

> %it dou%le 8ord, D %it Huad 8ord

" Integer: signed %inar& using t8os

complement representation

" )(n*pac


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Instruction Formats

" 3a&out o$ %its in an instruction

" Includes opcode

" Includes )implicit or eplicit* operand)s*

" (suall& more than one instruction $ormatin an instruction set


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Instruction 3ength

" A$$ected %& and a$$ects: / emor& size

/ emor& organization . addressing

/ us structure, e+g+, 8idth

/ C'( compleit& / C'( speed

" #rade o$$ %et8een po8er$ul instructionrepertoire and sa5ing space


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Allocation o$ its

" 6um%er o$ addressing modes: implicit oradditional %its speci$&ing it

" 6um%er o$ operands

" 4egister )$aster, limited size and num%er,

>* 5ersus memor&" 6um%er o$ register sets, e+g+, data and

address )shorter addresses*

" Address range" Address granularit& )e+g+, %& %&te*


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6um%er o$ Addresses" ore addresses

/ ore comple )po8er$ul!* instructions / ore registers . inter.register operations are

Huic


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> addresses

Operation 4esult, Operand 1, Operand

/ 6ot common

/ 6eeds 5er& long 8ords to hold e5er&thing

S( ,A, -. A.

' #,,E # -. E

A #,#,C # -. #C

I2 ,,# -. :#


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addresses

One address dou%les as operand and result

/ 4educes length o$ instruction

/ 4eHuires some etra 8or


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1 addressImplicit second address, usuall& a register

)accumulator, AC*3OA AC -.

' E AC -. ACE

A C AC -. ACC

S#O4 -. AC

3OA A AC -. A

S( AC -. AC.

I2 AC -. AC:

S#O4 -. AC


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0 )zero* addresses

All addresses implicit, e+g+ A

/ (ses a stac


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Addressing odes

" Immediate

" irect

" Indirect

" 4egister

" 4egister Indirect

" isplacement )Indeed*

" Stac<


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Immediate Addressing

" Operand is part o$ instruction

" Operand J address $ield

" e+g+, A MN / Add N to contents o$ accumulator

/ N is operand" 6o memor& re$erence to $etch data

" Fast

" 3imited range


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irect Addressing

" Address $ield contains address o$ operand

" E$$ecti5e address )EA* J address $ield )A*

" e+g+, A A / Add contents o$ cell A to accumulator

/ 3oo< in memor& at address A $or operand" Single memor& re$erence to access data

" 6o additional calculations needed to 8or<

out e$$ecti5e address" 3imited address space )length o$ address$ield*


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irect Addressing iagram

Address AOpcode

Instruction

Memory

Operand


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Indirect Addressing )1*

" emor& cell pointed to %& address $ieldcontains the address o$ the operand

" EA J )A* / 3oo< in A, $ind e$$ecti5e address and loo<

there $or operand" E+g+ A )A*

/ Add content o$ cell pointed to %& content o$ Ato accumulator


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Indirect Addressing )*

" 3arge address space

" n 8here n J 8ord length

" a& %e nested, multile5el, cascaded / e+g+ EA J )))A***

" ultiple memor& accesses to $ind operand" 9ence slo8er


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Indirect Addressing iagram

Address AOpcode

Instruction

Memory

Operand

Pointer to operand


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4egister Addressing )1*

" Operand is held in register named inaddress $ield

" EA J 4

" 3imited num%er o$ registers

" 2er& small address $ield needed / Shorter instructions

/ Faster $etch


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4egister Addressing )*

" 6o memor& access

" 2er& $ast eecution

" 2er& limited address space

" ultiple registers helps per$ormance / 4eHuires good assem%l& programming or

compiler 8riting / see register renaming

" c$+ direct addressing


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4egister Addressing iagram

Register Address R Opcode

Instruction

Registers

Operand


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4egister Indirect Addressing

" C$+ indirect addressing

" EA J )4*

" Operand is in memor& cell pointed to %&contents o$ register 4

" 3arge address space )n*" One $e8er memor& access than indirect

addressing


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4egister Indirect Addressing iagram

Register Address R Opcode

Instruction

Memory

OperandPointer to Operand

Registers


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isplacement Addressing

" EA J A )4*

" Address $ield holds t8o 5alues / A J %ase 5alue

/ 4 J register that holds displacement

/ or 5ice 5ersa" See segmentation


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isplacement Addressing iagram

Register R Opcode

Instruction

Memory

OperandDisplacement

Registers

Address A

+


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4elati5e Addressing

" A 5ersion o$ displacement addressing

" 4 J 'rogram counter, 'C

" EA J A )'C*

" i+e+, get operand $rom A cells a8a& $rom

current location pointed to %& 'C" c$+ localit& o$ re$erence cache usage


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Indeed Addressing

" A J %ase

" 4 J displacement

" EA J A 4

" ;ood $or iteration, e+g+, accessing arra&s

/ EA J A 4 / 4

" Sometimes automated: autoindeing

)signalled %& one %it in instruction*


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Stac< Addressing

" Operand is )implicitl&* on top o$ stac<

" e+g+ / A 'op top t8o items $rom stac< and add

and push result on top


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'o8er'C Addressing odes" 3oad=store architecture )see net slide*:

/ isplacement and indirect indeed / EA J %ase displacement=inde

/ 8ith updating %ase %& computed address

" ranch address

/ A%solute

/ 4elati5e )see loops*: )'C* I

/ Indirect: $rom register

" Arithmetic / Operands in registers or part o$ instruction

/ For $loating point: register onl&

'o8er'C emor& Operand


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'o8er'C emor& Operand Addressing odes

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