CS 61C L6.2.2 Interrupts (1) K. Meinz, Summer 2004 © UCB CS61C : Machine Structures Lecture 6.2.2 Interrupts 2004-07-29 Kurt Meinz inst.eecs.berkeley.edu/~cs61c

CS 61C L6.2.2 Interrupts (1) K. Meinz, Summer 2004 © UCB

CS61C : Machine Structures

Lecture 6.2.2Interrupts

2004-07-29

Kurt Meinz

inst.eecs.berkeley.edu/~cs61c


Big Idea•How to choose between associativity, block size, replacement policy?

•Design against a performance model• Minimize: Average Memory Access Time

= Hit Time + Miss Penalty x Miss Rate

• influenced by technology & program behavior

• Note: Hit Time encompasses Hit Rate!!!

•Create the illusion of a memory that is large, cheap, and fast - on average


Example•Assume

• Hit Time = 1 cycle

• Miss rate = 5%

• Miss penalty = 20 cycles (on top of hit)

• Calculate AMAT…

•Avg mem access time = 1 + 0.05 x 20

= 1 + 1 cycles

= 2 cycles


Ways to reduce miss rate•Larger cache

• limited by cost and technology

• hit time of first level cache < cycle time

•More places in the cache to put each block of memory – associativity

• fully-associative- any block any line

• k-way set associated- k places for each block

- direct map: k=1


Improving Miss Penalty•When caches first became popular, Miss Penalty ~ 10 processor clock cycles

•Today 2400 MHz Processor (0.4 ns per clock cycle) and 80 ns to go to DRAM 200 processor clock cycles!

Proc $2

DR

AM

$

MEM

Solution: another cache between memory and the processor cache: Second Level (L2) Cache


Analyzing Multi-level cache hierarchy

Proc $2

DR

AM

$

L1 hit time

L1 Miss RateL1 Miss Penalty

Avg Mem Access Time = L1 Hit Time + L1 Miss Rate * L1 Miss Penalty

L1 Miss Penalty = AMATL2 = L2 Hit Time + L2 Miss Rate * L2 Miss Penalty

Avg Mem Access Time = L1 Hit Time + L1 Miss Rate * (L2 Hit Time + L2 Miss Rate * L2 Miss Penalty)

L2 hit time L2 Miss Rate

L2 Miss Penalty


Typical Scale•L1

• size: tens of KB• hit time: complete in one clock cycle

• miss rates: 1-5%

•L2:• size: hundreds of KB• hit time: few clock cycles

• miss rates: 10-20%

•L2 miss rate is fraction of L1 misses that also miss in L2

• why so high?


Example: with L2 cache•Assume

• L1 Hit Time = 1 cycle

• L1 Miss rate = 5%

• L2 Hit Time = 5 cycles

• L2 Miss rate = 15% (% L1 misses that miss)

• L2 Miss Penalty = 200 cycles

•L1 miss penalty = 5 + 0.15 * 200 = 35

•Avg mem access time = 1 + 0.05 x 35= 2.75 cycles


Example: without L2 cache•Assume

• L1 Hit Time = 1 cycle

• L1 Miss rate = 5%

• L1 Miss Penalty = 200 cycles

•Avg mem access time = 1 + 0.05 x 200= 11 cycles

•4x faster with L2 cache! (2.75 vs. 11)


Cache Summary

•Cache design choices:• size of cache: speed v. capacity• direct-mapped v. associative• for N-way set assoc: choice of N• block replacement policy• 2nd level cache?• Write through v. write back?

•Use performance model to pick between choices, depending on programs, technology, budget, ...


Outline•Exceptions

•Memory Mapped IO

•Exception Implementation


Recall : 5 components of any Computer

Processor (active)

Computer

Control(“brain”)

Datapath(“brawn”)

Memory(passive)

(where programs, data live whenrunning)

Devices

Input

Output

Keyboard, Mouse

Display, Printer

Disk,Network


Motivation for Input/Output• I/O is how humans interact with computers

• I/O gives computers long-term memory.

• I/O lets computers do amazing things:• Read pressure of synthetic hand and control synthetic arm and hand of fireman

• Control propellers, fins, communicate in BOB (Breathable Observable Bubble)

•Computer without I/O like a car without wheels; great technology, but won’t get you anywhere


I/O Device Examples and Speeds

• I/O Speed: bytes transferred per second(from mouse to Gigabit LAN: 100-million-to-1)

• Device Behavior Partner Data Rate (KBytes/s)

Keyboard Input Human 0.01Mouse Input Human 0.02Voice output Output Human 5.00Floppy disk Storage Machine 50.00Laser Printer Output Human 100.00Magnetic Disk Storage Machine 10,000.00Wireless Network I or O Machine 10,000.00Graphics Display Output Human 30,000.00Wired LAN Network I or O Machine 1,000,000.00


What do we need to make I/O work?

•A way to present them to user programs so they are useful

cmd reg.data reg.

Operating System

APIsFiles

Proc Mem

•A way to connect many types of devices to the Proc-Mem

PCI Bus

SCSI Bus

•A way to control these devices, respond to them, and transfer data


Instruction Set Architecture for I/O

•What must the processor do for I/O?• Input: reads a sequence of bytes • Output: writes a sequence of bytes

•Some processors have special input and output instructions

•Alternative model (used by MIPS):• Use loads for input, stores for output

• Called “Memory Mapped Input/Output”

• A portion of the address space dedicated to communication paths to Input or Output devices (no memory there)


Memory Mapped I/O•Certain addresses are not regular memory

• Instead, they correspond to registers in I/O devices

cntrl reg.data reg.

0

0xFFFFFFFF

0xFFFF0000

address


Processor-I/O Speed Mismatch

•1GHz microprocessor can execute 1 billion load or store instructions per second, or 4,000,000 KB/s data rate

• I/O devices data rates range from 0.01 KB/s to 1,000,000 KB/s

• Input: device may not be ready to send data as fast as the processor loads it

• Also, might be waiting for human to act

•Output: device not be ready to accept data as fast as processor stores it

•What to do?


Processor Checks Status before Acting•Path to device generally has 2 registers:

• Control Register, says it’s OK to read/write (I/O ready) [think of a flagman on a road]

• Data Register, contains data

•Processor reads from Control Register in loop, waiting for device to set Ready bit in Control reg (0 1) to say its OK

•Processor then loads from (input) or writes to (output) data register

• Load from or Store into Data Register Proc resets Ready bit (1 0) of Control Register


SPIM/Proj4 I/O Simulation•Simulate 1 I/O device: memory-mapped terminal (keyboard + display)• Read from keyboard (receiver); 2 device regs

• Writes to terminal (transmitter); 2 device regs

Received Byte

Receiver Data0xffff0004 Unused (00...00)

(IE)Receiver Control0xffff0000

Read

y(I.E

.)Unused (00...00)

TransmittedByte

Transmitter Control0xffff0008

Transmitter Data0xffff000c

Read

y(I.E

.)Unused (00...00)

Unused


SPIM I/O•Control register rightmost bit (0): Ready

• Receiver: Ready==1 means character in Data Register not yet been read; 1 0 when data is read from Data Reg

• Transmitter: Ready==1 means transmitter is ready to accept a new character;0 Transmitter still busy writing last char

- I.E. bit discussed later

•Data register rightmost byte has data• Receiver: last char from keyboard; rest = 0

• Transmitter: when write rightmost byte, writes char to display


I/O Example• Input: Read from keyboard into $v0

lui $t0, 0xffff #ffff0000Waitloop: lw $t1, 0($t0) #control

andi $t1,$t1,0x1beq $t1,$zero, Waitlooplw $v0, 4($t0) #data

•Output: Write to display from $a0

lui $t0, 0xffff #ffff0000Waitloop: lw $t1, 8($t0) #control

andi $t1,$t1,0x1beq $t1,$zero, Waitloopsw $a0, 12($t0) #data

• Processor waiting for I/O called “Polling”


Cost of Polling?•Assume for a processor with a 1GHz clock it takes 400 clock cycles for a polling operation (call polling routine, accessing the device, and returning). Determine % of processor time for polling

• Mouse: polled 30 times/sec so as not to miss user movement

• Floppy disk: transfers data in 2-Byte units and has a data rate of 50 KB/second. No data transfer can be missed.

• Hard disk: transfers data in 16-Byte chunks and can transfer at 16 MB/second. Again, no transfer can be missed.


% Processor time to poll [p. 677 in book]Mouse Polling, Clocks/sec

= 30 [polls/s] * 400 [clocks/poll] = 12K [clocks/s]

• % Processor for polling: 12*103 [clocks/s] / 1*109 [clocks/s] = 0.0012%

Polling mouse little impact on processor

Frequency of Polling Floppy = 50 [KB/s] / 2 [B/poll] = 25K [polls/s]

• Floppy Polling, Clocks/sec= 25K [polls/s] * 400 [clocks/poll] = 10M [clocks/s]

• % Processor for polling: 10*106 [clocks/s] / 1*109 [clocks/s] = 1%

OK if not too many I/O devices


% Processor time to poll hard disk

Frequency of Polling Disk= 16 [MB/s] / 16 [B] = 1M [polls/s]

•Disk Polling, Clocks/sec= 1M [polls/s] * 400 [clocks/poll] = 400M [clocks/s]

•% Processor for polling: 400*106 [clocks/s] / 1*109 [clocks/s] = 40%

Unacceptable


What is the alternative to polling?

•Wasteful to have processor spend most of its time “spin-waiting” for I/O to be ready

•Would like an unplanned procedure call that would be invoked only when I/O device is ready

•Solution: use exception mechanism to help I/O. Interrupt program when I/O ready, return when done with data transfer


Definitions for Clarification

•Exception: signal marking that something “out of the ordinary” has happened and needs to be handled

• Interrupt: asynchronous exception

•Trap: synchronous exception

•Note: These are different from the book’s definitions.

• All I care about: that you know the difference between sync and async.


I/O Interrupt

•An I/O interrupt is like overflow exceptions except:

• An I/O interrupt is asynchronous

• More information needs to be conveyed

•An I/O interrupt is asynchronous with respect to instruction execution:

• I/O interrupt is not associated with any instruction, but it can happen in the middle of any given instruction

• I/O interrupt does not prevent any instruction from completion


Interrupt Driven Data Transfer

(1) I/Ointerrupt

(2) save PC

Memory

addsubandor

userprogram

readstore...jr

interruptserviceroutine

(3) jump to interruptservice routine(4) perform transfer

(5)


SPIM I/O Simulation: Interrupt Driven I/O• I.E. stands for Interrupt Enable

•Set Interrupt Enable bit to 1 have interrupt occur whenever Ready bit is set

Received Byte

Receiver Data0xffff0004 Unused (00...00)

(IE)Receiver Control0xffff0000

Read

y(I.E

.)Unused (00...00)

TransmittedByte

Transmitter Control0xffff0008

Transmitter Data0xffff000c

Read

y(I.E

.)Unused (00...00)

Unused


Benefit of Interrupt-Driven I/O

•Find the % of processor consumed if the hard disk is only active 5% of the time. Assuming 500 clock cycle overhead for each transfer, including interrupt:

• Disk Interrupts/s = 16 MB/s / 16B/interrupt = 1M interrupts/s

• Disk Interrupts, clocks/s = 1M interrupts/s * 500 clocks/interrupt = 500,000,000 clocks/s

• % Processor for during transfer: 500*106 / 1*109 = 50%

•Disk active 5% 5% * 50%2.5% busy


Generalizing Interrupts•We can handle all sorts of exceptions with interrupts.

•Big idea: jump to handler that knows what to do with each interrupt, then jump back

•Our types: syscall, overflow, mmio ready.


OS: I/O Requirements•The OS must be able to prevent:• The user program from communicating with the I/O device directly

• If user programs could perform I/O directly:• No protection to the shared I/O resources

•3 types of communication are required:• The OS must be able to give commands to the I/O devices

• The I/O device notify OS when the I/O device has completed an operation or an error

• Data transfers between memory and I/O device


Instruction Set Support for OS (1/2)•How to turn off interrupts during interrupt routine?

•Bit in Status Register determines whether or not interrupts enabled: Interrupt Enable bit (IE) (0 off, 1 on)

Status Register(described later) IE


Instruction Set Support for OS (2/2)•How to prevent user program from turning off interrupts (forever)?• Bit in Status Register determines whether in user mode or OS (kernel) mode: Kernel/User bit (KU) (0 kernel, 1 user)

Status RegisterAssume Unused IEKU

• On exception/interrupt disable interrupts (IE=0) and go into kernel mode (KU=0)


Kernel/User Mode

•Generally restrict device access to OS

•HOW?

•Add a “mode bit” to the machine: K/U

•Only allow SW in “kernel mode” to access device registers

• If user programs could access device directly?

• could destroy each others data, ...

• might break the devices, …


Crossing the System Boundary•System loads user program into memory and ‘gives’ it use of the processor

•Switch back• SYSCALL

- request service

- I/O

• TRAP (overflow)

• Interrupt

Proc Mem

I/O Bus

cmd reg.data reg.

System

User


Syscall

•How does user invoke the OS?•syscall instruction: invoke the kernel (Go to 0x80000080, change to kernel mode)

• By software convention, $v0 has system service requested: OS performs request


SPIM OS Services via Syscall

•Note: most OS services deal with I/O

print_int 1 $a0 = integerprint_float 2 $f12 = floatprint_double 3 $f12 = doubleprint_string 4 $a0 = stringread_int 5 integer (in $v0)read_float 6 float (in $f0)read_double 7 double (in $f0)read_string 8 $a0 = buffer,

$a1 = lengthsbrk 9 $a0 = amount address(in $v0)exit 10

Service Code Args Result (put in $v0)


Example: User invokes OS (SPIM)•Print “the answer = 42”

•First print “the answer =”:.datastr:.asciiz "the answer = " .textli $v0,4 # 4=code for print_strla $a0,str # address of string syscall # print the string

•Now print 42

li $v0,1 # 1=code for print_intli $a0,42 # integer to print syscall # print int


Handling a Single Interrupt (1/3)•An interrupt has occurred, then what?

• Automatically, the hardware copies PC into EPC ($14 on cop0) and puts correct code into Cause Reg ($13 on cop0)

• Automatically, PC is set to 0x80000080, process enters kernel mode, and interrupt handler code begins execution

• Interrupt Handler code: Checks Cause Register (bits 5 to 2 of $13 in cop0) and jumps to portion of interrupt handler which handles the current exception


Handling a Single Interrupt (2/3)•Sample Interrupt Handler Code

.text 0x80000080

mfc0 $k0,$13 # $13 is Cause Reg

sll $k0,$k0,26 # isolate

srl $k0,$k0,28 # Cause bits

•Notes:• Don’t need to save $k0 or $k1

- MIPS software convention to provide temp registers for operating system routines

- Application software cannot use them

• Can only work on CPU, not on cop0


Handling a Single Interrupt (3/3)

• When the interrupt is handled, copy the value from EPC to the PC.

• Call instruction rfe (return from exception), which will return process to user mode and reset state to the way it was before the interrupt

•What about multiple interrupts?


Multiple Interrupts•Problem: What if we’re handling an Overflow interrupt and an I/O interrupt (printer ready, for example) comes in?

•Options:• drop any conflicting interrupts: unrealistic, they may be important

• simultaneously handle multiple interrupts: unrealistic, may not be able to synchronize them (such as with multiple I/O interrupts)

• queue them for later handling: sounds good


Prioritized Interrupts (1/3)•Question: Suppose we’re dealing with a computer running a nuclear facility. What if we’re handling an Overflow interrupt and a Nuclear Meltdown Imminent interrupt comes in?

•Answer: We need to categorize and prioritize interrupts so we can handle them in order of urgency: emergency vs. luxury.


Prioritized Interrupts (2/3)•OS convention to simplify software:

• Process cannot be preempted by interrupt at same or lower "level"

• Return to interrupted code as soon as no more interrupts at a higher level

• When an interrupt is handled, take the highest priority interrupt on the queue

- may be partially handled, may not, so we may need to save state of interrupts(!)


Prioritized Interrupts (3/3)•To implement, we need an Exception Stack:

• portion of address space allocated for stack of “Exception Frames”

• each frame represents one interrupt: contains priority level as well as enough info to restart handling it if necessary


Modified Interrupt Handler (1/3)•Problem: When an interrupt comes in, EPC and Cause get overwritten immediately by hardware. Lost EPC means loss of user program.

•Solution: Modify interrupt handler. When first interrupt comes in:

• disable interrupts (in Status Register)

• save EPC, Cause, Status and Priority Level on Exception Stack

• re-enable interrupts

• continue handling current interrupt


Modified Interrupt Handler (2/3)•When next (or any later) interrupt comes in:

• interrupt the first one

• disable interrupts (in Status Register)

• save EPC, Cause, Status and Priority Level (and maybe more) on Exception Stack

• determine whether new one preempts old one

- if no, re-enable interrupts and continue with old one

- if yes, may have to save state for the old one, then re-enable interrupts, then handle new one


Modified Interrupt Handler (3/3)•Notes:

• Disabling interrupts is dangerous

• So we disable them for as short a time as possible: long enough to save vital info onto Exception Stack

•This new scheme allows us to handle many interrupts effectively.


Interrupt Levels in MIPS?•What are they?

• It depends what the MIPS chip is inside of: differ by app Casio PalmPC,Sony Playstation, HP LaserJet printer

•MIPS architecture enables priorities for different I/O events


Interrupt Levels in MIPS Architecture•Conventionally, from highest level to lowest level exception/interrupt levels:

• Bus error

• Illegal Instruction/Address trap

• High priority I/O Interrupt (fast response)

• Low priority I/O Interrupt (slow response)

• (later in course, will talk about other events with other levels)


Improving Data Transfer Performance•Thus far: OS give commands to I/O, I/O device notify OS when the I/O device completed operation or an error

•What about data transfer to I/O device?• Processor busy doing loads/stores between memory and I/O Data Register

• Ideal: specify the block of memory to be transferred, be notified on completion?

• Direct Memory Access (DMA) : a simple computer transfers a block of data to/from memory and I/O, interrupting upon done


Example: code in DMA controller•DMA code from Disk Device to Memory

.dataCount: .word 4096Start: .space 4096

•DMA “computer” in parallel with CPU

.textInitial: lw $s0, Count # No. chars

la $s1, Start # @next char Wait: lw $s2, DiskControl

andi $s2,$s2,1 # select Ready

beq $s2,$0,Wait # spinwaitlb $t0, DiskData # get bytesb $t0, 0($s1) # transferaddiu $s0,$s0,-1 # Count--addiu $s1,$s1,1 # Start++bne $s0,$0,Wait # next

char


Details not covered•MIPS has a field to record all pending interrupts so that none are lost while interrupts are off; in Cause register

•The Interrupt Priority Level that the CPU is running at is set in memory

•MIPS has a field in that can mask interrupts of different priorities to implement priority levels; in Status register

•MIPS has limited nesting of saving KU,IE bits to recall in case higher priority interrupts; in Status Register


Interrupts while serving interrupts?•Suppose there was an interrupt while the interrupt enable or mask bit is off: what should you do? (cannot ignore)

•Cause register has field--Pending Interrupts (PI)-- 5 bits wide (bits15:11) for each of the 5 HW interrupt levels

• Bit becomes 1 when an interrupt at its level has occurred but not yet serviced

• Interrupt routine checks pending interrupts ANDed with interrupt mask to decide what to service

Cause RegisterExcCodePI


support for OS: User => System mode• Bit in Status Register determines whether in

user mode or OS (kernel) mode: Kernel/User bit (KU) (0 kernel, 1 user)

Status Register(described later) IEKU

• On exception/interrupt disable interrupts (IE=0) and go into kernel mode (KU=0)

•How remember old KU, IE bits?• Hardware copies Current KU and IE bits (0-1) into Previous KU and IE bits (2-3)

Status Register(described later) IEKUIEKU 0 0


support for OS: System => user mode•OS saves user registers, performs its task and restores user registers.• can JR back to value saved in EPC

• how to get back to user mode?

•use Return from Exception (rfe)

Status Register(described later) IEK

UIEK

U


Prioritizing Interrupts•How implement interrupt levels?

•Allow selective interruption via Interrupt Mask(IM) in Status Register: 5 for HW interrupts• Interrupt only if IE==1 AND Mask bit == 1 (bits 15:11 of SR) for that interrupt level

• Set Mask Bits above your level to 1

•To support interrupts of interrupts, have 3 deep stack in Status for IE,K/U bits: Current (1:0), Previous (3:2), Old (5:4)

IEKUStatus

RegisterIEKUIEKUIM

CPO

0 0


Revised Interrupt Routine 2/2•Jump to appropriate interrupt routine

•On Return, disable interrupts using Current IE bit of Status Register

•Then restore saved registers, previous KU,IE bits of Status (via rfe) and return to instruction determined by old EPC

rfe

IEKU IEKUIEKUIMStatus Reg After

IEKU Status Reg BeforeIEKUIEKUIM

CurrentPre.Old


Re-entrant Interrupt Routine?•How allow interrupt of interrupts and safely save registers?

•Stack? • Resources consumed by each exception, so cannot tolerate arbitrary deep nesting of exceptions/interrupts

•With priority level system only interrupted by higher priority interrupt, so cannot be recursive

•Only need one save area (“exception frame”) per priority level


Things to Remember•Kernel Mode v. User Mode: OS can provide security and fairness

•Syscall: provides a way for a programmer to avoid having to know details of each I/O device

•To be acceptable, interrupt handler must:

• service all interrupts (no drops)

• service by priority

• make all users believe that no interrupt has occurred


Interrupts• Interrupt Implementation


Generalizing Interrupts•Must support:

• Jumping to handler- On exception, proc sets nPC handlerAddr

• Knowing what happened/bookkeeping- EPC: Reg holds ~inst at which nrpt occurred

- Cause: Holds the specific interrupt

• Jumping back to user program- More bookkeeping (back to user mode)

- ~ “jr $EPC”


Knowing what happened•On exception, proc copies PC+4 into EPC:

assign exception = arith_excp | mem_excp | sys_excp

always @ (posedge clk)

if (exception) EPC <= PC + 4;

•Proc copies exception number into cause:

always @ (posedge clk) {

if (arith_excp) Cause <= 0x1;

else if (mem_excp) Cause <= 0x2;

else if (sys_excp) Cause <= 0x4; }


Jumping to handlerNew nPC mux:

assign nPC = (exception) ? 0x04000040

: old_npc;

•Overrides all other nPC signals• Jump to handler takes priority over branch.


In handler:•Handler uses special regs/instrs to access exception data:

• $k0/$k1 (Why not $t0 … $t9?)

• mfc0 $reg $EPC

• mfc0 $reg $CAUSE

• When done, move EPC (or whatever) into $k0 and then jr $k0.


Proc Support for mfc0:•mfc0 $reg X

Lots of options:

• In decode as “add $reg X $0”:- Mux in front of BusA <- ForwardA, Cause, EPC

- Mux in front of BusB <- ForwardB, 0

• In wb:- Mux in front of regdst:

Regdst <- ALUout, MemOut, Cause, EPC

Which one do you think pipelines better?


What about pipelining?!

• Precise Exceptions State of the machine is preserved as if program executed up to (not including) the offending instruction

• All previous instructions completed

• Offending instruction and all following instructions act as if they have not even started

• Same system code will work on different implementations


Exception/Interrupts: Implementation

5 instructions, executing in 5 different pipeline stages!

• Who caused the interrupt?

Stage Problem interrupts occurring

IF Page fault on instruction fetch; misaligned memory access; memory-protection violation

ID Undefined or illegal opcode; syscall

EX Arithmetic exception

MEM Page fault on data fetch; misaligned memory access; memory-protection violation; memory

error

• How do we stop the pipeline? How do we restart it?

• Do we interrupt immediately or wait?

• How do we sort all of this out to maintain preciseness?


Exception Handling

npc

I mem

Regs

B

alu

S

D mem

m

IAU

PClw $2,20($5)

Regs

A im op rwn

detect bad instruction address

detect bad instruction

detect overflow

detect bad data address

Allow exception to take effect

Excp

Excp

Excp

Excp


Another look at the exception problem

• Use pipeline to sort this out!

• Pass exception status along with instruction.

• Keep track of PCs for every instruction in pipeline.

• Don’t act on exception until it reaches WB stage

• When instruction reaches WB stage:

• Save PC EPC, exc_status cause, handler addr PC

• Turn all instructions in earlier stages into noops!

Pro

gram

Flo

w

Time

IFetch Dcd Exec Mem WB




Data TLB

Bad Inst

Inst TLB fault

Overflow


Detailed implementation• New pipeline regs:

• Valid <- If instr. Is not valid, no writes to regfile or mem will occur. Invalids will not trigger exceptions

• iPC <- addr of the current instr. Will go into EPC

• Exception <- type of exception. Will go into cause.

• In each stage: if excepting, set except reg. “flag exception”

• In MEM, WB, only do write if Valid

• In WB: “raise exception” …


Detailed implementation• In WB:

if (ME/WB.Valid & ME/WB.Except) {

IF/DE.valid_in = DE/Ex.Valid_in = EX/ME.Valid_in = ME/WB.valid_in = 0;

npc ME/WB.iPC;

cause Me/WB.Except;

EPC Me/WB.iPC;

Documents

CS 61C L6.2.2 Interrupts (1) K. Meinz, Summer 2004 © UCB CS61C : Machine Structures Lecture 6.2.2 Interrupts 2004-07-29 Kurt Meinz inst.eecs.berkeley.edu/~cs61c