Upload
others
View
2
Download
0
Embed Size (px)
Citation preview
CS61C:GreatIdeasinComputerArchitecture
VirtualMemoryCont.
Instructors:VladimirStojanovic&NicholasWeaverhttp://inst.eecs.berkeley.edu/~cs61c/
1
2
“Bare”5-StagePipeline
• Inabaremachine,theonlykindofaddressisaphysicaladdress
PCInst.Cache D Decode E M
DataCache W+
MainMemory (DRAM)
MemoryController
PhysicalAddress
PhysicalAddress
PhysicalAddress
PhysicalAddress
PhysicalAddress
AddressTranslation
• So,whatdowewanttoachieveatthehardwarelevel?– TakeaVirtualAddress,thatpointstoaspotintheVirtualAddressSpaceofaparticularprogram,andmapittoaPhysicalAddress,whichpointstoaphysicalspotinDRAMofthewholemachine
3
VirtualPageNumber OffsetVirtualAddress
PhysicalAddress Physical PageNumber Offset
AddressTranslation
4
VirtualPageNumber Offset
Physical PageNumber Offset
VirtualAddress
PhysicalAddress
AddressTranslation
CopyBits
Therestofthelectureisallaboutimplementing
5
• Processor-generatedaddress canbesplitinto:PagedMemorySystems
Page tables make it possible to store the pages of a program non-contiguously.
0123
0123
Address Spaceof Program #1
Page Table of Program #1
10
2
3
Physical Memory
• Apagetablecontainsthephysicaladdressofthebaseofeachpage
VirtualPageNumber Offset
6
Private(Virtual)AddressSpaceperProgram
VA1Prog 1
Page Table
VA1Prog 2
Page Table
VA1Prog 3
Page Table
Phys
ical
Mem
ory
free
OSpages
• Each prog has a page table • Page table contains an entry for each prog page• Physical Memory acts like a “cache” of pages for currently
running programs. Not recently used pages are stored in secondary memory, e.g. disk (in “swap partition”)
7
WhereShouldPageTablesReside?• Spacerequiredbythepagetables(PT)isproportionaltotheaddressspace,numberofusers, ...
Þ ToolargetokeepinregistersinsideCPU
• Idea:Keeppagetablesinthemainmemory– NeedsonereferencetoretrievethepagebaseaddressandanothertoaccessthedatawordÞ doublesthenumberofmemoryreferences! (butwecan
fixthisusingsomethingwealreadyknowabout…)
8
PageTablesinPhysicalMemory
VA1
Prog 1 Virtual Address Space
Prog 2 Virtual Address Space
PT Prog1
PT Prog2
VA1
Phys
ical
Mem
ory
9
Linear(simple)PageTable
VPN OffsetVirtual address
PT Base Register
VPN
Data word
Data Pages
Offset
PPNPPN
DPNPPN
PPNPPNPage Table
DPN
PPN
DPNDPN
DPNPPN
• PageTableEntry(PTE)contains:– 1bittoindicateifpageexists– AndeitherPPNorDPN:– PPN(physicalpagenumber)foramemory-residentpage
– DPN(diskpagenumber)forapageonthedisk
– Statusbitsforprotectionandusage(read,write,exec)
• OSsetsthePageTableBaseRegisterwheneveractiveuserprocesschanges
10
Supposeaninstructionreferencesamemorypagethatisn’tinDRAM?
• Wegetanexceptionoftype“pagefault”• Pagefaulthandlerdoesthefollowing:– Ifvirtualpagedoesn’tyetexist,assignanunusedpageinDRAM,orifpageexists…
– Initiatetransferofthepagewe’rerequestingfromdisktoDRAM,assigningtoanunusedpage
– Ifnounusedpageisleft,apagecurrentlyinDRAMisselectedtobereplaced(basedonusage)
– Thereplacedpageiswritten(back)todisk,pagetableentrythatmapsthatVPN->PPNismarkedasinvalid/DPN
– Pagetableentryofthepagewe’rerequestingisupdatedwitha(now)validPPN
11
SizeofLinearPageTableWith32-bitmemoryaddresses,4-KiBpages:
Þ 232 /212 =220 virtualpagesperuser,assuming4-BytePTEs,Þ 220 PTEs,i.e,4MiB pagetableperuser!
Largerpages?• Internalfragmentation(Notallmemoryin pagegetsused)• Largerpagefaultpenalty(moretimetoreadfromdisk)
Whatabout64-bitvirtualaddressspace???• Even1MiBpageswouldrequire2448-BytePTEs(128TiB!)
Whatisthe“savinggrace”?
Mostprocesses onlyuseasetofhighaddress (stack),andasetoflowaddress (instructions,heap)
12
HierarchicalPageTable– exploitssparsityofvirtualaddressspaceuse
Level 1 Page Table
Level 2Page Tables
Data Pages
page in primary memory page in secondary memory
Root of the CurrentPage Table
p1
p2
Virtual Address
(ProcessorRegister)
PTE of a nonexistent page
p1 p2 offset01112212231
10-bitL1 index
10-bit L2 index
Phys
ical
Mem
ory
MT2Grades
13
59%
Administrivia• UpcomingLectureSchedule– 04/18:VM(today)– 04/20:I/O:DMA,Disks– 04/22:Networking– 04/25:Dependability:Parity,ECC(+HKNreviews)– 04/27:RAID• Lastdayofnewmaterial
– 04/29:Summary,What’sNext?
14
Administrivia
• Project4programmingcompetitionrulesposted
• Project5released– dueon4/26• GuerrillaSession:VirtualMemory– Wed4/203- 5PM@241Cory– Sat4/221- 3PM@521Cory
• LastHW(3)VirtualMemory– Due05/01
15
16
AddressTranslation&Protection
• Every instruction and data access needs address translation and protection checks
A good VM design needs to be fast (~ one cycle) and space efficient
Physical Address
Virtual Address
AddressTranslation
Virtual Page No. (VPN) offset
Physical Page No. (PPN) offset
ProtectionCheck
Exception?
Kernel/User Mode
Read/Write
17
TranslationLookaside Buffers(TLB)Address translation is very expensive!
In a two-level page table, each reference becomes several memory accesses
Solution: Cache some translations in TLBTLB hit Þ Single-Cycle TranslationTLB miss Þ Page-Table Walk to refill
VPN offset
V R W D tag PPN
physical address PPN offset
virtual address
hit?
(VPN = virtual page number)
(PPN = physical page number)
18
TLBDesigns• Typically32-128entries,usuallyfullyassociative
– Eachentrymapsalargepage,hencelessspatiallocalityacrosspages=> morelikelythattwoentriesconflict
– SometimeslargerTLBs (256-512entries)are4-8wayset-associative
– Largersystemssometimeshavemulti-level(L1andL2)TLBs• RandomorFIFOreplacementpolicy• “TLBReach”:Sizeoflargestvirtualaddressspacethatcan
besimultaneouslymappedbyTLB
Example:64TLBentries,4KiBpages,onepageperentry
TLBReach=_____________________________________________?
VM-relatedeventsinpipeline
• HandlingaTLBmissneedsahardwareorsoftwaremechanismtorefillTLB– usuallydoneinhardwarenow
• Handlingapagefault(e.g.,pageisondisk)needsaprecisetrapsosoftwarehandlercaneasilyresumeafterretrievingpage
• Handlingprotectionviolationmayabortprocess19
PCInst TLB
Inst. Cache D Decode E M
Data TLB
Data Cache W+
TLB miss? Page Fault?Protection violation?
TLB miss? Page Fault?Protection violation?
20
HierarchicalPageTableWalk:SPARCv8
31 11 0
Virtual Address Index 1 Index 2 Index 3 Offset31 23 17 11 0
ContextTableRegister
ContextRegister
root ptr
PTPPTP
PTE
Context Table
L1 Table
L2 TableL3 Table
Physical Address PPN Offset
MMU does this table walk in hardware on a TLB miss
21
Page-BasedVirtual-MemoryMachine(HardwarePage-TableWalk)
PCInst.TLB
Inst.Cache D Decode E M
DataCache W+
PageFault?Protectionviolation?
PageFault?Protectionviolation?
• Assumespagetablesheldinuntranslated physicalmemory
DataTLB
MainMemory (DRAM)
MemoryControllerPhysicalAddress
PhysicalAddress
PhysicalAddress
PhysicalAddress
Page-Table Base Register
VirtualAddress Physical
Address
VirtualAddress
HardwarePageTableWalker
Miss? Miss?
22
AddressTranslation:puttingitalltogetherVirtual Address
TLBLookup
Page TableWalk
Update TLBPage Fault(OS loads page)
ProtectionCheck
PhysicalAddress(to cache)
miss hit
the page is Ï memory Î memory denied permitted
ProtectionFault
hardwarehardware or softwaresoftware
SEGFAULTWhere?
23
ModernVirtualMemorySystemsIllusionofalarge,private,uniformstore
Protection & Privacyseveral users, each with their private address space and one or more shared address spaces
page table ºname space
Demand PagingProvides the ability to run programs larger than the primary memory
Hides differences in machine configurations
The price is address translation on each memory reference
OS
useri
PrimaryMemory
Swapping Store(Disk)
VA PAmappingTLB
ClickerQuestion
Let’strytoextrapolatefromcaches…Whichoneisfalse?A.#offsetbitsinV.A.=log2(pagesize)B.#offsetbitsinP.A.=log2(pagesize)C.#VPNbitsinV.A.=log2(#ofphysicalpages)D.#PPNbitsinP.A.=log2(#ofphysicalpages)E.Asingle-levelpagetablecontainsaPTEforeverypossibleVPNinthesystem
24
25
Conclusion:VMfeaturestrackhistoricaluses
• Baremachine,onlyphysicaladdresses– Oneprogramownedentiremachine
• Batch-stylemultiprogramming– SeveralprogramssharingCPUwhilewaitingforI/O– Base&bound:translationandprotectionbetweenprograms(notvirtualmemory)
– Problemwithexternalfragmentation(holesinmemory),neededoccasionalmemorydefragmentationasnewjobsarrived
26
Conclusion:VMfeaturestrackhistoricaluses
• Timesharing– Moreinteractiveprograms,waitingforuser.Also,morejobs/second.
– Motivatedmovetofixed-sizepagetranslationandprotection,noexternalfragmentation(butnowinternalfragmentation,wastedbytesinpage)
– Motivatedadoptionofvirtualmemorytoallowmorejobstosharelimitedphysicalmemoryresourceswhileholdingworkingsetinmemory
• VirtualMachineMonitors– Runmultipleoperatingsystemsononemachine– Ideafrom1970sIBMmainframes,nowcommononlaptops
• e.g.,runWindowsontopofMacOSX– Hardwaresupportfortwolevelsoftranslation/protection
• GuestOSvirtual->GuestOSphysical->Hostmachinephysical– AlsobasisofCloudComputing
• VirtualmachineinstancesonEC2