CS 350 Operating SystemsSpring 2021

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13. Paging and Address Translation

Address Space

• Address space is another fundamental abstraction in OSes to virtualize memory for users to easily to use computers.

• Address space is a running program’s virtual view of (physical) memory in the system, starting from 0 and growing to a very large number (2^n, where n is the address length); it contains all the memory state of the running program.

• Practically, it is impossible to fit a large address space into a limited physical memory; thus, the address space is practically divided into small pieces (i.e., pages) and only the needed pieces are put into memory – called virtual memory.

• The OS will maintain the mappings between address space and physical memory and translate an address in the address space to the address in the physical memory (in this lecture).

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PagingAddress Space

of a single Process

EntirePhysical RAM

Page}• Address space could be very large

and not easy to fit into the physical memory

• Paging: Split up the address space into equal-sized units, which are called pages

• Paging allows the OS to keep only needed portion of address space into physical memory• Physical memory is also (logically)

divided into equal-sized slots, called frames

• The OS maintains the mappingsbetween pages and frames

}frame

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Why Paging?• What if a process is “smaller” than the physical memory

• Only the pages that are used by the process are loaded to the physical memory

Virtual Address Space of a single Process Entire

Physical RAM

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Why Paging?• What if a process is “bigger” than the physical memory

• Only the pages that are used currently by the process are loaded to the physical memory

• The remaining pages are stored somewhere else (e.g., hard disks)

Virtual Address Space of a single Process Entire

Physical RAM

Stored in Hard disk

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Why Paging?• What if multiple processes share the physical memory

• Pages from different processes can be dynamically scattered across the whole physical memory

• OS maintains the mappings for each process. But how?

Address Space1

EntirePhysical RAM

Address Space

Mappings

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Page Table• A per-process, in-kernel array that stores the mapping from pages to

their hosting physical frames.• A page is represented using a virtual page number (VPN)

• The first page’s VPN is 0, the second page’s VPN is 1, and so on

• A physical frame is represented using a physical frame number (PFN)

• The first frame’s PFN is 0, the second frame’s VPN is 1, and so on

Page 4

Page 3

Page 2

Page 1

Page 0

Address Space Physical RAM

Frame 0

Frame 1

Frame 2

Frame 3

0x0

max

0x0

max'

VPN

4

1

2

3

0

PFN

0

1

2

3

Page Table

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Page Table• A Page table is just a big array with each page table entry (PTE),

storing a mapping from one VPN to one PFN• The first PTE stores page 0’s mapped PFN, the second entry stores page

1’s mapped PFN, and so on; actually, a VPN serves as the index to the page table to locate the PTE of a page

• A page could map to NULL, indicating that the page is not allocated and/or loaded to physical memory

• In addition to PFN, each PTE also stores some meta information for the page used for memory management

PFN

Page 4

Page 3

Page 2

Page 1

Page 0

Address Space

Physical RAMPage Table

Frame 0

Frame 1

Frame 2

Frame 3

0x0

max

0x0

max'

2

X (not present)

0

1

3

VPN

4

1

2

3

0

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Summary of Terminologies• Pages: address space is split into equal-sized units, called pages• VPN: a page is identified by its virtual page number – locating the page’s position in address

space• Frames: physical memory is split into equal-sized units, called frames• PFN: a frame is identified by its physical frame number – locating the frame’s position in

main memory• Page table: Per-process array storing mappings between each page and its physical frame

(could be NULL)• PTE: a page table entry (PTE) stores a virtual page’s physical frame as well as other meta

data; VPN serves as the index to locate its page’s PTE

PFN

Page 4

Page 3

Page 2

Page 1

Page 0

Address Space

Physical RAMPage Table

Frame 0

Frame 1

Frame 2

Frame 3

0x0

max

0x0

max'

2

X (not present)

0

1

3

VPN

4

1

2

3

0

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Size of Page Table

• Question? What are the main factors determining the size of a page table (i.e., the number of entries)?• Page size

• Size of address space

number_of_entries = size_of_address_space/page_size

• Consider a machine that has a 32-bit address space and 8 KByte page size. What is the total size (in bytes) of the address space for each process? How many PTEs do we need?

Size_of_address_space = 2^32 bytes

Number_of_entries = size_of_address_space/page_size

= 2^32 bytes/8 Kbytes = 2^19

Points to note

• Page table is a per-process, in-kernel data structure

• Maintained by OS and stored in kernel memory

• Each page in the address space has a PTE in the page table• Present --- loaded to a physical frame and maps to a physical frame

• Not present --- stored in hard disk or not used by the process

• Size of a page table is determined by 1) size of address space and 2) page size• Usually, size of address space is fixed (determined by hardware)

• Page size can be configured (e.g., 4 KB by default in Linux)

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Address Translation

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Address Translation• While a process is being executed, it only can reference addresses

(instruction and data) within its address space

• The content is stored in some physical location – the processor needs to know the physical location to access those content (i.e., instruction or data)

• Hence, each memory access needs translation from virtual address to physical address.

0x0100

0xffffAddress space

.text

.data

Heap

Stack

0x0200

pc

esp 0x0e00

inst1

Global var1

inst1

Global var1

Physical memory

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An examplevoid func()

{

int x = 3000;

x = x + 3;

…

code snippet

124: movl %esp, %ebx ;load x addr to ebx128: movl 0x0(%ebx), %eax ;load 0+ebx into eax

;read value of x to eax132: addl $0x03, %eax ;add 3 to eax register136: movl %eax, 0x0(%ebx) ; store eax back to mem

Assembly code

• When the process runs, the processor：1. Fetches instruction at address 124 2. This instruction loads the address (i.e.,

15K) of variable x to register ebx. Assume that, the address is held by the stack register esp.

3. Fetches instruction at address 1284. This instruction loads the value stored

at address 15 K (i.e., 0+ebx) to register eax

5. Fetches instruction at address 1326. This instruction adds 3 to register eax7. Fetches instruction at address 1368. This instruction stores eax back to

address 15 K (i.e., 0+ebx) 0

0xffffffff

Stack

free

Address space

x=3000esp

movl %esp, %ebxmovl 0x0(%ebx), %eaxaddl $0x03, %eaxmovl %eax, 0x0(%ebx)

pc 124

128

132136

Heap

15K

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An example

1. Fetches instruction at address 124 2. This instruction loads the address (i.e.,

15K) of variable x to register ebx. Assume that, the address is held by the stack register esp.

3. Fetches instruction at address 1284. This instruction loads the value stored

at address 15 K (i.e., 0+ebx) to register eax

5. Fetches instruction at address 1326. This instruction adds 3 to register eax7. Fetches instruction at address 1368. This instruction stores eax back to

address 15 K (i.e., 0+ebx)

• For each of the following steps, does memory access take place?

• For each memory access, an address translation is needed.

• But how?Memory Access

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Address Translation with paging• Given an address space with the

size of 2^n (n is the system bit number, e.g., n=32)

• With paging, the address space is divided into a group of equal-sized pages with each page size of N (e.g., 4 KB)

• Given an arbitrary virtual address x in address space:• It can be located with its page and

offset within the page• How do we know which page x

resides, or which virtual page number (VPN) it resides ?

• How do we know the offset of x in its page?

Address Space

n-1

nByte Offset

VirtualPage

Numbers(VPN)

n+1

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Address Translation with paging

kn-1 n-2 n-3 … k-1 k-2 1 0

VPN (m bits) Byte offset (n-m bits)

• The virtual address is divided into two parts: VPN and byte offset • VPN: The first m bits (from left) represent virtual page number• Byte offset: The remaining (n-m) bits represent byte offset within the page

• To determine m: • Given the address space of 2^n size and N page size, it has (2^n)/N pages• Given m bits, it supports up to 2^m pages• Thus: 2^m = (2^n) / N

𝑚 = 𝑙𝑜𝑔2

2𝑛

𝑁 = 𝑛 − 𝑙𝑜𝑔2𝑁

• Thus, byte offset 𝑛 −𝑚 = 𝑙𝑜𝑔2

𝑁

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An exerciseConsider a machine that has a 32-bit virtual address size and 4 KByte page size.

1.How large is the address space?2^32 = 4 GB

1.How many pages could a process have?4GB/4KB = 2^20

2. How many page-table entries (for one process) are there in the page table?

2^20 (same as the page number)3. How many address bits are needed to determine a VPN

32 - Log2(4KB) = 32 – Log2(2^12) = 204. How many address bits are needed for the byte offset within a 4-KB page

Log2(4KB) =Log2(2^12) = 12

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Discussion

• VPN (i.e., how many bits in VPN) is determined by the total number of pages

𝑚 = 𝑙𝑜𝑔2

2𝑛

𝑁 , where 2𝑛

𝑁is the total number of pages within

an address space

• Byte offset (i.e., how many bits in byte offset) is determined by page size𝑛 −𝑚 = 𝑙𝑜𝑔2

𝑁, where N is the page size

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A quick quizConsider a machine that has a 16-bit address space and 4KByte page size.

1. Total size (in bytes) of the virtual address space for each process2^16 = 64 * 1024 bytes = 64 KB

2. Number of pages in virtual address space 64 KB / 4 KB = 16

3. How many bits to represent VPNlog2(16) = 4

4. How many bits to represent the byte offset within a page?log2(4KB) = log2(2^12) = 12Also, 16 – 4 = 12 bits

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Address Translation with paging• Given an address space with the size of 2^n (e.g., n=16)

• For an arbitrary virtual address x (e.g., 0xb008) in the address

• Address translation from the virtual address (e.g., 0xb008) to physical address:1. Get the VPN (e.g., 0xb -- VPN = 11), and byte offset (e.g., 0x008)

2. From the VPN’s entry in the page table, get the physical frame number (PFN) (e.g., 0x7008)

3. Concatenate PFN and the byte offset - the physical memory address

Address Space

0xb008

(VPN) 010 10001 11110 12000 13100 14011 15000 06000 07000 08101 19000 010111 111000 012000 013000 014000 015

VPN PFN Present?

Page table

VPN = 11

Byte OffsetPhysical address

0x7008

(PFN) 0

1

7Byte Offset

Physical memory

x

Points to note

• Address translation• Virtual address (in address space) -> physical address (in main

memory)

• Translation procedures• Extract VPN and BYTE_OFFSET from the virtual address

• Look up the page table and retrieve the PFN from the entry indexed by VPN

• PFN + BYTE_OFFSET -> physical address, where data is stored

• Alternative view• The address translation can also be viewed as identifying the

physical frame from a virtual page via page table (since the byte offset in the virtual page and physical frame is same)

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Question?Consider a 32-bit machine:

• Q1: assume 4-KB pages and one page table entry (PTE) takes 8 bytes, what is the total memory for storing one process’s page table? How about 100 processes?

• Q2: Assume 2-KB pages and one PTE takes 8 bytes, what is the total memory for storing one process’s page table?

• Q3: Assume 16-KB pages and one PTE takes 8 bytes, what is the total memory for storing one process’s page table?

• Any thoughts?

Complete this question before next lecture!

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Readings

• OSTEP: (finish reading these two chapters)• Address Translation:

https://pages.cs.wisc.edu/~remzi/OSTEP/vm-mechanism.pdf

• Paging: Introduction https://pages.cs.wisc.edu/~remzi/OSTEP/vm-paging.pdf