CS-280Dr. Mark L. Hornick

1

Atmel Timer/Counter System

Most microcontrollers include some type of timer system

Facilitates real-time monitoring and control1. Measuring time between two event occurrences

Motor speed based on time for a full revolution

2. Invoking an action at precise intervals Injecting fuel into an engine’s combustion chamber

3. Measuring the number of events that occur within a specific time interval

Number of engine misfires

4. Generating a waveform at a specific frequency

CS-280Dr. Mark L. Hornick

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Atmega32 Timer/Counter subsystem has 3 T/C units

Timer/Counter 0 8-bit timer

Timer/Counter 1 16-bit timer

Timer/Counter 2 8-bit timer

Subsequent slides will focus on Timer/Counter 0

CS-280Dr. Mark L. Hornick

3

8-bit Timer/Counter 0Overview

Counter value is stored in 8-bit I/O register TCNT0 TCNT0 is automatically incremented TCNT0 can be read or written at any time

The counter is driven by either: External signal on pin T0 (PB0) CPU internal clock

A scale factor can be applied to slow down the clock signal to the T/C

TCNT0 is incremented with each clock tick A specified number of increments corresponds

to a precise time interval

Basic operation of the Timer/Counter (8-bit)

CS-280Dr. Mark L. Hornick

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MAX=TOP = 0xFF

BOTTOM = 0x00

ticks

TCNT0 value

Counter is started hereand automatically incrementsat a precise rate

Counter reaches itsMAX value and is automatically reset to 0

CS-280Dr. Mark L. Hornick

5

Controlling the frequency of the Timer/Counter

Controlled by bits CS00:CS02 of the TCCR0 (Timer/Counter 0 Control Register)

0 0 0 Counter/Timer stopped (does not increment) 0 0 1: Counter incremented every CPU clock tick 0 1 0: Counter incremented every 8 clock ticks 0 1 1: Counter incremented every 64 clock ticks 1 0 0: Counter incremented every 256 clock ticks 1 0 1: Counter incremented every 1024 clock ticks

1 1 0: use external clock source on T0 (PB0) pin; falling edge 1 1 1: use external clock source on T0 (PB0) pin; rising edge

Ext clock source can be anything that generates a signal (e.g. pushbutton)

CS-280Dr. Mark L. Hornick

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The Timer/Counter has several modes of operation:

Mode is determined by bits WGM00:WGM01

0:0 – Normal mode TOP is 0xFF

After reaching 0xFF, rolls over to 0x00 and starts over

0:1 – (CTC) mode : Clear Timer on Compare match TOP is determined by the value assigned to OCR0

When TCNT0=OCR0 (compare match) TCNT0 is reset to 0

There are also two other modes we’ll discuss later…

Behavior of T/C in Normal vs. CTC Modes

CS-280Dr. Mark L. Hornick

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MAX=TOP = 0xFF

MAX=0xFF

TOP

BOTTOM = 0x00

ticks

ticks

Counter value

Counter value

Normal Mode

CTC ModeBOTTOM = 0x00

Value of TOP is the value of OCR0, which you can modifyat any time within your program

CS-280Dr. Mark L. Hornick

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Normal Mode Interrupt of Timer/Counter 0

When TCNT0 overflows from 0xFF to 0, TOV0 flag in TIFR is set

The TIMSK Register controls generation of interrupts on overflow When TOV0 is set and TOIE0 is enabled:

Overflow interrupt is generated ISR is setup via jump vector 0x16 TOV0 is cleared when the ISR is executed

Normal mode interrupt

CS-280Dr. Mark L. Hornick

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MAX=TOP = 0xFF

BOTTOM = 0x00

ticks

TCNT0 value

Counter is started hereand automatically incrementsat a precise rate

Timer interrupt TOIE1 occurswhen TCNT0 overflows (resets)

TOV0 flag is set on overflow and resets automatically when TOIE1ISR is vectored

Normal Mode

CS-280Dr. Mark L. Hornick

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CTC Mode Interrupts of Timer/Counter 0

When TCNT0=OCR0, OCF0 flag in TIFR is set When in CTC mode, TCNT0 is automatically reset to 0

The TIMSK Register controls generation of Output Comparator interrupts (as well as Counter Overflow interrupts described earlier) When OCF0 is set and OCIE0 is enabled:

Compare Match interrupt is generated ISR is setup via jump vector 0x14 OCF0 is cleared when the ISR is executed

CTC mode interrupt

CS-280Dr. Mark L. Hornick

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Counter is started hereand automatically incrementsat a precise rate

Timer interrupt OCIE1 occurswhen TCNT0=OCR0 (compare match)

OCF0 flag is set on match and resets automatically when OCIE1ISR is vectored

MAX=0xFF

TOP

ticks

Counter value

CTC ModeBOTTOM = 0x00

CS-280Dr. Mark L. Hornick

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The Output Comparator circuitry can be configured to drive a voltage on OC0 (PB3) high or low

When in CTC mode, bits COM01:COM00 affect the operation as follows:

0 0: OC0 disconnected 0 1: Toggle OC0 on compare match 1 0: Clear OC0 on compare match 1 1: Set OC0 on compare match

PB3 must be setup for output

Signal patterns on OC0

CS-280Dr. Mark L. Hornick

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MAX=0xFF

TOP

ticks

Counter value

CTC ModeBOTTOM = 0x00

COM01:COM00 = 1:1 Set OC0 on compare match

COM01:COM00 = 1:0 Clear OC0 on compare match

COM01:COM00 = 0:1 Toggle OC0 on compare match

Interrupt frequency can be varied by modifying the value of OCR0

CS-280Dr. Mark L. Hornick

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CS-280Dr. Mark L. Hornick

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Review SFIOR – A/D Special Function Register

ADC can be configured to perform A/D conversion based on Counter overflow or Output Comparator match