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CS 230: Computer Organization and

Assembly LanguageAviral

ShrivastavaDepartment of Computer Science and

EngineeringSchool of Computing and Informatics

Arizona State University

Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

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Announcements• Project 3

– Due October 19, 2009

• Midterm– Thursday, October 22, 2009– Contents

• MIPS ISA and Programming• Function calls and register conventions• Assembling MIPS Instructions• 2’s complement number system• FP number system

• Finals– Tuesday, Dec 08, 2009

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Computer Organization

• We have leaned the ISA of the processor till now– Given an algorithm, express it in terms of the

processor ISA

Instruction Set Architecture

software

hardware

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High-level language program (in C) swap (int v[], int k) . . .

Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31

Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

Below the Program

C - Compiler

Assembler

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Working of Computer

Processor

Control

Datapath

Memory

Devices

Input

Output

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Input Device Inputs Object Code

Processor

Control

Datapath

Memory

Devices

Input

Output

000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

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Object Code Stored in Memory

Processor

Control

Datapath

Memory Devices

Input

Output

000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000

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Processor Fetches an Instruction

Processor

Control

Datapath

Memory Devices

Input

Output

000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000

Processor fetches an instruction from memory

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Control000000 00100 00010 0001000000100000

Control Decodes the Instruction

Processor

Datapath

Memory

Devices

Input

Output

Control decodes the instruction to determine what to execute

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Datapath Executes the Instruction

Processor

Control

Datapath

Memory

Devices

Input

Outputcontents Reg #4 ADD contents Reg #2results put in Reg #2

Datapath executes the instruction as directed by control

000000 00100 00010 0001000000100000

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Update the PC, and continue

Processor

Control

Datapath

Memory Devices

Input

Output

000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000

Fetch

DecodeExecute

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Output Data Stored in Memory

Processor

Control

Datapath

Memory Devices

Input

Output000001000101000000000000000000000000000001001111000000000000010000000011111000000000000000001000

At program completion the data to be output resides in memory

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Output Device Outputs Data

Processor

Control

Datapath

Memory

Devices

Input

Output

000001000101000000000000000000000000000001001111000000000000010000000011111000000000000000001000

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MIPS ISA to Implement• Arithmetic Instructions

– Add, sub, AND, OR, and slt (R-type)

• Memory access instructions– LW, and SW (I-type)

• Branch instructions– Beq (I-type)

• Jump instructions– J (J-type)

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MIPS Machine

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Shiftleft 2

0

1

Jump

32Instr[25-0]

26PC+4[31-28]

28

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Build a MIPS Processor• Today – Build the ALU

– Support all the Arithmetic/Logic operations

32

32

32

ALU control lines

result

a

b

ALU

ALU Control Lines

Function

0000 AND0001 OR0010 add0110 subtract0111 Set on less

than1100 NOR

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ALUOp and ALU control bits

Instruction Opcode

ALUOp

Instruction operation

Funct field

Desired ALU action

ALU control input

LW 00 Load word XXXXXX

add 0010

SW 00 Store word XXXXXX

Add 0010

Beq 01 Branch equal XXXXXX

Subtract 0110

R-type 10 Add 100000 Add 0010R-type 10 Subtract 100010 Subtract 0110R-type 10 AND 100100 AND 0000R-type 10 OR 100101 OR 0001R-type 10 Set on less

than101010 Set on less

than0111

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Implementation

Truth table for 4 ALU control bits

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Building a 1-bit Binary Adder

S = A xor B xor carry_in carry_out = (A and B) or (A and carry_in) or (B and

carry_in)

1 bit Full Adder

A

BS

carry_in

carry_out

• How can we use it to build a 32-bit adder?• How can we modify it easily to build an

adder/subtractor?

A B carry_in

carry_out

S

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

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Building 32-bit Adder• Just connect the carry-out

of the least significant bit FA to the carry-in of the next least significant bit and connect . . .

• Ripple Carry Adder (RCA)– advantage: simple logic, so

small (low cost)– disadvantage: slow and lots

of glitching (so lots of energy consumption)

1-bit FA

A0

B0S0

c0=carry_in

c1

1-bit FA

A1

B1S1

c2

1-bit FA

A2

B2S2

c3

c32=carry_out

1-bit FA

A31

B31S31

c31

. . .

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Building 32-bit Adder/Subtractor

• Remember 2’s complement is just– complement all the bits

– add a 1 in the least significant bit

A 0111 0111B - 0110 + 1010

1-bit FA S0

c0=carry_in

c1

1-bit FA S1

c2

1-bit FA S2

c3

c32=carry_out

1-bit FA S31

c31

. . .

A0

A1

A2

A31

B0

B1

B2

B31

add/subt

B0

control(0=add,1=subt) B0 if control =

0, !B0 if control = 1

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Logic Operations• Logic operations operate on individual bits of

the operand.$t2 = 0…0 0000 1101 0000$t1 = 0…0 0011 1100 0000and $t0, $t1, $t2 $t0 =or $t0, $t1, $t2 $t0 =xor $t0, $t1, $t2 $t0 =nor $t0, $t1, $t2 $t0 =

• How do we expand our FA design to handle the logic operations - and, or, xor, nor ?

0…0 0000 1100 00000…0 0011 1101 00000…0 0011 0001 00001…1 1100 0010 1111

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A Simple ALU Cell

1-bit FA

carry_in

carry_out

A

B

add/subt

add/subt

result

op

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Tailoring the ALU to the MIPS ISA

• Need to support the set-on-less-than instruction (slt)– remember: slt is an arithmetic instruction– produces a 1 if rs < rt and 0 otherwise– use subtraction: (a - b) < 0 implies a < b

• Need to support test for equality (beq)– use subtraction: (a - b) = 0 implies a = b

• Need to add the overflow detection hardware

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Modifying the ALU Cell for slt

1-bit FA

A

B

result

carry_in

carry_out

add/subt op

add/subt

less

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ALU for slt

0

0set

First perform a subtraction

Make the result 1 if the subtraction yields a negative result

Make the result 0 if the subtraction yields a positive result

A1

B1

A0

B0

A31

B31

+

result1

less

+

result0

less

+

result31

less

. . .tie the most

significant sum bit (sign bit) to the low order less input

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ALU for Zero

+

A1

B1

result1

less

+

A0

B0

result0

less

+

A31

B31

result31

less

. . .0

0

set

First perform subtraction

Insert additional logic to detect when all result bits are zero

zero

. . .

add/subtop

Note zero is a 1 when result is all zeros

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Overflow Detection

• Overflow: the result is too large to represent in the number of bits allocated

• On your own: Prove you can detect overflow by:– Carry into MSB xor Carry out of MSB

1

1

1 10

1

0

1

1

0

0 1 1 1

0 0 1 1+

7

3

0

1

– 6

1 1 0 0

1 0 1 1+

–4

– 5

71

0

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Modifying the ALU for Overflow

+

A1

B1

result1

less

+

A0

B0

result0

less

+

A31

B31

result31

less

. . .0

0

set

Modify the most significant cell to determine overflow output setting

Disable overflow bit setting for unsigned arithmetic

zero

. . .

add/subtop

overflow

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Shift Operations• Also need operations to pack and unpack 8-bit

characters into 32-bit words• Shifts move all the bits in a word left or right sll $t2, $s0, 8 #$t2 = $s0 << 8 bits

srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits

• Such shifts are logical because they fill with zeros

op rs rt rd shamt funct

000000 00000 10000 01010 01000 000000

000000 00000 10000 01010 01000 000010

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Shift Operations• An arithmetic shift (sra) maintain the arithmetic

correctness of the shifted value (i.e., a number shifted right one bit should be ½ of its original value; a number shifted left should be 2 times its original value)– so sra uses the most significant bit (sign bit) as the bit

shifted in– note that there is no need for a sla when using two’s

complement number representation sra $t2, $s0, 8 #$t2 = $s0 >> 8 bits

• The shift operation is implemented by hardware (usually a barrel shifter) outside the ALU

000000 00000 10000 01010 01000 000011

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MIPS Machine

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Shiftleft 2

0

1

Jump

32Instr[25-0]

26PC+4[31-28]

28

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Yoda says…

Use your feelings, Obi-Wan, and find him you will