CS 194-6 Digital Systems Project Laboratory Lecture 7: DRAMcs194-6/fa08/lecnotes/lec7.pdfTo read C, measure V. V > 0.75 volts is a “1”. V < 0.75 volts is a “0”. Cost:

UC Regents Fall 2008 © UCBCS 194-6 L7: DRAM

2008-10-27John Lazzaro

(www.cs.berkeley.edu/~lazzaro)

CS 194-6 Digital Systems Project Laboratory

Lecture 7: DRAM

www-inst.eecs.berkeley.edu/~cs194-6/

TA: Greg Gibeling

1


Today: What’s inside a DRAM chip ?

Memory arrays

DRAM core cells

Silicon technology review

Error correcting codes (ECC DRAM)(if time permits)

2

UC Regents Fall 2008 © UCBCS 194-6 L7: DRAM 44

MooreMoore’’s Law - 2005s Law - 2005

40044004

8080808080868086

8028680286386386™™ Processor Processor

486486™™ Processor ProcessorPentiumPentium® ® ProcessorProcessor

PentiumPentium®® II ProcessorII Processor

PentiumPentium®® III Processor III Processor

PentiumPentium®® 4 Processor 4 ProcessorItaniumItanium™™ ProcessorProcessor

TransistorsTransistors

Per DiePer Die

101088

101077

101066

101055

101044

101033

101022

101011

101000

101099

10101010

80088008

ItaniumItanium™™ 22 ProcessorProcessor

1K1K

4K4K

64K64K

256K256K

1M1M

16M16M4M4M

64M64M

256M256M512M512M

1G1G 2G2G

128M128M

16K16K

1965 Data (Moore)1965 Data (Moore)

MicroprocessorMicroprocessor

MemoryMemory

19601960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

Source: IntelSource: Intel

Moore’s Law for CPUs and DRAMs

From: “Facing the Hot Chips Challenge Again”, Bill Holt, Intel, presented at Hot Chips 17, 2005.

3


Main driver: device scaling ...

66

65nm

300mm

Dual Core

Scaling: Scaling: The Fundamental Cost DriverThe Fundamental Cost Driver

90nm

300mm

130nm

200mm

180nm

200mm

250nm

200mm

350nm

200mm

OROR ==Twice theTwice the

circuitry in thecircuitry in the

same spacesame space

(architectural(architectural

innovation)innovation)

The sameThe same

circuitry in halfcircuitry in half

the spacethe space

(cost reduction)(cost reduction)

Half the die sizeHalf the die sizefor the samefor the same

capability thancapability thanin the priorin the prior

processprocess


4


88

Processed Wafer CostProcessed Wafer Cost

Wafer size conversions offset trend ofWafer size conversions offset trend of

increasing wafer processing costincreasing wafer processing costSource: IntelSource: Intel

Secondary driver: Wafer size


5

UC Regents Fall 2008 © UCBCS 194-6 L7: DRAM 44

MooreMoore’’s Law - 2005s Law - 2005

40044004

8080808080868086

8028680286386386™™ Processor Processor

486486™™ Processor ProcessorPentiumPentium® ® ProcessorProcessor

PentiumPentium®® II ProcessorII Processor

PentiumPentium®® III Processor III Processor

PentiumPentium®® 4 Processor 4 ProcessorItaniumItanium™™ ProcessorProcessor

TransistorsTransistors

Per DiePer Die

101088

101077

101066

101055

101044

101033

101022

101011

101000

101099

10101010

80088008

ItaniumItanium™™ 22 ProcessorProcessor

1K1K

4K4K

64K64K

256K256K

1M1M

16M16M4M4M

64M64M

256M256M512M512M

1G1G 2G2G

128M128M

16K16K

1965 Data (Moore)1965 Data (Moore)

MicroprocessorMicroprocessor

MemoryMemory

19601960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

Source: IntelSource: Intel

Thus, cost per transistor plummets ...


6


Capacitance

7


Recall: Building a capacitor

Conducts electricity well.(metal, doped polysilicon)

TopPlate

BottomPlate

Conducts electricity well(metal, doped polysilicon)

DielectricAn insulator. Does not conducts electricity at all.(air, glass (silicon dioxide))

8


Recall: Capacitors in action

I = 0

Because the dielectric is an insulator, and does not conduct.

After circuit “settles” ...

Q = C V = C * 1.5 Volts (D cell)

Q: Charge stored on capacitorC: The capacitance of the device: function of device shape and type of dielectric.

+++ +++

--- ---

After battery is removed: +++ +++

--- ---Still, Q = C * 1.5 VoltsCapacitor “remembers” charge

1.5V

9


Capacitors and current ...Q = C V

+++ +++

--- ---I V

Differentiate with respect to time ... if C != C(t) ...

dQ/dt = C dV/dt

Observation: If a voltage change dV occurs in zero time (dt = 0), the current I is infinite (impossible).

The voltage across a capacitor cannot change instantaneously. And by Q = C V, the charge stored

on a capacitor cannot change instantaneously.

I is defined as dQ/dt ...

I = C dV/dt

10


State is coded as the amount of energy stored by a device.

+++ +++

--- ---

Storing computational state as charge

State is read by sensing the amount

of energy

+++ +++

--- ---

1.5V

Problems: noise changes Q (up or down), parasitics leak or source Q. Fortunately,

Q cannot change instantaneously, but that only gets us in the ballpark.

11


How do we fight noise and win?Store more energy than we expect from the noise.

Q = CV. To store more charge, use a bigger V or

make a bigger C.Cost: Power, chip size.

Example: 1 bit per capacitor.Write 1.5 volts on C.

To read C, measure V.V > 0.75 volts is a “1”.V < 0.75 volts is a “0”.

Cost: Could have stored many bits on that capacitor.

Represent stateas charge in ways that are robust to noise.

Correct small state errors that are introduced by noise.

Ex: read C every 1 msIs V > 0.75 volts?Write back 1.5V (yes) or 0V (no).Cost: Complexity.

12


MOS Transistors

Two diodes and a capacitor in an interesting arrangement. So, we begin with a diode review ...

13


Diodes in action ...Light emitting

diode (LED)Resistor Light on?

Yes!

No!

Light on?

14


Diodes: Current vs Voltage

Anode+

-Cathode

I V

Diode is onI ⋲ Io exp(V/Vo)

I = Io [exp(V/Vo) - 1]Io range: 1fA to 1nA Vo range: 25mV to 60 mV

Diode is offI ⋲ - Io

15


Making a diode on a silicon wafer

16


A pure (”intrinsic”) silicon crystal ...Conducts electricity

better than an insulator, worse than a conductor.

Why? Most electrons (dots) are in a full “valence” band. Moving in the band is

difficult.Especially near 0 degrees K.

Many electrons, but packed too tight to move.

Lots of room, but few electrons.

electron

energy

Valence band

Conduction band

Forbidden “band gap”

17


Intrinsic silicon crystal as T rises ...Some valence band

electrons diffuse into the conduction band.

These electrons leave behind “holes” in the

valence band, allowing remaining electrons to

move easier.

We think of “holes” as positive carriers ...

More electrons,better conduction

Valence band

Conduction band

electron

energy

18


We “engineer” crystal with impurities ...

19


N-type silicon: add donor atoms

Use diffusion or ion implantation to replace some

of the Si atoms with As

Arsensic has an extra electron that is “donates” to

the conduction band.

Valence band

Conduction bandelectron

energy

Electronsfrom donor atoms.

Improves conductivy.

Donor energy

No change in the number of holes

n+ : heavy doping. n- : light doping.

20


P-type silicon: add acceptor atomsUse diffusion or ion

implantation to replace some of the Si atoms with Boron

Boron has one fewer electron than Si. It can

accept valence band electrons, creating holes.

No change in conduction band electron count Acceptor energy

Number of holes increased, conductivity improves

Valence band

Conduction bandelectron

energy

p+ : heavy doping. p- : light doping.

21


How to make a silicon diode ...Wafer cross-section

n+

p-

Wafer doped p-type

n+ region

p- region At V ⋲ 0, “hill” too high for electrons to diffuse up.

V

Cathode: -

+

-

Anode: +

no carriers

depletion region

For holes, going “downhill” is hard. V controls hill.

electron

energy

depletion region

22


Diodes: Current vs Voltage

Anode+

-Cathode

I V

Diode is onI ⋲ Io exp(V/Vo)

I = Io [exp(V/Vo) - 1]Io range: 1fA to 1nA Vo range: 25mV to 60 mV

Diode is offI ⋲ - Io

23


Note: IC Diodes are biased “off”!

p-

n+

V1

0 V - “ground”

n+

V2V1 V2

V1, V2 > 0V. Diodes “off”, only current is Io “leakage”.

I = Io [exp(V/Vo) - 1]Anodes of all diodes on wafer connected to ground.

24


MOS Transistors

Two diodes and a capacitor in an interesting arrangement ...

25


What we want: the perfect switch.

p-

n+

V1

n+

V2Switch is off. V1 is not

connected to V2.

p-

V1

n+

V2Switch is on. V1 is connected

to V2.

We want to turn a p-type region into an n-type region under

voltage control.

We need electrons to fill valence holes and add

conduction band electrons

+++ +++

--- ---

26


An n-channel MOS transistor (nFET)

p-

n+

Vd = 1V

n+

Vs = 0V Polysilicon gate,dielectric, and substrate form

a capacitor.

nFet is off(I is “leakage”)

dielectric

Vg = 0VI ⋲ nA

----------

p-

n+

Vd = 1V

n+

Vs = 0Vdielectric

Vg = 1V+++++++++----------

Vg = 1V, small region near the surface turns

from p-type to n-type.

nFet is on.

I ⋲ µA

27


Drawing an nFET

“Mask” drawings sent to the fabrication facility to make the chips.

28


Mask set for an n-Fet (circa 1986)

p-

n+

Vd = 1V

n+

Vs = 0Vdielectric

Vg = 0VI ⋲ nA #1: n+ diffusion

Top-down view:

Masks

#3: diff contact#2: poly (gate)

#4: metal

Layers to do p-Fet not shown. Modern processes have 6 to 10 metal layers (or more)(in 1986: 2).

29


“Design rules” for masks, 1986 ...

#1: n+ diffusion #3: diff contact#2: poly (gate) #4: metal

Poly overhang. So that if masks are misaligned, we still get “---” in channel.

Minimum gate length. So that the source and drain depletion regions do not meet!

length

Metal rules:Contact

separation from channel, one fixed contact size, overlap

rules with metal, etc ...

30

CS 152 L11: VLSI UC Regents Fall 2006 © UCB

Fabrication

31

UC Regents Fall 2006 © UCBCS 152 L11: VLSI

Mask set for an n-Fet ...

p-

n+

Vd = 1V

n+

Vs = 0Vdielectric

Vg = 1V

#1: n+ diffusionTop-down view:

Masks

#3: diff contact#2: poly (gate)

#4: metal

How does a fab use a mask set to make an IC?

Vg

Vd

Vs

Ids I ⋲ µA

32


Start with an un-doped wafer ...

Steps

p-

#1: dope wafer p-

#5: place positive poly mask and expose with UV.

UV hardens exposed resist. A wafer wash leaves only hard resist.

#2: grow gate oxide

oxide

#3: grow undoped polysilicon

#4: spin on photoresist

33


Wet etch to remove unmasked ...

p-

oxide

HF acid etches through poly and oxide, but not hardened resist.

p-

oxideAfter etch and resist removal

34


Use diffusion mask to implant n-type

p-

oxide

accelerated donor atoms

n+ n+

Notice how donor atoms are blocked by gate and do not enter channel.

Thus, the channel is “self-aligned”,precise mask alignment is not needed!

35


Metallization completes device

p-

oxiden+ n+

Grow a thick oxide on topof the wafer.

p-

oxiden+ n+

Mask and etch to make contact holes

p-

oxiden+ n+

Put a layer of metal on chip.Be sure to fill in the holes!

36


Final product ...

Top-down view:

p-

oxiden+ n+

Vd Vs “The planar process”

Jean Hoerni,Fairchild Semiconductor1958

37


p-channel Transistors

38


p-Fet: Change polarity of everything

n-wellp+

Vwell = Vs = 1V

p+

Vd = 0Vdielectric

Vg = 0VI ⋲ µA

p-

New “n-well” mask

Vg

Vs

Vd

Isd

“Mobility” of holes is slowerthan electrons.

p-Fets drive less current than n-Fets, all else being equal

39


Device Equations

40


Recall: Our old “switch” model ...

A “on” p-FET fillsup the capacitor

with charge.

1/28/04 ©UCB Spring 2004CS152 / Kubiatowicz

Lec3.29

Delay Model:

CMOS


Lec3.30

Review: General C/L Cell Delay Model

° Combinational Cell (symbol) is fully specified by:• functional (input -> output) behavior

- truth-table, logic equation, VHDL

• load factor of each input

• critical propagation delay from each input to each output for each transition

- THL(A, o) = Fixed Internal Delay + Load-dependent-delay x load

° Linear model composes

Cout

Vout

Cout

Delay

Va -> Vout

XX

X

X

X

X

Ccritical

delay per unit load

A

B

X

.

.

.

Combinational

Logic Cell

Internal Delay


Lec3.31

Basic Technology: CMOS

° CMOS: Complementary Metal Oxide Semiconductor• NMOS (N-Type Metal Oxide Semiconductor) transistors

• PMOS (P-Type Metal Oxide Semiconductor) transistors

° NMOS Transistor• Apply a HIGH (Vdd) to its gate

turns the transistor into a “conductor”

• Apply a LOW (GND) to its gateshuts off the conduction path

° PMOS Transistor• Apply a HIGH (Vdd) to its gate

shuts off the conduction path

• Apply a LOW (GND) to its gateturns the transistor into a “conductor”

Vdd = 5V

GND = 0v

Vdd = 5V

GND = 0v


Lec3.32

Basic Components: CMOS Inverter

Vdd

Circuit

° Inverter Operation

OutIn

SymbolPMOS

NMOS

In Out

Vdd

Open

Charge

VoutVdd

Vdd

Out

Open

Discharge

Vin

Vdd

Vdd

A “on” n-FET empties the

bucket.


Lec3.29

Delay Model:

CMOS


Lec3.30

Review: General C/L Cell Delay Model

° Combinational Cell (symbol) is fully specified by:• functional (input -> output) behavior

- truth-table, logic equation, VHDL

• load factor of each input

• critical propagation delay from each input to each output for each transition

- THL(A, o) = Fixed Internal Delay + Load-dependent-delay x load

° Linear model composes

Cout

Vout

Cout

Delay

Va -> Vout

XX

X

X

X

X

Ccritical

delay per unit load

A

B

X

.

.

.

Combinational

Logic Cell

Internal Delay


Lec3.31

Basic Technology: CMOS

° CMOS: Complementary Metal Oxide Semiconductor• NMOS (N-Type Metal Oxide Semiconductor) transistors

• PMOS (P-Type Metal Oxide Semiconductor) transistors

° NMOS Transistor• Apply a HIGH (Vdd) to its gate

turns the transistor into a “conductor”

• Apply a LOW (GND) to its gateshuts off the conduction path

° PMOS Transistor• Apply a HIGH (Vdd) to its gate

shuts off the conduction path

• Apply a LOW (GND) to its gateturns the transistor into a “conductor”

Vdd = 5V

GND = 0v

Vdd = 5V

GND = 0v


Lec3.32

Basic Components: CMOS Inverter

Vdd

Circuit

° Inverter Operation

OutIn

SymbolPMOS

NMOS

In Out

Vdd

Open

Charge

VoutVdd

Vdd

Out

Open

Discharge

Vin

Vdd

Vdd

!"#$%&'())* ++,!-.)'/ 012-)34$5$%& 67&1'-)

!"#$%&'(#)*(+,%-$*".(/0

1 2+.$0#$03

1 4546%,"#$3

“1”

“0”Time

Water level

!"#$%&'())* ++,!-.)'/ 012-)34$5$%& 67&1'-)

!"#$%&'(#)*(+,%-$*".(/0

1 2+.$0#$03

1 4546%,"#$3

“0”

“1”

TimeWater level

We begin by modeling transistors that are “off”

41


Recall: Why diode current is I = exp(V) ...Wafer cross-section

n+

p-

Wafer doped p-type

n+ region

p- region At V = 0, “hill” too high for electrons to diffuse up.

V

Cathode: -

+

-

Anode: +

no carriers

depletion region

For holes, going “downhill” is hard. V controls hill.

electron

energy

depletion region

42


A simple model for “off” transistor ...

p-n+

Vd = 1V

n+

Vs = Vsub = 0Vdielectric

Vg = 0.2V

Vg

Vd

VsIds I ⋲ nA

n+ regionelectron

energy

n+ region

Current flows when electrons diffuse to the “gate wall” top

# electrons that reach top goes up as wall comesdown, implies Ids ~ exp(Vg)

Ids = Io [exp((κVg - Vs)/Vo)] [1 - exp(-Vds/Vo)]

Io ~100fA, Vo = kT/q = 25mV, κ = 0.7

Vg exponential dependence

⋲1 if Vds > 70mV

43


T.J. Watson Research Center

© 2004, 2005 IBM Corporation29 Pradip Bose| Hot Chips 2005 Tutorial August 14, 2005

Power-related issues in chip design

Temperature

Capacitive (Dynamic) Power Static (Leakage) Power

Minimum Voltage

20 cycles

Di/Dt (Vdd/Gnd Bounce)

Vo

lta

ge

(V

)C

urr

en

t (A

)

VOUT

CL ISub

VIN

IGate

Vin Vout

CL

Vdd

0V =

Sad fact of life: Leakage current

Even when a logic gate isn’t switching, it burns power.

Isub: Even when this nFet is off, it passes an Ioff leakage current.

We can engineer any Ioffwe like, but a lower Ioff also results in a lower Ion, and thus the lower the clock speed.

44


Data Plot: Transistor Off Current @ 25nm

I ds

Vs

Vd

V g I ds

Ioff ⋲ 10 nA

0.25 ⋲ Vt

1.2 mA = Ion

0.7 = Vdd

Ids = Io [exp((κVg - Vs)/Vo)] [1 - exp(-Vds/Vo)]

45


----------

p-n+

Vd = 2V

n+dielectric

Vg = 1V+++++++++----------

Simple model for “on” transistor ...

Vs = Vsub = 0VI ⋲ µA Vg

Vd

VsIds

Ids = (carriers in channel) / (transit time)Q = CV f(length, velocity)

Ids = [(µεW)/(LD)] [Vgs -Vth] [Vds]

If Vds > Vgs - Vth, channel physics change :

Ids = [(µεW)/(2LD)] [Vgs -Vth]^2 W = transistor width, L = length,

D = capacitor plate distance µ is velocity, ε is C dilectric constant

46


Data Plot: Transistor On Current @ 25nm

I ds

Vs

Vd

V g

0.7 = Vdd

0.25 ⋲ Vt

I ds

1.2 mA = Ion

Ioff = 0 ???

Ids = [(µεW)/(2LD)] [Vgs - Vth]^1.x

25nm is a small device! The simple model no longer captures how “on” device works.

47


Dynamic Memory (DRAM)

48


Recall: Capacitors in action

I = 0

Because the dielectric is an insulator, and does not conduct.

After circuit “settles” ...

Q = C V = C * 1.5 Volts (D cell)

Q: Charge stored on capacitorC: The capacitance of the device: function of device shape and type of dielectric.

+++ +++

--- ---

After battery is removed: +++ +++

--- ---Still, Q = C * 1.5 VoltsCapacitor “remembers” charge

1.5V

49


DRAM cell: 1 transistor, 1 capacitor

Vdd

Capacitor

“Word Line”“Bit Line”

p-

oxiden+ n+

oxide------

“Bit Line”

Word Line and Vdd run on “z-axis”

Word Line

Vdd

“Bit Line”

Vdd

Diode leakagecurrent.

Why Vcap values start out at ground.

Vcap

50


A 4 x 4 DRAM array (16 bits) ....

51


Invented after SRAM, by Robert Dennard

www.FreePatentsOnline.com



52


DRAM Circuit Challenge #1: Writing

Vdd

Vdd - Vth. Bad, we store less charge. Why do we not get Vdd?

VddVdd

Ids = [(µεW)/(2LD)] [Vgs -Vth]^2 , but “turns off” when Vgs <= Vth!

Vgs

Vc

Vgs = Vdd - Vc. When Vdd - Vc == Vth, charging effectively stops!

53


DRAM Challenge #2: Destructive Reads

Vdd

Bit Line

0 -> Vdd Vc -> 0

+++++++

+++++++ (stored charge from cell)

Word Line

Raising the word line removes the charge from every cell it connects too!

Must write back after each read.

Vgs

(initializedto a low voltage)

54


DRAM Circuit Challenge #3a: Sensing

Assume Ccell = 1 fF

Word line may have 2000 nFet drains,assume word line C of 100 fF, or 100*Ccell.

Ccell holds Q = Ccell*(Vdd-Vth)

dV = [Ccell*(Vdd-Vth)] / [100*Ccell]

dV = (Vdd-Vth) / 100 ⋲ tens of millivolts! In practice, scale array to get a 60mV signal.

When we dump this charge onto the word line, what voltage do we see?

Ccell100*Ccell

55


DRAM Circuit Challenge #3b: Sensing

Compare the word line against the voltage on a “dummy” world line.

How do we reliably sense a 60mV signal?

[...]

“Dummy” word line.Cells hold no charge.

?-+Word line to sense

Dummy word line

“sense amp”

56


DRAM Challenge #4: Leakage ...

Vdd

Bit Line+++++++

Word Line

p-

oxiden+ n+

oxide------

Parasitic currents leak away charge.

Diode leakage ...

Solution: “Refresh”, by reading cells at regular intervals (tens of milliseconds)

57


DRAM Challenge #5: Cosmic Rays ...

Vdd

Bit Line+++++++

Word Line

p-

oxiden+ n+

oxide------

Cosmic ray hit.

Solution: Store extra bits to detect and correct random bit flips (ECC).

Cell capacitor holds 25,000 electrons (or less). Cosmic rays that constantly bombard us can release the charge!

58


DRAM Challenge 6: Yield

Solution: add extra word lines (i.e. 80 when you only need 64). During testing, find the bad word lines, and use high current to burn away “fuses” put on chip to remove them.

If one bit is bad, do we throw chip away?

[...]

Extra word lines.Used for “sparing”.

59


Energy Storage and Process Scaling

66

65nm

300mm

Dual Core

Scaling: Scaling: The Fundamental Cost DriverThe Fundamental Cost Driver

90nm

300mm

130nm

200mm

180nm

200mm

250nm

200mm

350nm

200mm

OROR ==Twice theTwice the

circuitry in thecircuitry in the

same spacesame space

(architectural(architectural

innovation)innovation)

The sameThe same

circuitry in halfcircuitry in half

the spacethe space

(cost reduction)(cost reduction)

Half the die sizeHalf the die sizefor the samefor the same

capability thancapability thanin the priorin the prior

processprocess

Recall: Process Scaling (“Moore’s Law”)


1616

Process Advances Still Scale PowerProcess Advances Still Scale Power

but the rate has slowed and collaboration is requiredbut the rate has slowed and collaboration is required

.. 35!

m35!

m

.. 25!

m25!

m

.. 18!

m18!

m

.. 13!

m13!

m

90n

m90n

m

65n

m65n

m

45n

m45n

m

32n

m32n

m

CV

CV

22 S

calin

g S

calin

g

Due to reducing V and C (length and width of Cs decrease, but plate distance gets smaller).

Recent slope more shallow because V is being scaled less aggressively.

60


DRAM Challenge 7: Scaling

Each generation of IC technology, we shrink width and length of cell.

dV ⋲ 60 mV= [Ccell*(Vdd-Vth)] / [100*Ccell]

Solution: Constant Innovation of Cell Capacitors!

Problem 1: Number of arrays per chip grows!

As Ccell and drain capacitances scale together, number of bits per word line stays constant.

Problem 2: Vdd may need to scale down too!

61


Poly-diffusion Ccell is ancient history

Vdd

Capacitor

“Word Line”“Bit Line”

p-

oxiden+ n+

oxide------

“Bit Line”

Word Line and Vdd run on “z-axis”

Word Line

Vdd

“Bit Line”

62


Modern cells: “trench” capacitors

63


Modern cells: “stacked” capacitors

64


Memory Arrays

1128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc.

128Mb: x4, x8, x16SDRAM

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

32 Meg x 4 16 Meg x 8 8 Meg x 16Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banksRefresh Count 4K 4K 4KRow Addressing 4K (A0–A11) 4K (A0–A11) 4K (A0–A11)Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)Column Addressing 2K (A0–A9, A11) 1K (A0–A9) 512 (A0–A8)

SYNCHRONOUSDRAM

MT48LC32M4A2 – 8 Meg x 4 x 4 banksMT48LC16M8A2 – 4 Meg x 8 x 4 banksMT48LC8M16A2 – 2 Meg x 16 x 4 banks

For the latest data sheet, please refer to the Micron Website: www.micron.com/dramds

PIN ASSIGNMENT (Top View)

54-Pin TSOP

FEATURES• PC100-, and PC133-compliant• Fully synchronous; all signals registered on positive

edge of system clock• Internal pipelined operation; column address can be

changed every clock cycle• Internal banks for hiding row access/precharge• Programmable burst lengths: 1, 2, 4, 8, or full page• Auto Precharge, includes CONCURRENT AUTO

PRECHARGE, and Auto Refresh Modes• Self Refresh Mode; standard and low power• 64ms, 4,096-cycle refresh• LVTTL-compatible inputs and outputs• Single +3.3V ±0.3V power supply

OPTIONS MARKING• Configurations

32 Meg x 4 (8 Meg x 4 x 4 banks) 32M416 Meg x 8 (4 Meg x 8 x 4 banks) 16M8

8 Meg x 16 (2 Meg x 16 x 4 banks) 8M16• WRITE Recovery (tWR)

tWR = “2 CLK”1 A2• Package/Pinout

Plastic Package – OCPL2

54-pin TSOP II (400 mil) TG60-ball FBGA (8mm x 16mm) FB 3,6

60-ball FBGA (11mm x 13mm) FC 3,6

• Timing (Cycle Time)10ns @ CL = 2 (PC100) -8E 3,4,5

7.5ns @ CL = 3 (PC133) -757.5ns @ CL = 2 (PC133) -7E

• Self RefreshStandard NoneLow power L

• Operating Temperature RangeCommercial (0oC to +70oC) NoneIndustrial (-40oC to +85oC) IT 3

Part Number Example:

MT48LC16M8A2TG-7ENOTE: 1. Refer to Micron Technical Note: TN-48-05.

2. Off-center parting line.3. Consult Micron for availability.4. Not recommended for new designs.5. Shown for PC100 compatability.6. See page 59 for FBGA Device Marking Table.

VDD

DQ0VDDQDQ1DQ2VssQDQ3DQ4

VDDQDQ5DQ6VssQDQ7VDD

DQMLWE#CAS#RAS#

CS#BA0BA1A10A0A1A2A3

VDD

123456789101112131415161718192021222324252627

545352515049484746454443424140393837363534333231302928

VssDQ15VssQDQ14DQ13VDDQDQ12DQ11VssQDQ10DQ9VDDQDQ8VssNCDQMHCLKCKENCA11A9A8A7A6A5A4Vss

x8x16 x16x8 x4x4-

DQ0-

NCDQ1

- NC

DQ2-

NCDQ3

- NC-

NC- - - - - - - - - - - -

- NC-

NCDQ0

- NCNC-

NCDQ1

- NC-

NC- - - - - - - - - - - -

- DQ7- NCDQ6- NCDQ5- NCDQ4- NC- - DQM- - - - - - - - - - -

- NC- NCDQ3- NCNC- NCDQ2 - NC- - DQM- - - - - - - - - - -

Note: The # symbol indicates signal is active LOW. A dash (–)indicates x8 and x4 pin function is same as x16 pin function.

KEY TIMING PARAMETERS

SPEED CLOCK ACCESS TIME SETUP HOLDGRADE FREQUENCY CL = 2* CL = 3* TIME TIME

-7E 143 MHz – 5.4ns 1.5ns 0.8ns-7E 133 MHz 5.4ns – 1.5ns 0.8ns-75 133 MHz – 5.4ns 1.5ns 0.8ns

-8E 3,4,5 125 MHz – 6ns 2ns 1ns-75 100 MHz 6ns – 1.5ns 0.8ns

-8E 3 ,4,5 100 MHz 6ns – 2ns 1ns

*CL = CAS (READ) latency

65


Bit Line“Column”

“Word Line”“Row”

People buy

DRAM for the bits.“Edge” circuits

are overhead

So, we amortize the edge circuits over big arrays

66


4096 rows

2048 columns

33,554,432 usable bits(tester found good bits in bigger array)

1

of

4096

decoder

12-bitrow

address input

2048 bits delivered by sense amps

Select requested bits, send off the chip

A “bank” of 32 Mb (128Mb chip -> 4 banks)

67


Recall DRAM Challenge #3b: Sensing

Compare the word line against the voltage on a “dummy” world line.

How do we reliably sense a 60mV signal?

[...]

“Dummy” word line.Cells hold no charge.

?-+Word line to sense

Dummy word line

“sense amp”

68


4096 rows

1

of

4096

decoder

2048 columns


12-bitrow

address input



Corresponds to row read into sense ampsSlow! This 7.5ns period DRAM (133 MHz) can

do row reads at only 75 ns ( 13 MHz).Plus, need to add selection time.

DRAM has high latency to first bit out. A fact of life.

69


An ill-timed refresh may add to latency

Vdd

Bit Line+++++++

Word Line

p-

oxiden+ n+

oxide------

Parasitic currents leak away charge.

Diode leakage ...

Solution: “Refresh”, by reading cells at regular intervals (tens of milliseconds)

70


4096 rows

1

of

4096

decoder

2048 columns


12-bitrow

address input



Latency is not the same as bandwidth!What if we want all of the 2048 bits? In row access time (75 ns) we can do

10 transfers at 133 MHz. 8-bit chip bus -> 10 x 8 = 80 bits << 2048

Now the row access time looks fast!

Thus, push to faster DRAM

interfaces

71


4096 rows

1

of

4096

decoder

2048 columns


12-bitrow

address input



Sadly, it’s rarely this good ...What if we want all of the 2048 bits?

The “we” for a CPU would be the program running on the CPU.

It’s more likely that ... 20% of the memory accesses need a new row access ... not good.

72


DRAM latency/bandwidth chip featuresColumns: Design the right interfacefor CPUs to request the subset of a column of data it wishes:



Interleaving: Design the right interface to the 4 memory banks on the chip, soseveral row requests run in parallel.

Bank 1 Bank 2 Bank 3 Bank 4

73


Off-chip interface for the Micron part ...



Operating ModeThe normal operating mode is selected by setting M7

and M8 to zero; the other combinations of values for M7and M8 are reserved for future use and/or test modes.The programmed burst length applies to both READ andWRITE bursts.

Test modes and reserved states should not be usedbecause unknown operation or incompatibility with fu-ture versions may result.

Write Burst ModeWhen M9 = 0, the burst length programmed via

M0-M2 applies to both READ and WRITE bursts; whenM9 = 1, the programmed burst length applies toREAD bursts, but write accesses are single-location(nonburst) accesses.

CAS LatencyThe CAS latency is the delay, in clock cycles, between

the registration of a READ command and the availabilityof the first piece of output data. The latency can be set totwo or three clocks.

If a READ command is registered at clock edge n, andthe latency is m clocks, the data will be available by clockedge n + m. The DQs will start driving as a result of theclock edge one cycle earlier (n + m - 1), and provided thatthe relevant access times are met, the data will be valid byclock edge n + m. For example, assuming that the clockcycle time is such that all relevant access times are met,if a READ command is registered at T0 and the latency isprogrammed to two clocks, the DQs will start drivingafter T1 and the data will be valid by T2, as shown inFigure 2. Table 2 below indicates the operating frequen-cies at which each CAS latency setting can be used.

Reserved states should not be used as unknown op-eration or incompatibility with future versionsmay result.

Figure 2CAS Latency

CLK

DQ

T2T1 T3T0

CAS Latency = 3

LZ

DOUT

tOHt

COMMAND NOPREAD

tAC

NOP

T4

NOP

DON’T CARE

UNDEFINED

CLK

DQ

T2T1 T3T0

CAS Latency = 2

LZ

DOUT

tOHt

COMMAND NOPREAD

tAC

NOP

Table 2CAS LatencyALLOWABLE OPERATING

FREQUENCY (MHz)CAS CAS

SPEED LATENCY = 2 LATENCY = 3-7E ≤ 133 ≤ 143-75 ≤ 100 ≤ 133-8E ≤ 100 ≤ 125

Note! This example is best-case! To access a new row, a slow ACTIVE

command must run before the READ.

A clocked bus protocol

(133 MHz)

DRAM is controlled via commands

(READ, WRITE, REFRESH, ...)

Synchronous data output.

From Micron 128 Mb SDRAM data sheet (on “resources” web page)

(CAS = Column Address Strobe)

74


Opening a row before reading ...



ENABLE AUTO PRECHARGE

tCH

tCLtCK

tRPtRAS

tRCD CAS Latency

tRC

DQM / DQML, DQMH

CKE

CLK

A0-A9, A11

DQ

BA0, BA1

A10

tCMHtCMS

tAHtAS

tAHtAS

tAHtAS

ROW

ROW

BANK BANK

ROW

ROW

BANK

DON’T CARE

UNDEFINED

tHZ

tOH

DOUT m

tAC

COMMAND

tCMHtCMS

NOP3 READACTIVE NOP NOP3 ACTIVENOP

tCKHtCKS

COLUMN m2

T0 T1 T2 T4T3 T5 T6 T7 T8

NOP NOP

NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.2. x16: A9 and A11 = “Don’t Care”

x8: A11 = “Don’t Care”3. READ command not allowed else tRAS would be violated.

*CAS latency indicated in parentheses.

-7E -75 -8ESYMBOL* MIN MAX MIN MAX MIN MAX UNITStCMH 0.8 0.8 1 nstCMS 1.5 1.5 2 nstHZ(3) 5.4 5.4 6 nstHZ(2) 5.4 6 6 nstLZ 1 1 1 nstOH 3 3 3 nstRAS 37 120,000 44 120,000 50 120,000 nstRC 60 66 70 nstRCD 15 20 20 nstRP 15 20 20 ns

TIMING PARAMETERS

-7E -75 -8ESYMBOL* MIN MAX MIN MAX MIN MAX UNITStAC (3) 5.4 5.4 6 nstAC (2) 5.4 6 6 nstAH 0.8 0.8 1 nstAS 1.5 1.5 2 nstCH 2.5 2.5 3 nstCL 2.5 2.5 3 nstCK (3) 7 7.5 8 nstCK (2) 7.5 10 10 nstCKH 0.8 0.8 1 nstCKS 1.5 1.5 2 ns

SINGLE READ – WITH AUTO PRECHARGE 1

70 ns between row opens

44 ns

6 ns +

75


Interleave: Access all 4 banks in parallel



Figure 8Random READ Accesses

CLK

DQ

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,COL n

DOUT

nDOUT

aDOUT

xDOUT

m

READ

NOTE: Each READ command may be to any bank. DQM is LOW.

READ READ NOP

BANK,COL a

BANK,COL x

BANK,COL m

CLK

DQ DOUT

n

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,COL n

DOUT

aDOUT

xDOUT

m

READ READ READ NOP

BANK,COL a

BANK,COL x

BANK,COL m

CAS Latency = 2

CAS Latency = 3

DON’T CARE

76


ECC and DRAM

77


ECC: Memory in an imperfect world

ECC == Error Correcting Codes

Detecting and correcting RAM bit errors

78


DRAM Challenge: Cosmic Rays ...

Vdd

Bit Line+++++++

Word Line

p-

oxiden+ n+

oxide------

Cosmic ray hit.

Cell capacitor holds 25,000 electrons (or less). Cosmic rays that constantly bombard us can release the charge!

79


Practical effect of a cosmic ray ...

ADDIU R1, R0, 7SW R1, 100(R0)

Address 100: 0b00...0111

Address 100: 0b00...0011

Cosmic ray hit.

LW R1, 100(R0)

After LW, R1 holds 3 but it should hold 7.Bit flips on memory holding instructions are bad too!

80


To “detect” errors -- add ‘P’, a parity bit

Address 100: 0b00...0011 1

Cosmic ray hit.

Extra “parity” bit for every word. Not seen by software. Hardware computes it on every write, so that the number of 1’s in every 33 bit word is even (even parity).

On a read, count the number of 1s. If odd, a bit flipped.

Address 100: 0b00...0111 1

P

So, halt the program and reboot? Application may know if this bit matters, but there’s no API to ask it ...

Does this work if two bits flip? If three?

81


Error Correction: Hamming Codes ...

Richard Hamming.Computing pioneer.

Famous quote:

“Computers are not for numbers.

Computers are for understanding.”

82


Trick: Compute parity of subsets of bits

P₂P₁P₀

Add 3 parity bits.

???

Each parity bit computed on a subset of bits

P₀ = D₃ xor D₁ xor D₀ = 0 xor 1 xor 0 = 1 P₁ = D₃ xor D₂ xor D₀ = 0 xor 1 xor 0 = 1P₂ = D₃ xor D₂ xor D₁ = 0 xor 1 xor 1 = 0

0

Consider 4 bit words.

1 0 1D₃D₂D₁D₀

D₃D₂D₁P₂D₀P₁P₀

Use this word bit arrangement

0 11 0 0 1 1

“Just believe” for now, we will justify later ...

83


Case #1: No cosmic ray hitsD₃D₂D₁P₂D₀P₁P₀

On readout we compute:

P₀ xor D₃ xor D₁ xor D₀ = 1 xor 0 xor 1 xor 0 = 0 = C0

P₁ xor D₃ xor D₂ xor D₀ = 1 xor 0 xor 1 xor 0 = 0 = C1

P₂ xor D₃ xor D₂ xor D₁ = 0 xor 0 xor 1 xor 1 = 0 = C₂

0 11 0 0 1 1We write:

D₃D₂D₁P₂D₀P₁P₀0 11 0 0 1 1Later, we read:

If C₂C₁C₀ = 0

no errors

No errors ... but how do we know that?

These equations come from how we computed

P₀ = D₃ xor D₁ xor D₀ = 0 xor 1 xor 0 = 1 P₁ = D₃ xor D₂ xor D₀ = 0 xor 1 xor 0 = 1P₂ = D₃ xor D₂ xor D₁ = 0 xor 1 xor 1 = 0

P₂P₁P₀

84


Case #2: A cosmic ray hits ...

Cosmic ray hit D1. But how do we know that?

D₃D₂D₁P₂D₀P₁P₀0 11 0 0 1 1We write:


C₂C₁C₀ = b101 = 5

What does “5” mean?

0 01 0 0 1 1The position of the flipped bit!To repair, just flip it back ...

D₃D₂D₁P₂D₀P₁P₀14 36 57 2

Note: we number the least significant bit with 1, not 0! 0 is reserved for “no errors”.





85


Why did we choose “3” parity bits?

0

Consider 4 bit words.

P₂P₁P₀

Observation: The C₂C₁C₀ bits need to encode the “no error” condition, plus a number for

each bit (both data and parity bits)

Add 3 parity bits.

???1 0 1D₃D₂D₁D₀

For “p” parity bits and “d” data bits:

d + p + 1 <= 2p

A Ci inC₂C₁C₀ exists for each Pi.

86


Why did we arrange bits as we did?Consider 4 bit words.

P₂P₁P₀

Add 3 parity bits.

How do we re-arrange bits?

D₃D₂D₁D₀

Start by numbering, 1 to 7.

14 36 57 2


With this order, an odd parity means an error in 1,3,5, or 7.So, P0 is the right parity bit to use:C₂C₁C₀


An odd parity means a mistake must be in 2, 3, 6, or 7 -- the four numbers possible if C1 = 1!

D₃D₂D₁P₂D₀P₁P₀Etc ... each bit narrows down the suspect bits, until it is certain.


A Ci inC₂C₁C₀ exists for each Pi.

87


Consider 4 bit words.P₂P₁P₀Add 3 parity bits.

P₀ = D₃ xor D₁ xor D₀ P₁ = D₃ xor D₂ xor D₀ P₂ = D₃ xor D₂ xor D₁

D₃D₂D₁D₀

It takes 3 bit flips to move from one legal number to another (for all 16 numbers)

If only one bit flips, we can always figure out the “closest” legal number, and correct.

Why did we arrange bits as we did?

7 bits can code 128 numbers, but only 16 of these numbers are legal.


88


What if 2 cosmic rays hit?D₃D₂D₁P₂D₀P₁P₀0 11 0 0 1 1We write:


C₂C₁C₀ = b111 = 7

What does “7” mean?

0 01 0 0 1 1

“Correcting” this bit makes things worse! Thus, this code corrects “single” bits only.

D₃D₂D₁P₂D₀P₁P₀14 36 57 2Note: it does do 2-

bit “detect” (since C3 C2 C1 does not code 0), but it does not let us know that we can’t correct ...

Cosmic ray hit D1 and P1.





89


Next Monday:

This Friday: RAMP Gold Meeting, BWRC

Final Presentation

Fri, Dec 5 90

Documents

CS 194-6 Digital Systems Project Laboratory Lecture 7: DRAMcs194-6/fa08/lecnotes/lec7.pdfTo read C, measure V. V > 0.75 volts is a “1”. V < 0.75 volts is a “0”. Cost: