CS 150 - Spring 2008 – Lec #22 – Signaling - 1 State Machine Signaling zTiming Behavior yGlitches/hazards and how to avoid them zFSM Partitioning yWhat

CS 150 - Spring 2008 – Lec #22 – Signaling - 1

State Machine Signaling Timing Behavior

Glitches/hazards and how to avoid them

FSM Partitioning What to do when the state machine doesn’t fit!

State Machine Signaling Introducing Idle States (synchronous model) Four Cycle Signaling (asynchronous model)

Dealing with Asynchronous Inputs Metastability and synchronization


F is not always 0pulse 3 gate-delays wide

D remains high forthree gate delays after

A changes from low to high

FA B C D

Momentary Changes in Outputs Can be useful—pulse shaping circuits Can be a problem—incorrect circuit

operation (glitches/hazards) Example: pulse shaping circuit

A' • A = 0 delays matter

in function


initially undefined

close switch

open switch

+

open switch

resistor

A B

CD

Oscillatory Behavior

Another pulse shaping circuit


Hazards/Glitches Hazards/glitches: unwanted switching at the outputs

Occur when different paths through circuit have different propagation delays

As in pulse shaping circuits we just analyzed Dangerous if logic causes an action while output is unstable

May need to guarantee absence of glitches

Usual solutions1) Wait until signals are stable (by using a clock): preferable

(easiest to design when there is a clock – synchronous design)

2) Design hazard-free circuits: sometimes necessary (clock not used – asynchronous design)


10 0

1 10 0

1 10 0

01 1

Types of Hazards Static 1-hazard

Input change causes output to go from 1 to 0 to 1

Static 0-hazard Input change causes output to go from 0 to 1 to 0

Dynamic hazards Input change causes a double change

from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0


F

static-0 hazard static-1 hazard

A

B

S

S'

F

hazard

AS

B

S'

Static Hazards Due to a literal and its complement momentarily

taking on the same value Thru different paths with different delays and

reconverging

May cause an output that should have stayed at the same value to momentarily take on the wrong value

Example:


B2

A

C

B1

F

hazarddynamic hazards

B3

A

C

B

F

1

23

Dynamic Hazards Due to the same versions of a literal taking on

opposite values Thru different paths with different delays and

reconverging

May cause an output that was to change value to change 3 times instead of once

Example:


Eliminating Static Hazards Following 2-level logic function has a hazard, e.g.,

when inputs change from ABCD = 0101 to 1101A

AB 00 01 11 10

0 0 1 1

1 1 1 1

1 1 0 0

0 0 0 0

00

01

11

10 C

CD

D

B

G1

G2

G3

A\C

\AD

F

G1

G2

G3

A\C

\AD

F

1

1

1

1

0

0

0

1

1

1

1

0

0

0

ABCD = 1100 ABCD = 1101

No Glitch in this case

G1

G2

G3

A\C

\AD

F

G1

G2

G3

A\C

\AD

F

0

1

0

0

1

0

0

1

1

1

1

1

0

0

ABCD = 1101 ABCD = 0101 (A is still 0)

G1

G2

G3

A\C

\AD

F

0

1

0

1

1

1

1

ABCD = 0101 (A is 1)

Glitch in this case

This is the fix

1


Eliminating Dynamic Hazards Very difficult! A circuit that is static

hazard free can still have dynamic hazards

Best approach: Design critical

circuits to be two level and eliminate all static hazards

OR, use good clocked synchronous design style

G1

G2

G3

G5

G4

\A B

\B

\B \C

F

A

0 1

1

1 0

1

0 1

1 0

1 0 1

1 0 0

1 0

1 0 1 0

Slow

V ery slow


Hazard-Free Circuit Families

NORA, Domino, DCVS Use “evaluate” signal Every gate guaranteed to transition at most once

Very similar, we’ll consider Domino


Domino Basic Domino Gate

When Evaluation is LOW, Output is low

When Evaluation turns high, connection to power is off

If gate inputs are high, connection to ground is made and output (inverted) goes low to high

So: Gate output transitions at

MOST once, low to high Gate cannot glitch

GateLogic

Evaluation

Output

Ground

Power


Domino: Plusses and Minusses Plus

Cannot glitch Timing analysis (false path

analysis) very simple Safe to connect Domino

gates together

Minus Non-inverting logic only Not functionally complete Use inverters on the circuit

outputs and inputs to complete

Glitches on inputs cause gate to fail

Ensure circuit inputs are stable when evaluation is high

Charge leaks away if Evaluation stays on too longHow to do the Evaluation signal?


DOMINO AND Gate

Evaluation

Output

Ground

Power

A

B

F

Evaluation

A

B

F

Output


DOMINO AND Gate

Evaluation

Output

Ground

Power

A

B

F

Evaluation

A

B

F

Output


DOMINO AND Gate

Evaluation

Output

Ground

Power

A

B

F

Evaluation

A

B

F

Output


DOMINO AND Gate

Evaluation

Output

Ground

Power

A

B

F

Evaluation

A

B

F

Output


Using Domino in a Larger Circuit safely

Domino CircuitClocked by Evaluation

Latch bank stable when Evaluation = 1

Latch bank active when Evaluation = 1


Key to Safe Operation

Inputs glitch/hazard free Guaranteed by latch discipline

Foreach gate: Inputs hazard-free => outputs hazard-free

By induction: Every node in circuit is hazard-free


Differential Cascode Voltage Switch Two Domino Gates back-to-

back

One realizes A, the other A’ Achieve by dualizing

pulldown trees Note A, A’ therefore

available for every DCVS output

Clever tricks can let one combine the pulldowns

Use BDDs!

Evaluation’

notA = notC or notD

Ground

Power

notC

notD

Evaluation’

A = C and D

Ground

Power

C

D


Nice properties of DCVS

Exactly one of A, notA will transition to high during evaluation

At most twice the size of DOMINO, static circuit (often less)

A XOR notA = 1 for every circuit output A is completion signal Can use this to clock latches

Nice building block for unclocked circuits

Still has charge leakage problem

All other positive properties of Domino remain


Domino In Static Logic

Key elements of Domino Noninverting logic only All nodes evaluate to 0 when eval = 0 (or 1) Inputs change at most once, low to high

Problem Leakage due to finite capacitance Need access to transistor-level design

Question: Can we build DOMINO (also DCVS) using only static logic?


Yes!

Key element of Domino: evaluate only once

All elements have one of two state changes Low->high Low->low (no change)

State change high->low forbidden

Let’s achieve that in full-static


Static Domino AND Gate To form A & B

A NAND B NOR the result with a new

signal, Evaluation’

Evaluation is high when circuit is evaluated

Evaluation is low => evaluation’ is high output is 0

Evaluation is high, Evaluation’ is low, NOR gate becomes an inverter

Output is A & B

A

AB

B

Evaluation’


Static DOMINO AND Gate

Evaluation

A

B

F

Output

AB

Evaluation’


DOMINO AND Gate (Example)

Evaluation

A

B

F

Output

AB

Evaluation’


DOMINO AND Gate

Evaluation

A

B

F

OutputAB

Evaluation’


Domino and Static Domino Domino

Glitch-free when inputs and evaluation glitch-free

Non-inverting logic only Requires transistor-level

design Incorrect when inputs

glitch Fast since pull-ups inactive

during evaluation

Static Domino Glitch-free when inputs

and evaluation glitch-free Non-inverting logic only Use with any design style Correct when inputs glitch

(but not glitch-free) Slow since double gate-

delay

Key: Evaluation line must be glitch-free


FSM Partitioning Why Partition?

What if programmable logic is limited in number of inputs and outputs that can be used in a particular device?

For PLAs, the number of product terms are limited, thus limiting the complexity of the next state and output functions


Partitioning the State Machine Suppose that FSM is

partitioned so that states at the right are in one partition and states at the left are in the other

How do you support intersignaling between the state machine partitions?

It is usually a good idea to partition the machine so there are as few cross links as possible (min cut set in graph theoretic terms)


Partitioning the State Machine Solution: introduce idle states SA and SB

Machine at left enters SA allowing machine at right to exit SB

When machine at right returns to SB, machine at left exits SA


Rules for Introducing Idle States


Example: Partitioning the Up/Down Counter


Example Partitioning: Traffic Light Controller Main Controller vs. Counter/Timer

ST triggers transfer of control TS or TL triggers return of

control

Reset

TS'

TS / ST

(TL•C)'

TL•C / ST

TS'

TS / ST

(TL+C')'

TL+C' / ST

HG

FG

FYHY

T00

T01

T02

T03

T04[TS]

T05

T09

T08

T07

T06

T10

T11

T12

T13

T19[TL]

T18

T17

T16

T15

T14

ST

(a) Main controller(b) Counter/timer


Partitioned FSM Block Diagram

Interface between the two partitions are the signals ST, TS, TL

NOTE: Main Controller and Timer use the same clock and are operating in a synchronous mode

traffic light controller

timer

TLTSST

resetC

HRHYHGFRFYFG


Generalized Inter-FSM Signaling Interlocked Synchronized Signaling


Asynchronous Signaling

Also known as “speed-independent” signaling Requester/client/master vs. Provider/Server/Slave

Communications Signals Clocked

SubsystemClocked

Subsystem

S1

requester client master

S2

provider server slave

Request

Data Flow

Acknowledgement


Asynchronous Signaling First consider the common clock case (synchronous)

Master asserts Request Slave recognizes request, processes request, indicates

completion by asserting Acknowledgement Master accepts results, removes Request Slave see Request removed, removes Acknowledge

Req

Data

Ack

Clk


Asynchronous Signaling What if Slave can’t respond in single cycle? Solution: Wait

signaling

Slave inhibits master by asserting wait

When slave unasserts wait, master knows request has been processed, and can latch results

Req

Data

W ait

Clk


Req

Data

Ack

True Asynchronous Signaling Now remove the assumption of a single common clock How do we make sure that receiver has seen the sender’s

signal? Solution: Interlocked signaling Four cycle signaling: assert Req, process request, assert

ack, latch result, remove Req, remove Ack and start again Sometimes called “Return to Zero” signaling

1

2

3

4


True Asynchronous Signaling

Alternative scheme: Two-Cycle Signaling Non-return-to-zero signaling Transaction start by Req lo-to-hi, finishes Ack lo-to-hi Next transaction starts by Req hi-to-lo, finishes Ack hi-to-

lo Requires EXTRA state to keep track of the current sense

of the transitions—faster than 4 cycle case, but usually involves more hardware

Ack

Data

Req 1

2

1

2


True Asynchronous Timing Self-Timed Circuits

Uses Req/Ack signaling as described

Components can be constructed with NO internal clocks

Determines on its own when the request has been processed

Concept of the delay line simply slows down the pass through of the Req to the Ack—usually matched to the worst case delay path

Becoming MORE important for large scale VLSI chips were global clock distribution is a challenge

Input

Req

Output

Ack

Combinational logic

Delay


Metastability and Asynchronous inputs Clocked synchronous circuits

Inputs, state, and outputs sampled or changed in relation to acommon reference signal (called the clock)

E.g., master/slave, edge-triggered

Asynchronous circuits Inputs, state, and outputs sampled or changed independently

of a common reference signal (glitches/hazards a major concern)

E.g., R-S latch

Asynchronous inputs to synchronous circuits Inputs can change at any time, will not meet setup/hold times Dangerous, synchronous inputs are greatly preferred Cannot be avoided (e.g., reset signal, memory wait, user input)


small, but non-zero probability that the FF output will get stuck

in an in-between state

oscilloscope traces demonstratingsynchronizer failure and eventual

decay to steady state

logic 0 logic 1logic 0

logic 1

Synchronization Failure Occurs when FF input changes close to clock edge

FF may enter a metastable state – neither a logic 0 nor 1 – May stay in this state an indefinite amount of time Is not likely in practice but has some probability


D DQ Qasynchronous

inputsynchronized

input

synchronous system

Clk

Dealing with Synchronization Failure Probability of failure can never be reduced to 0,

but it can be reduced(1) slow down the system clock: this gives the

synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems

(2) use fastest possible logic technology in the synchronizer:this makes for a very sharp "peak" upon which to balance

(3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail)


D Q

D Q

Q0

Clock

Clock

Q1

Async Input

D Q

D Q

Q0

Clock

Clock

Q1

Async Input D Q

Clocked Synchronous

System

Synchronizer

Handling Asynchronous Inputs Never allow asynchronous inputs to fan-out to

more than one flip-flop Synchronize as soon as possible and then treat as

synchronous signal


In is asynchronous and fans out to D0 and D1

one FF catches the signal, one does not

inconsistent state may be reached!

In

Q0

Q1

CLK

Handling Asynchronous Inputs (cont’d)

What can go wrong? Input changes too close to clock edge (violating setup

time constraint)


Signaling Summary Glitches/Hazards

Introduce redundant logic terms to avoid them OR use synchronous design!

FSM Partitioning Replacing monolithic State Machine with simpler

communicating state machine Technique of introducing idle states

Machine-to-machine Signaling Synchronous vs. asynchronous Four vs. Two Cycle Signaling

Asynchronous inputs and their dangers Synchronizer failure: what it is and how to minimize its impact

Documents

CS 150 - Spring 2008 – Lec #22 – Signaling - 1 State Machine Signaling zTiming Behavior yGlitches/hazards and how to avoid them zFSM Partitioning yWhat