CS 121Digital Logic

Design

Gate-Level Minimization

Chapter 3

Outline3.1 Introduction3.2 The Map Method3.3 Four-Variable Map3.4 Product of sums simplification3.5 Don‘t Care Conditions3.7 NAND and NOR Implementaion3.8 Other Two-Level Implementaion3.9 Exclusive-OR function

3.7 NAND and NOR Implementation (1-15)

Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR gates.

3.7 NAND and NOR Implementation (2-15)

NAND gate: a universal gate. Any digital system can be implemented

with it.

NAND Implementation

3.7 NAND and NOR Implementation (3-15)

To facilitate the conversion to NAND logic, there are alternative graphic symbol for it.

NAND Implementation

3.7 NAND and NOR Implementation (4-15)

Procedures of Implementation with two levels of NAND gates:

1. Express simplified function in sum of products form.2. Draw a NAND gate for each product term that has

at least two literals to constitute a group of first-level gates

3. Draw a single gate using AND-invert or invert-OR in the second level

4. A term with a single literal requires an inverter in the first level.

NAND ImplementationTwo-Level Implementation

3.7 NAND and NOR Implementation (5-15)

NAND ImplementationTwo-Level Implementation

F = AB + CD

([ =AB + CD’]’)

([ =AB(*’)CD’]’)

3.7 NAND and NOR Implementation (6-15)

NAND ImplementationTwo-Level ImplementationExample (3.10):F(X,Y,Z) = ∑ (1,2,3,4,5,7)

y zx

1

00 01 11 1001 1

1 1

Z

X’Y

1

1

XY’

F = XY’ + X’Y + Z

3.7 NAND and NOR Implementation (7-15)

Procedures of Implementation with multilevel of NAND gates:

1. Convert all AND gates to NAND gates with AND-invert graphic symbols

2. Convert all OR gates to NAND gates with invert-OR graphic symbols

3. Check all the bubbles in the diagrams. For a single bubble, invert aninverter (one-input NAND gate) or complement the input literal

NAND ImplementationMultilevel Implementation

3.7 NAND and NOR Implementation (8-15)

NAND ImplementationMultilevel Implementation

EXAMPLE 1:F = A(CD + B) + BC’

3.7 NAND and NOR Implementation (9-15)

NAND ImplementationMultilevel ImplementationEXAMPLE 2:F = (AB’ + A’B).(C + D’)

3.7 NAND and NOR Implementation (10-15)

The NOR operation is the dual of the NAND operation. The NOR gate is anothar universal gate to

implement any Boolean function.

NOR Implementation

3.7 NAND and NOR Implementation (11-15)

To facilitate the conversion to NOR logic, there are alternative graphic symbol for it.

NOR Implementation

3.7 NAND and NOR Implementation (12-15)

Procedures of Implementation with two levels of NOR gates:

1. Express simplified function in product of sums form.2. Draw a NOR gate for each product term that has at

least two literals to constitute a group of first-level gates

3. Draw a single gate using OR-invert or invert-AND in the second level

4. A term with a single literal requires an inverter in the first level.

NOR Implementation

Two-Level Implementation

3.7 NAND and NOR Implementation (13-15)

NOR ImplementationTwo-Level ImplementationExample :F = (A+B).(C+D).E

E

3.7 NAND and NOR Implementation (14-15)

Procedures of Implementation with multilevel of NOR gates:

1. Convert all OR gates to NOR gates with OR-invert graphic symbols

2. Convert all AND gates to NOR gates with invert-AND graphic symbols

3. Check all the bubbles in the diagrams. For a single bubble, invert aninverter (one-input NAND gate) or complement the input literal

NOR Implementation

Multilevel Implementation

3.7 NAND and NOR Implementation (15-15)

NOR ImplementationMulti-Level ImplementationExample :F = (A B’ + A’B).(C+D’)

A

B’

A’

B

3.9 Exclusive-OR Function (1-7)

Exclusive-OR (XOR) denoted by the symbol : x y = xy‘ + x‘y Exclusive-OR is equal to 1, when the values of x and y are

diffrent. Exclusive-NOR (XNOR): (x y )‘ = xy + x‘y‘ Exclusive-NOR is equal to 1, when the values of x and y

are same.

Only a limited number of Boolean functions can be expressed in terms of XOR operations, but it is particularly useful in arithmetic operations and error-detection and correction circuits.

3.9 Exclusive-OR Function (2-7)

Exclusive-OR principles: x 0 = x x 1 = x‘ x x = 0 x x‘ = 1 x y‘ = x‘ y = (x y)‘ x y = y x (x y) z = x (y z)

3.9 Exclusive-OR Function (3-7)

Implementaion Exclusive-OR with AND-OR-NOT:

x y = xy‘ + x‘y Implementaion

Exclusive-OR with NAND: x y = xy‘ + x‘y = x (x‘+y‘) + y (x‘+y‘) = x (xy)‘ + y (xy)‘ = [ (x(xy)‘ + y(xy)‘)‘]‘ = [ (x(xy)‘)‘ + (y(xy)‘)‘ ]‘

3.9 Exclusive-OR Function (4-7)

The 3-variable XOR function is equal to 1 if only one variable is equal to 1 or if all three variables are equal to 1.

Multiple-variable exclusive OR operation = odd function : odd number of variables be equal to 1.

(A B C) = (AB‘ + A‘B) C‘ + (A‘B‘ + AB) C = AB‘C‘ + A‘BC‘ + A‘B‘C + ABC = ∑ (1,2,4,7)

Odd Function:

3.9 Exclusive-OR Function (5-7)

Odd Function:

3.9 Exclusive-OR Function (6-7)

Odd Function:A B C D= ∑ (1,2,4,7,8,11,13,14)

3.9 Exclusive-OR Function (7-7)

Exclusive-OR function is useful in systems requiring error-detection and correction circuits.

A parity bit is used for purpose of detection errors during transmission.

Parity bit : an extra bit included with a binary message to make the number of 1’s either odd or even.

The circuit generates the parity bit in transmitter is called parity generator.

The circuit checks the parity bit in receiver is called parity checker.

Parity Generation and Checking:

3.9 Exclusive-OR Function (8-7)

Parity Generation and Checking:Example : Three-bit message with even parityThree-bit Massage Parity

bitX Y Z P0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 11 0 1 01 1 0 01 1 1 1

o From the truth table , P constitutes an odd function.

o It is equal 1 when numerical value of 1’s in a minterm is odd

o P = x y z

3.9 Exclusive-OR Function (8-7)

Parity Generation and Checking:Example : Three-bit message with even parity

o From the truth table , C constitutes an odd function.

o It is equal 1 when numerical value of 1’s in a minterm is odd

o C = x y z P

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FIGURE 4-25 XOR gates used to implement the parity generator and the parity checker for an even-parity system.

Parity Generation and Checking

11/3/2013