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EVIEW

Copyright copy 2011 American Scientific PublishersAll rights reservedPrinted in the United States of America

Science ofAdvanced Materials

Vol 3 322ndash331 2011

CrossNets Neuromorphic HybridCMOSNanoelectronic Networks

Konstantin K LikharevDepartment of Physics and Astronomy Stony Brook University Stony Brook NY 11794-3800 USA

Hybrid CMOSnanoelectronic circuits combining CMOS chips with simple nanoelectronic crossbaradd-ons may extend the exponential Moore-Law progress of microelectronics beyond the 10-nmfrontier This paper reviews the development of neuromorphic networks (ldquoCrossNetsrdquo) based onthis prospective technology In these networks the neural cell bodies (ldquosomasrdquo) are implementedin the CMOS subsystem crossbar nanowires are used as axons and dendrites while two-terminalcrosspoint devices are used as elementary synapses Extensive analysis and simulations haveshown that such networks may perform virtually all information processing tasks demonstratedwith software-implemented neural networks with much higher performance Estimates show thatCrossNets may eventually overcome bio-cortical circuits in density at comparable connectivity whileoperating 4 to 6 orders of magnitude faster at manageable power dissipation

Keywords Nanoelectronics Hybrid Circuits Crossbar Latching Switches Memristive DevicesNeuromorphic Circuits Neural Networks Plasticity Adaptation Cognitive Tasks

CONTENTS

1 Introduction CMOLNanoelectronic Hybrids 3222 Topologies 3233 Performance Estimates 3254 Synaptic Weight SettingAdaptationPlasticity 326

41 Weight Import 32642 In-Situ Adaptation Firing-Rate Models 32643 In-Situ Adaptation STDP 326

5 Application Examples 32851 Hopfield Networks Pattern Recognition 32852 Multilayer Perceptrons Pattern Classification 32953 Global Reinforcement and TD Learning 329

6 Prospects Challenges and Options 329Acknowledgments 330References and Notes 330

1 INTRODUCTION CMOLNANOELECTRONIC HYBRIDS

Recent research has shown that the impending crisis ofthe exponential (ldquoMoorersquos-Lawrdquo) progress of microelec-tronics may be postponed for more than a decade bythe transfer from purely CMOS technology to hybridCMOSnanodevice circuits1ndash4 In such a circuit a speciallydesigned CMOS chip is complemented with a simple nano-electronic add-on a nanowire crossbar with simple simi-lar two-terminal nanodevices at each crosspoint (Fig 1)Two types on two-terminal nanodevices are being exploredfor use in the hybrids ldquolatching switchesrdquo (sometimes

called ldquoresistive switchesrdquo or ldquoprogrammable diodesrdquo)with resistive bistability shown schematically in Figure 2and ldquomemristiverdquo devices whose parameters includingeffective resistance depend gradually of their operationhistorya Effective connection between the CMOS sub-system and the crossbar subsystem may be provided byan area-distributed interface Figure 3 shows the so-calledldquoCMOLrdquo version of such interface1ndash4 b which allows theCMOS subsystem to address every nanowire and henceevery crosspoint device of the add-on crossbarc The basicidea behind such CMOSnanoelectronic hybrids is thatnanowire levels of the crossbar do not need alignment(ldquooverlayrdquo)58 and hence may be fabricated using advancedpatterning methods such as nanoimprint9ndash11 EUV interfer-ence lithography12ndash14 or block-copolymer lithography1516

for whom the nanoscale-accurate overlay is not availableAs a result the crossbar half-pitch Fnano may be muchsmaller than that (FCMOS) of the CMOS subsystemDetailed simulations have shown that for the ratio

FCMOSFnano sim10 which may be anticipated by the end

aThis author prefers to refer the currently popular term ldquomemristorrdquo tothe original theoretical concept by Chua5 from which the experimentallydemonstrated memristive devices differ rather substantially

bIndependently a similar idea has been suggested by Cerofolini andRomano6

cA prototype of a simplified version of the CMOL interface calledFPNI has already been demonstrated experimentally7

322 Sci Adv Mater 2011 Vol 3 No 3 1947-293520113322010 doi101166sam20111177

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REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

(a)

(b)

Bottom nanowire level

Top nanowire level

Similar two-terminalnanodevices at each

cross point

Nanoelectronicadd-on

CMOS stack

MOSFET

Fig 1 Hybrid CMOSnanoelectronic circuit (a) the general topologyand (b) the nanoelectronic crossbar add-on (schematically)

of this decade23 the CMOSnano hybrids with CMOSinterface may provide a nearly two-orders-of magnitudeadvantage over pure CMOS (with the same FCMOS andpower per unit area and comparable speed) for at least twodigital applications resistive memories24 and FPGA-likereconfigurable logic circuits25ndash26 This advantage aloneequivalent crudely to 10 to 15 years of Moorersquos Law exten-sion may be a sufficient motivation for the industrial intro-duction of the hybridsThe goal of this paper is to review another area of pos-

sible applications of such hybrids in integrated circuitsof another type bio-inspired neuromorphic networksmdashldquoCrossNetsrdquo 2ndash527ndash35 whose estimated performance overCMOS circuits with similar functionally is even muchhigher up to 6 orders of magnitude The review starts witha description (in Section 2) of the basic idea and topol-ogy of CrossNets followed by their performance estimates(Section 3) Section 4 reviews the developed methods for

Konstantin K Likharev received the Candidate (PhD) degree in Physics from theLomonosov Moscow State University Russia in 1969 and the habilitation degree of Doc-tor of Sciences from the Higher Attestation Committee of the USSR in 1979 From1969 to 1988 Dr Likharev was a Staff Scientist of Moscow State University and from1989 to 1991 the Head of the Laboratory of Cryoelectronics of that university In 1991 heassumed a Professorship at Stony Brook University (Distinguished Professor since 2002)During his research career Dr Likharev worked in the fields of nonlinear classical anddissipative quantum dynamics and solid-state physics and electronics notably includingsuperconductor electronics and nanoelectronics He is an author of more than 250 origi-nal publications 75 review papers and book chapters 2 monographs and several patentsDr Likharev is a Fellow of the APS and IEEE More detailed information is available onlineat httprsfq1physicssunysbedu likharevpersonal

V

I ON state

ON state

OFF rarr ONswitching

ON rarr OFFswitching

0

V+

OFF state

VtVtprime

Vndash

Fig 2 The IndashV curve of a latching switch (schematically) The devicemay be switched from OFF state to ON state and back by applying suf-ficiently high voltages V gt Vt and V lt V prime

t respectively Such deviceshave been implemented using a broad range of materials (for reviewssee Refs [51718]) some of them with acceptable device-to-devicereproducibility19ndash22

the import andor runtime adaptation of their synapticweights (which for neural computation play the role ofprogramming at usual computing) Several examples oftasks which may be performed by CrossNets are describedin Section 5 while the concluding Section 6 discussesprospects of their practical applications and major chal-lenges to be met on the way towards their practicalintroduction

2 TOPOLOGIES

Figure 4 shows the generic geometry of CrossNets Neu-ral cell bodies (somas) are implemented in the CMOSsubsystem For the simplest firing-rate models of neuralnetworks36ndash38 the soma may be just an analog ampli-fier with saturation while in more bio-plausible ldquospikingrdquomodels the somatic circuit receives processes and gener-ates its own nerve pulses (ldquospikesrdquo)Output signal voltage Vk (t) of a soma is applied

through an area-distributed interface (Fig 3) to twoldquoaxonicrdquo nanowires in Figure 4 shown with red lines Per-pendicular physically similar ldquodendriticrdquo nanowires of thecrossbar (blue lines) lead to inputs of other somas If thetwo-terminal device at the crosspoint of k-th axon and j-th

Sci Adv Mater 3 322ndash331 2011 323

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IP 1294956157Sat 02 Jul 2011 132733

REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

(a)

(b)

Bottom nanowire level

Top nanowire level

Similar two-terminalnanodevices at each

cross point

Nanoelectronicadd-on

CMOS stack

MOSFET

Fig 1 Hybrid CMOSnanoelectronic circuit (a) the general topologyand (b) the nanoelectronic crossbar add-on (schematically)

of this decade23 the CMOSnano hybrids with CMOSinterface may provide a nearly two-orders-of magnitudeadvantage over pure CMOS (with the same FCMOS andpower per unit area and comparable speed) for at least twodigital applications resistive memories24 and FPGA-likereconfigurable logic circuits25ndash26 This advantage aloneequivalent crudely to 10 to 15 years of Moorersquos Law exten-sion may be a sufficient motivation for the industrial intro-duction of the hybridsThe goal of this paper is to review another area of pos-

sible applications of such hybrids in integrated circuitsof another type bio-inspired neuromorphic networksmdashldquoCrossNetsrdquo 2ndash527ndash35 whose estimated performance overCMOS circuits with similar functionally is even muchhigher up to 6 orders of magnitude The review starts witha description (in Section 2) of the basic idea and topol-ogy of CrossNets followed by their performance estimates(Section 3) Section 4 reviews the developed methods for

Konstantin K Likharev received the Candidate (PhD) degree in Physics from theLomonosov Moscow State University Russia in 1969 and the habilitation degree of Doc-tor of Sciences from the Higher Attestation Committee of the USSR in 1979 From1969 to 1988 Dr Likharev was a Staff Scientist of Moscow State University and from1989 to 1991 the Head of the Laboratory of Cryoelectronics of that university In 1991 heassumed a Professorship at Stony Brook University (Distinguished Professor since 2002)During his research career Dr Likharev worked in the fields of nonlinear classical anddissipative quantum dynamics and solid-state physics and electronics notably includingsuperconductor electronics and nanoelectronics He is an author of more than 250 origi-nal publications 75 review papers and book chapters 2 monographs and several patentsDr Likharev is a Fellow of the APS and IEEE More detailed information is available onlineat httprsfq1physicssunysbedu likharevpersonal

V

I ON state

ON state

OFF rarr ONswitching

ON rarr OFFswitching

0

V+

OFF state

VtVtprime

Vndash

Fig 2 The IndashV curve of a latching switch (schematically) The devicemay be switched from OFF state to ON state and back by applying suf-ficiently high voltages V gt Vt and V lt V prime

t respectively Such deviceshave been implemented using a broad range of materials (for reviewssee Refs [51718]) some of them with acceptable device-to-devicereproducibility19ndash22

the import andor runtime adaptation of their synapticweights (which for neural computation play the role ofprogramming at usual computing) Several examples oftasks which may be performed by CrossNets are describedin Section 5 while the concluding Section 6 discussesprospects of their practical applications and major chal-lenges to be met on the way towards their practicalintroduction

2 TOPOLOGIES

Figure 4 shows the generic geometry of CrossNets Neu-ral cell bodies (somas) are implemented in the CMOSsubsystem For the simplest firing-rate models of neuralnetworks36ndash38 the soma may be just an analog ampli-fier with saturation while in more bio-plausible ldquospikingrdquomodels the somatic circuit receives processes and gener-ates its own nerve pulses (ldquospikesrdquo)Output signal voltage Vk (t) of a soma is applied

through an area-distributed interface (Fig 3) to twoldquoaxonicrdquo nanowires in Figure 4 shown with red lines Per-pendicular physically similar ldquodendriticrdquo nanowires of thecrossbar (blue lines) lead to inputs of other somas If thetwo-terminal device at the crosspoint of k-th axon and j-th

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EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Crosspoint

CMOS

Nanowire

Interface pins

α

2rFnano2βFCMOS

2Fnano

(a)

(b)

Fig 3 CMOL interface between the CMOS subsystem and nanowirecrossbar (a) side view and (b) top view (schematically) The specificangle = arctan (1r where r asymp FCMOSFnano is an integer of the tiltbetween the square mesh of interface pins and the crossbar allows theCMOS system to address every nanowire of the crossbar and hence everycrosspoint device individually

Soma k

Soma j

wjk

wjk

+

ndash

Fig 4 Topology of the simplest (feedforward binary-weight) Cross-Net Red lines show ldquoaxonicrdquo and blue lines physically similar ldquoden-driticrdquo nanowires Gray squares show positions of two CMOS-basedsomatic circuits with their interfaces with the nanowire crossbar shownin darker gray Green circles denote latching switches forming elementarysynapses (For clarity only those of them responsible for signal transferbetween two somas k and j are shown) Nanowire open-circuit termina-tions (shown without solid dots) do nor allow somas to communicate inbypass of synapses

dendrite is in its ON state (Fig 2) this voltage provides asubstantial contribution to the current injection Ij into j-thdendritic wire so that in the linear approximation and lowinput load the total current is

Ijt=Msumk=1

sumsj=plusmn1

sjGjkVkt (1)

where Gjk is the crosspoint device conductance and sj =plusmn1 is the input polarity Equation (1) is exactly the keyaddndashmultiply operation pertinent to any artificial neuralnetwork (with the product sjGjk playing the role of thesynaptic weight wjk which consumes most computingresources at the network implementation in software runon general-purpose digital computers In CrossNets this isan analog operation which may be extremely fastmdashsee thenext section

Fig 5 Signal forwarding in two CrossNet species (a) FlossBar withconnectivity M = 10 and (b) InBar with M = 9 For clarity only thenanowires and nanodevices coupling one pre-synaptic cell (indicated withred dashed lines) to M post-synaptic cells (blue dashed lines) are shownactually all other cells are similarly coupled

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REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

Vj

i = 1

2

hellip

RS RL

Vj

i prime = 1 hellip n 2

Fig 6 Composite synapse providing L = n2 + 1 discrete weight lev-els Dark-gray rectangles are resistive metallic strips at somenanowireinterfaces

Perhaps the most important feature of CrossNets is thattheir connectivity M (the upper limit in the sum in Eq (1)ie the number of cells providing signal to any given oneldquodirectlyrdquo (via a synaptic contact) depends only on thedistance between the somas and theoretically is unlimiteddespite the quasi-2D geometry of these circuits This isvery important for modeling of (and eventually competingwith) bio-cortical circuits whose average connectivity isclose to 10439

Besides the intercell distance (and hence the connectiv-ity) CrossNet properties depend on the cell distributionover the synaptic field Figure 5 shows the feedforwardversions of two CrossNet types most explored so far theso-called FlossBar and InBar28 The former network ismore natural for the implementation of multilayered per-ceptrons (MLP see Section 52) while the latter systemmay be preferable for recurrent network implementations(Section 51)The generic topologies shown in Figures 4ndash5 may be

readily extended to more advanced neuromorphic net-works For example flexible combinations of FlossBarand InBar plaquettes are straightforward to engineer55

Also if the used crosspoint devices are bistable (Fig 2)ie if a single device provides binary synaptic weightsynapses with multi-level weights may be organized fromsmall arrays of such bistable switches (Fig 6) two com-plementary square arrays of ntimes n switches each pro-vide L= 2n2+1 discrete weight levels with L= 33 (ien= 4) being sufficient for some key algorithms32

3 PERFORMANCE ESTIMATES

The most important motivation for the architecturedevelopment quantitative simulation (and eventually

hardware implementation) of CMOL CrossNets comesfrom estimates of their possible density speed and powerIn CMOL topology the total area occupied by synapsesserving one cell is close to

Aasymp 4 MLF 2nano (2)

At reasonable connectivity (M gt 102 and weight leveldiscreteness (Lge 33) this area is more than sufficient forthe layout of even the most complex (say spiking) somaticcircuitry so that CrossNet density may be estimated fromEq (2) For such realistic numbers as L= 33 M = 3times103and Fnano = 5 nm it yields A sim 10minus7 cm2 correspond-ing to approximately 100 M neural cells per cm2 Thisis already close to mammal cerebral cortex neuron den-sity (per cortex area39) A substantial additional densityincrease may be obtained by the further crossbar scaling(some conceptual problems such as quantum-mechanicaltunneling between the adjacent nanowires do not start untilFnano sim 2 nm) quasi-3D40 and genuine-3D41 integration aswell as and using single ldquomemristiverdquo crosspoint deviceswith continuously adjustable conductance as synapsesmdashsee Section 6 belowCrossNet speed estimates are even more impressive

Since some crosspoint devices may be switched faster than100 ns (see Tables IndashIII in Ref [6]) the main speed lim-itation comes from the RC time of dendritic nanowirerecharging by ON currents of latching switches With thecalculated specific capacitance C0 close to 02 fFm25

a CrossNet with parameters cited above would haveC asymp C0A

12 sim 1 pF Concerning the effective resistanceRasymp RON2 ML crosspoint devices with RON values withina broad range have been demonstrated so that the mostimportant limitation comes from the necessity to keep thecircuit power density P asymp V 28F 2

nanoRON (where V is theaxonic voltage scale) at a manageable level With V =1 V the parameters cited above yield P = 1 Wcm2 atRON asymp 05times 1012 (R asymp 25times 106 For this powerlevel which does not require dedicated cooling the inter-cell delay scale RC is of the order of 25 s If P isincreased to 100 Wcm2 (typical for the high-performancemicroprocessors) the latency decreases to sim25 ns Thesenumbers are respectively approximately 3 and 5 orders ofmagnitude lower than the average intercell latency in thebiological cortex3839

Of course such comparison of CrossNet with bio-cortical circuitry would be completely fair only if theirfunctionality had been close So far theoretical neuro-science is still very far from telling us how this goal maybe achieved and gives recipes for performing only rela-tively simple cognitive tasks (some of which neverthelessalready have important practical applications) The nextsection describes some options for implementation suchrecipes in CrossNets

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EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

4 SYNAPTIC WEIGHTSETTINGADAPTATIONPLASTICITY

In neurocomputing the role of programming is playedby setting synaptic weights to their desired valuesmdasheitherbefore the calculation or in runtime (Weight adaptation inthe latter mode is frequently referred to as network ldquoplas-ticityrdquo) What follows is the list of procedures which havealready been developed and demonstrated (on adequatecomputer models of CrossNets) for this purpose

41 Weight Import

If the set of synaptic weights for a particular task has beendetermined using an external digital computer (a ldquoprecur-sorrdquo) these weights may be imported into a CrossNetThis task is not so trivial Indeed setting a certain setwjk of synaptic weights in a CrossNet with bistable cross-point devices requires switching each device into its properstate either ON and OFF For that voltages applied totwo nanowires leading to each device have to be manipu-lated in a way which ensures the desirable switching eventin the selected device while not perturbing the states ofother (ldquosemi-selectedrdquo) devices connected to each of thewires Moreover the import procedure should be paral-lelized as much as possible to ensure practicable weightimport timesNevertheless such import procedures with a number

of time steps scaling as M (rather than the total numberof crosspoint devices in the network) have been devel-oped both for InBars and FlossBars both with binary29

and multi-level2932 synaptic weights There is a feelingthat these solutions may be extended to virtually any futureCrossNet topology

42 In-Situ Adaptation Firing-Rate Models

If the task of synaptic weight calculation is too large for adigital precursor it has to be performed within the Cross-Net itself Of several adaptation algorithms the Hebb ruleand its variations36ndash38 are believed to be most importantFigure 7 shows the method (based on the well-known ldquosta-tistical multiplicationrdquo approach) of providing the Hebb-type plasticity in firing-rate CrossNets30

In this method each synapse consists of four arrays ofntimesn elementary latching switches fed by bipolar (dual-rail) voltages so that in the signal propagation mode thesynaptic weight may take any of the L = 4n2 + 1 quan-tized equidistant values within the zero-centered range[minuswmax +wmax] In the weight adaptation mode voltagesV1t and V2t are developed by comparators C12 withbinary outputs The comparators are fed by(i) the analog signals x12 (supplied by somatic cells) withmagnitudes limited to a certain range [0 xmax] and thesigns changed in time to perform 4-stage time divisionmultiplexing (see the table inset in Fig 7) and

+V1

ndashV1

ndashV2+V2

plusmnx1

plusmnx2

RND1

RND2

C2

C1

S(t)

S(t)

S(t)

S(t)

Stage 1 2 3 4

Sign of x1 + ndash + ndash

Sign of x2 ndash + + ndash

Sign of S + + ndash ndash

Fig 7 Stochastic multiplication scheme for quasi-Hebbian weightadaptation Each green circle is the latching switch the compositesynapse consists of four groups of ntimes n switches (The figure is forn= 3) RND12 are random (quasi-)analog signals while C12 are the sig-nal comparators with binary outputs The inset table shows the 4-stagetime division multiplexing sequence (The order of stages is arbitrary buttheir time duration should be similar)

(ii) reference signals REF12 from two independentpseudo-random signal generators with the uniform prob-ability within the same range [0 xmax]

In this arrangement the probability of each compara-tor to apply the voltage of proper polarity to each outputwire is proportional to the input analog signal A straight-forward analysis30 shows that as a result the averagesynaptic weight change during a time-division multiplex-ing cycle is

w = x1x2timeswmaxminusw for x1x2 gt 0

wmax+w for x1x2 lt 0(3)

where is a constant depending on the bistable deviceparameters and the comparator output voltage This is justthe standard x1x2 form of the Hebb rule but with addi-tional saturation (which is unavoidable at hardware imple-mentation of synaptic weights)An important feature of this adaptation method is that all

necessary circuitry (including the comparator and pseudo-random number generator) serving one axonic or dendriticline may be shared by all M synapses of that line As aresult the overhead of CMOS hardware necessary for theirimplementation does not affect density of CrossNets withbiologically-plausible values of connectivity M

43 In-Situ Adaptation STDP

In spiking neuromorphic networks which explicitly modelneural pulses in biological systems the most popular wayof the Hebb rule implementation is the so-called spike-time-dependent plasticity STDP4243 The STDP requires

326 Sci Adv Mater 3 322ndash331 2011

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REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

to increase the probability of OFFrarr ON switching if thepre-synaptic and post-synaptic spikes are within a certaintime window (the latter spike follows the former one) andsuppress the probability in the opposite caseFigure 8 shows an simple example of how this can be

achieved in spiking CrossNets6 Each spike consists of twovoltage pulses a longer pulse A and a shorter but higherpulse B with the amplitude approaching (but somewhatbelow) the switching threshold Vt Applied to a compositesynapse (Fig 6) the former pulse creates a current pulsewhich causes a gradual RC-increase of the dendritic volt-age Vd (The contribution of pulse B to the recharging issmall due to its short duration)If the dendritic voltage was well below the spiking

threshold of the post-synaptic cell the dendritic wirerecharging decreases the net voltage V = VandashVd applied tothe crosspoint switches and hence creates a certain (small)probability of ON rarr OFF switching of those deviceswhich were in their ON state However if Vd was closeenough to the threshold the recharging triggers a sim-ilar spike in the post-synaptic neuron The somatic cir-cuitry sends this pulse not only to that somarsquos output(V prime

a but also back to the dendrite with the appropriate(negative) polarity Now the net voltage V is increasedso that when the short pulse B is applied to the axonicnanowire V exceeds the threshold creating a finite proba-bility of switching for those crosspoint devices of the com-posite synapse which were still in their OFF state (Similarschemes but with more complex somatic circuitry havebeen proposed in Refs [44ndash46])Unfortunately numerical modeling shows that this

scheme does not promise good scaling of STDP plastic-ity with growing connectivity M (Fig 9) The reason is

∆Gjk prop (Vjk)max

Vdj(t)gtVt

triggers spike

(k prime = 1hellipMndash1)

CVdj(t)

Va(tndash tk)

Gjk

Vjk(t)

Gjkprime Cf

Va(tndash tkprime)

Va(tndash tj)

inverter

t0 τ1 τ2 τ3

V1

V2

Va(t)

(a)

(b)

Fig 8 (a) The somatic circuit providing STDP and (b) the spike formused for simulations

ndash100 ndash50 0 50 100

20

21

22

23

Vm

axV

1

(tj ndash tk)τ0

M = 1024

Fig 9 Maximum synaptic voltage Vmax (which defines the STDPresponse) versus the time delay between the output (post-synaptic) spikeand the input (pre-synaptic) spike for a CrossNet with two-terminaldevices (Fig 8) for relatively high connectivity M Small black pointsraw results of 20000 numerical experiments with random spike timingred squares values of Vmax averaged within 25 0mdashwide time bins Otherparameters f0 = 001 0 = 10 = 20 = 10 (3 minus 20 = 01V2V1 = 2

(a)

(b)

from soma kprime

from soma k

Vgjprime Vdjprime Vgj Vdj

Vak

Vakprime

synapsejk

additionalgate wires

(one per cell)

∆Gjk

prop (Vjk)max

Vdj(t)gtVt

triggers spike

(kprime = 1hellipMndash1)

C

Vgj(t)

Gjk

Vjk(t)

Gjkprime

Vdj(t)

Va(tndash tk)

Va(tndash tkprime)

Va(tndash tj)

timesα

scalinginverter

from tosoma jprime

from tosoma jprime

Fig 10 The simplest Flash CrossNet (a) a 2times2 fragment of the synap-tic field and (b) the somatic circuit providing STDP adaptation

Sci Adv Mater 3 322ndash331 2011 327

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EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Table I Approximate bias conditions for crosspoint synapses based onstandard NAND flash memory cells

Electrode potentials(versus the p-well) Vak Vdk Vgj Vakprime Vdj prime Vgj prime

Spike propagation 0 V float 0 V +5 V float +5 Vwith STDP +spikes k minusspikes j +spikes kprime minusspikes j prime

Block reset 0 V 0 V minus15 V 0 V 0 V minus15 V(all Gjk larrGmax

Particular weight 0 V float +15 V +7 V Float 0 Vimport (Gjk larr 0)

that at the bio-plausible average rate f of spikes generatedby each cell may be as high as sim01 where is thespike duration so that the product Mf may be muchhigher than 1 meaning that at the input of each somamany spikes may overlap As a result the STDP responsebecomes noisy and its average deviates from the desiredantisymmetric function of the spike delayWays toward better scaling still have to explored here

let me only mention that these complications may benaturally avoided in ldquoFlash CrossNetsrdquomdashmodel circuitsusing flash memory cells working in the analog modemdashseeFigure 10 and Table I (Earlier suggestions of using flashtechnology in neuromorphic networks47ndash49 were based onmore complex cells)Figure 11 shows a typical result of theoretical analysis

of such flash synapses with the simple somatic feedbackcircuit shown in Figure 10(b) using both Monte Carlomodeling and an approximate quasi-analytical single-spike approximation (exact in the limit Mf rarr 0) Theresults indicate very good scaling of the STDP responseeven at Mf 1 limited only by the biologically-plausible condition f 1 due to a natural separationof the adjustment feedback signals Vg from feedforwarddendritic signals VdOf course the flash memory technology is essentially a

twist of CMOS so that it requires patterning with accurate

ndash15 ndash10 ndash5 0 502

03

04

05

a = 04τ1τ2 = 2Tτ2 = 10

ττ2 = 20

α = 08

Fig 11 Maximum source-to-gate voltage Vmax in a Flash CrossNet(Fig 10) versus the spike delay Small points simulation results fromsim2400 numerical experiments squaresmdashresults given by the single-spike approximation

layer alignment and cannot be scaled down as much asnanowire crossbars However in Flash CrossNets one flashcell may provide the synaptic weight accuracy compara-ble to that of a multi-latching-switch array (Figs 6 7)at a comparable network density (Suggestions50 to usecontinuously-adjusted memristive crosspoint devices forproviding analog synaptic weights would probably requiremuch lower device-to-device variability than the onedemonstrated experimentally)

5 APPLICATION EXAMPLES

The results presented in this section have been obtained byCrossNet simulation using their realistic models They givesome idea about possible performance of such networks

51 Hopfield Networks Pattern Recognition

Possibly the simplest type of an artificial neural net isthe recurrent firing-rate network with symmetric synap-tic weights wjk = wkj (Such networks had been exploredby several researchers51 before they were made famousby Hopfield52) Properly trained the Hopfield networkmay work as an associative memory using a part of apre-written patterns to restore (ldquorecognizerdquo) the wholepatternSince the capacity of such memory is very weakly

affected by synaptic weight discreteness a CrossNet withjust one latching switch per synapse may operate very wellin this mode its main difference from the generic Hop-field net is the quasi-local (rather than global) connectiv-ity M limiting its capacity to sim045 M at 99 restorationfidelity53

Figure 12 shows an example of such an operation thefinal image is completely error free However the mostremarkable feature of the pattern restoration is its speed(sim 5 RC) taking into account that in realistic CrossNetsthe RC time constant may be below 1 s (See Section 3above)

t RC = 0

Fig 12 Dynamics of recognition of one of three trained black-and-white images by an InBar-type CrossNet with 256times256 neural cellsand connectivity parameter M = 64 The initial image (left panel) wasobtained from the trained image (identical to the one shown in the rightpanel) by flipping as many as 40 of pixels at random RC is theeffective time constant of intercell interaction Reprinted with permissionfrom [53] Ouml Tuumlrel and K K Likharev Possible nanoelectronic imple-mentation of neuromorphic networks Proc IJCNNrsquo03 (2003) pp 365ndash370 copy 2003 IEEE

328 Sci Adv Mater 3 322ndash331 2011

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REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

52 Multilayer Perceptrons Pattern Classification

A much more important but also more demandingfunction of neuromorphic networks is the pattern clas-sification which may be achieved for example inlayered perceptrons after their supervised training by errorbackpropagationmdashsee eg Refs [36ndash38] Two major con-cerns about using CrossNets in this mode have been(i) the necessary accuracy of synaptic weights and(ii) defect tolerance

Figure 13 shows typical results of study32 which useda very common benchmarkmdashthe MNIST database oftypewritten characters54 It shows that for exampleL= 33 synaptic levels (available from two 4times4 compos-ite synapses shown in Fig 6) are sufficient for gettingvirtually the same fidelity (sim98) as for exact (contin-uous) synaptic weights and that a very substantial num-ber of stuck-at-closed defects cause only a slow fidelitydegradationThese results pertain to weights imported from a pre-

cursor network this training method is quite sufficient forexample for a known face recognition in a large crowdbecause it may be based on using multiple copies of thedesired pattern with a TV-raster-type search (Fig 14)Estimates have shown55 that such a CrossNet chip witharea below 1 cm2 may identify a face on a 8-Mpixel imagein approximately 100 s the number to be compared withsim103 s for the same algorithm run on a general-purposemicroprocessor

53 Global Reinforcement and TD Learning

Some cognitive tasks require unsupervised learning inparticular global reinforcement with either instant or

00 01 02 03 04 05 06001

01

Cla

ssifi

catio

n er

ror

frac

tion

Defect fraction q

L = 73D

L = 51D

L = 33DL = 73C

L = 51CL = 33CC Continuous-weight precursor

D Discrete-weight precursor

Fig 13 The MNIST set classification error of CrossNets with weightsimported from a discrete-weight precursor network as a function of thefraction of bad nanodevices in comparison with that for the continuous-weight precursor results L is the number of discrete weight levelsReprinted with permission from [32] J H Lee and K K Likharev IntJ Circuit Theory App 35 239 (2007) copy 2007 John Wiley amp Sons Ltd

w

h

ImagePanel k

Input ofnetwork

processingpanel k

Fig 14 Scan mapping of the input image on CrossNet inputs Red linesshow the possible time sequence of image pixels sent to a certain inputof the network processing image from the upper-left panel of the pattern

Fig 15 Dynamics of learning to balance the cart-pole system (seeinset) using three synaptic weight adaptation rules (All results wereaveraged over 20 independent experiments) Reprinted with permissionfrom [33] X Ma and K K Likharev IEEE Trans on Neural Networks18 573 (2007) copy 2007 IEEE

delayed reward36ndash3856 A study of this mode of CrossNetoperation33 has shown that these networks are quite suit-able for the most popular global-reinforcement algorithmssuch as Ari

56 Moreover they may use similar algorithms(which have been called A1 and A1 based on synap-tic rather than somatic randomness which are more natu-ral for nanodevice implementation of synapses Figure 15shows that these new algorithms provide just a slightlylower learning speed than Ari for the cart-and-pole balanc-ing taskmdasha popular benchmark for global reinforcementwith delayed reward

6 PROSPECTS CHALLENGESAND OPTIONS

Though studies of possible CrossNet applications are inthe very beginning it looks like that these networks maybe used for performing virtually any cognitive task whichhad been demonstrated using software-implemented neu-ral nets at very high speed (with manageable power

Sci Adv Mater 3 322ndash331 2011 329

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IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Crossbar layer

Via translation layer

CMOS layer

Fig 16 Possible 3D hybrid circuit with area-distributed interface

consumption) This may enable at least two areas of Cross-Net applications(i) Relatively simple networks performing well-understood tasks (such as face recognition) at a very highspeedmdashsee Section 52 above(ii) Experimental networks used for high-performancestudies of novel neuromorphic algorithmsmdashboth for mod-eling certain cortical functions and for the implementationof more complex practical cognitive tasks such as datamining or autonomous robotic operation in complex andhostile environments

Moreover it is possible (though by no means guar-anteed) that in future CrossNet circuits will becomethe first hardware capable of challenging the mammal(human) cerebral cortex This opportunity may be evenmore enhanced by the recent suggestion of several quasi-3D40 and genuinely-3D41 versions of CMOL circuitsmdashseeeg Figure 16However in order for that to happen numerous issues

have to be resolved First of all the existing methodsof fabrication of crosspoint devices with latching-switchfunctionality have to be improved to increase their yieldand reduce device-to-device variability It may happen thatthe solution of this problem will require latching switcheswith a completely different physics of their operationmdashforexample based on single-electron tunneling in molecularself-assembled monolayers57

Second integration of hybrid circuits has to be demon-strated at much larger scale than it has been done so farwhich in turn may require facing several technologicalchallenges (such as fabrication of nanometer-sharp inter-connect pins at temperatures allowable at the back end ofCMOS stack)Last but not least new CrossNet architectures capa-

ble of performing more complex cognitive tasks have to

be suggested and exploredmdashpossibly assisted by modelingwith simpler CrossNet circuits

Acknowledgments Useful discussions with L AbbottP Adams R Douglass R Granger D HammerstromP Hasler G Hinton E Izhikevich J KrichmarC Lebiere Y LeCun J H Lee X Ma A MayrR Miikkulainen R OrsquoReilly T Sejnowski N SimonianG Snider N Srinivasa D Strukov Ouml Tuumlrel and R SWilliams as well as technical help by T S Singh aregratefully acknowledged

References and Notes

1 K Likharev A Mayr I Muckra and Ouml Tuumlrel Ann NY Acad Sci1006 146 (2003)

2 K K Likharev Interface 14 43 (2005)3 K K Likharev and D B Strukov CMOL Devices circuits and

architectures edited by G Cuniberti G Fagas and K Richter Intro-ducing Molecular Electronics Springer Berlin (2005) pp 447ndash477

4 K K Likharev J Nanoel Optoel 3 203 (2008)5 L O Chua IEEE Trans on Circuit Theory 18 507 (1971)6 G F Cerofolini and E Romano Appl Phys A 91 181 (2008)7 Q F Xia W Robinett M W Cumbie N Banerjee T J Cardinali

J J Yang W Wu X M Li W M Tong D B Strukov G SSnider G Medeiros-Ribeiro and R S Williams Nano Lett 9 3640(2009)

8 K K Likharev J Vac Sci Technol B 25 2531 (2007)9 L J Guo J Phys D 37 R123 (2004)10 D J Wagner and A H Jayatissa Proc SPIE 6002 136

(2005)11 M Bender A Fuchs U Plachetka and H Kurz Microel Eng

83 827 (2006)12 H H Solak J Phys DmdashAppl Phys 39 R171 (2006)13 B Q Wua and A Kumar J Vac Sci Technol B 25 1743

(2007)14 V Auzelyte C Dais P Farquet D Gruzmacher L J Heyderman

F Luo S Olliges C Padeste P K Sahoo T ThomsonA Turchanin C David and H H Solak J MicroNanolith MEMSMOEMS 8 3640 (2009)

15 I W Hamley Nanotechnology 14 R39 (2003)16 D Bratton D Yang J Y Dai and C K Ober Polymers for

Advanced Technologies 17 94 (2006)17 M N Kozicki IEEE Trans on Nanotechnology 4 331 (2005)18 R Waser and M Aono Nat Mater 6 833 (2007)19 I G Baek et al Multi-layer cross-point binary oxide resistive mem-

ory (OxRRAM) for post-NAND storage applications Tech DigestIEDMrsquo05 pp 750ndash753

20 S H Jo and W Lu Nano Lett 8 392 (2008)21 T W Kim H Choi S H Oh M Jo G Wang B Cho D Y Kim

H Hwang and T Lee Nanotechnology 20 art 025201 (2009)22 J Borghetti G S Snider P J Kuekes J J Yang D R Stewart

and R S Williams Nature 464 873 (2010)23 K K Likharev and D B Strukov Prospects for the development of

digital CMOL circuits Proc NanoArchrsquo07 pp 109ndash11624 D B Strukov and K K Likharev J Nanosci Nanotechnol 7 151

(2007)25 D B Strukov and K K Likharev Nanotechnology 16 888

(2005)26 D B Strukov and K K Likharev A reconfigurable architecture for

hybrid CMOSnanodevice circuits Proc FPGArsquo06 pp 131ndash14027 S Foumllling Ouml Tuumlrel and K Likharev Single-electron latching

switches as nanoscale synapses Proc IJCNNrsquo01 pp 216ndash221

330 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733

REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

Vj

i = 1

2

hellip

RS RL

Vj

i prime = 1 hellip n 2

Fig 6 Composite synapse providing L = n2 + 1 discrete weight lev-els Dark-gray rectangles are resistive metallic strips at somenanowireinterfaces

Perhaps the most important feature of CrossNets is thattheir connectivity M (the upper limit in the sum in Eq (1)ie the number of cells providing signal to any given oneldquodirectlyrdquo (via a synaptic contact) depends only on thedistance between the somas and theoretically is unlimiteddespite the quasi-2D geometry of these circuits This isvery important for modeling of (and eventually competingwith) bio-cortical circuits whose average connectivity isclose to 10439

Besides the intercell distance (and hence the connectiv-ity) CrossNet properties depend on the cell distributionover the synaptic field Figure 5 shows the feedforwardversions of two CrossNet types most explored so far theso-called FlossBar and InBar28 The former network ismore natural for the implementation of multilayered per-ceptrons (MLP see Section 52) while the latter systemmay be preferable for recurrent network implementations(Section 51)The generic topologies shown in Figures 4ndash5 may be

readily extended to more advanced neuromorphic net-works For example flexible combinations of FlossBarand InBar plaquettes are straightforward to engineer55

Also if the used crosspoint devices are bistable (Fig 2)ie if a single device provides binary synaptic weightsynapses with multi-level weights may be organized fromsmall arrays of such bistable switches (Fig 6) two com-plementary square arrays of ntimes n switches each pro-vide L= 2n2+1 discrete weight levels with L= 33 (ien= 4) being sufficient for some key algorithms32

3 PERFORMANCE ESTIMATES

The most important motivation for the architecturedevelopment quantitative simulation (and eventually

hardware implementation) of CMOL CrossNets comesfrom estimates of their possible density speed and powerIn CMOL topology the total area occupied by synapsesserving one cell is close to

Aasymp 4 MLF 2nano (2)

At reasonable connectivity (M gt 102 and weight leveldiscreteness (Lge 33) this area is more than sufficient forthe layout of even the most complex (say spiking) somaticcircuitry so that CrossNet density may be estimated fromEq (2) For such realistic numbers as L= 33 M = 3times103and Fnano = 5 nm it yields A sim 10minus7 cm2 correspond-ing to approximately 100 M neural cells per cm2 Thisis already close to mammal cerebral cortex neuron den-sity (per cortex area39) A substantial additional densityincrease may be obtained by the further crossbar scaling(some conceptual problems such as quantum-mechanicaltunneling between the adjacent nanowires do not start untilFnano sim 2 nm) quasi-3D40 and genuine-3D41 integration aswell as and using single ldquomemristiverdquo crosspoint deviceswith continuously adjustable conductance as synapsesmdashsee Section 6 belowCrossNet speed estimates are even more impressive

Since some crosspoint devices may be switched faster than100 ns (see Tables IndashIII in Ref [6]) the main speed lim-itation comes from the RC time of dendritic nanowirerecharging by ON currents of latching switches With thecalculated specific capacitance C0 close to 02 fFm25

a CrossNet with parameters cited above would haveC asymp C0A

12 sim 1 pF Concerning the effective resistanceRasymp RON2 ML crosspoint devices with RON values withina broad range have been demonstrated so that the mostimportant limitation comes from the necessity to keep thecircuit power density P asymp V 28F 2

nanoRON (where V is theaxonic voltage scale) at a manageable level With V =1 V the parameters cited above yield P = 1 Wcm2 atRON asymp 05times 1012 (R asymp 25times 106 For this powerlevel which does not require dedicated cooling the inter-cell delay scale RC is of the order of 25 s If P isincreased to 100 Wcm2 (typical for the high-performancemicroprocessors) the latency decreases to sim25 ns Thesenumbers are respectively approximately 3 and 5 orders ofmagnitude lower than the average intercell latency in thebiological cortex3839

Of course such comparison of CrossNet with bio-cortical circuitry would be completely fair only if theirfunctionality had been close So far theoretical neuro-science is still very far from telling us how this goal maybe achieved and gives recipes for performing only rela-tively simple cognitive tasks (some of which neverthelessalready have important practical applications) The nextsection describes some options for implementation suchrecipes in CrossNets

Sci Adv Mater 3 322ndash331 2011 325

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IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

4 SYNAPTIC WEIGHTSETTINGADAPTATIONPLASTICITY

In neurocomputing the role of programming is playedby setting synaptic weights to their desired valuesmdasheitherbefore the calculation or in runtime (Weight adaptation inthe latter mode is frequently referred to as network ldquoplas-ticityrdquo) What follows is the list of procedures which havealready been developed and demonstrated (on adequatecomputer models of CrossNets) for this purpose

41 Weight Import

If the set of synaptic weights for a particular task has beendetermined using an external digital computer (a ldquoprecur-sorrdquo) these weights may be imported into a CrossNetThis task is not so trivial Indeed setting a certain setwjk of synaptic weights in a CrossNet with bistable cross-point devices requires switching each device into its properstate either ON and OFF For that voltages applied totwo nanowires leading to each device have to be manipu-lated in a way which ensures the desirable switching eventin the selected device while not perturbing the states ofother (ldquosemi-selectedrdquo) devices connected to each of thewires Moreover the import procedure should be paral-lelized as much as possible to ensure practicable weightimport timesNevertheless such import procedures with a number

of time steps scaling as M (rather than the total numberof crosspoint devices in the network) have been devel-oped both for InBars and FlossBars both with binary29

and multi-level2932 synaptic weights There is a feelingthat these solutions may be extended to virtually any futureCrossNet topology

42 In-Situ Adaptation Firing-Rate Models

If the task of synaptic weight calculation is too large for adigital precursor it has to be performed within the Cross-Net itself Of several adaptation algorithms the Hebb ruleand its variations36ndash38 are believed to be most importantFigure 7 shows the method (based on the well-known ldquosta-tistical multiplicationrdquo approach) of providing the Hebb-type plasticity in firing-rate CrossNets30

In this method each synapse consists of four arrays ofntimesn elementary latching switches fed by bipolar (dual-rail) voltages so that in the signal propagation mode thesynaptic weight may take any of the L = 4n2 + 1 quan-tized equidistant values within the zero-centered range[minuswmax +wmax] In the weight adaptation mode voltagesV1t and V2t are developed by comparators C12 withbinary outputs The comparators are fed by(i) the analog signals x12 (supplied by somatic cells) withmagnitudes limited to a certain range [0 xmax] and thesigns changed in time to perform 4-stage time divisionmultiplexing (see the table inset in Fig 7) and

+V1

ndashV1

ndashV2+V2

plusmnx1

plusmnx2

RND1

RND2

C2

C1

S(t)

S(t)

S(t)

S(t)

Stage 1 2 3 4

Sign of x1 + ndash + ndash

Sign of x2 ndash + + ndash

Sign of S + + ndash ndash

Fig 7 Stochastic multiplication scheme for quasi-Hebbian weightadaptation Each green circle is the latching switch the compositesynapse consists of four groups of ntimes n switches (The figure is forn= 3) RND12 are random (quasi-)analog signals while C12 are the sig-nal comparators with binary outputs The inset table shows the 4-stagetime division multiplexing sequence (The order of stages is arbitrary buttheir time duration should be similar)

(ii) reference signals REF12 from two independentpseudo-random signal generators with the uniform prob-ability within the same range [0 xmax]

In this arrangement the probability of each compara-tor to apply the voltage of proper polarity to each outputwire is proportional to the input analog signal A straight-forward analysis30 shows that as a result the averagesynaptic weight change during a time-division multiplex-ing cycle is

w = x1x2timeswmaxminusw for x1x2 gt 0

wmax+w for x1x2 lt 0(3)

where is a constant depending on the bistable deviceparameters and the comparator output voltage This is justthe standard x1x2 form of the Hebb rule but with addi-tional saturation (which is unavoidable at hardware imple-mentation of synaptic weights)An important feature of this adaptation method is that all

necessary circuitry (including the comparator and pseudo-random number generator) serving one axonic or dendriticline may be shared by all M synapses of that line As aresult the overhead of CMOS hardware necessary for theirimplementation does not affect density of CrossNets withbiologically-plausible values of connectivity M

43 In-Situ Adaptation STDP

In spiking neuromorphic networks which explicitly modelneural pulses in biological systems the most popular wayof the Hebb rule implementation is the so-called spike-time-dependent plasticity STDP4243 The STDP requires

326 Sci Adv Mater 3 322ndash331 2011

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REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

to increase the probability of OFFrarr ON switching if thepre-synaptic and post-synaptic spikes are within a certaintime window (the latter spike follows the former one) andsuppress the probability in the opposite caseFigure 8 shows an simple example of how this can be

achieved in spiking CrossNets6 Each spike consists of twovoltage pulses a longer pulse A and a shorter but higherpulse B with the amplitude approaching (but somewhatbelow) the switching threshold Vt Applied to a compositesynapse (Fig 6) the former pulse creates a current pulsewhich causes a gradual RC-increase of the dendritic volt-age Vd (The contribution of pulse B to the recharging issmall due to its short duration)If the dendritic voltage was well below the spiking

threshold of the post-synaptic cell the dendritic wirerecharging decreases the net voltage V = VandashVd applied tothe crosspoint switches and hence creates a certain (small)probability of ON rarr OFF switching of those deviceswhich were in their ON state However if Vd was closeenough to the threshold the recharging triggers a sim-ilar spike in the post-synaptic neuron The somatic cir-cuitry sends this pulse not only to that somarsquos output(V prime

a but also back to the dendrite with the appropriate(negative) polarity Now the net voltage V is increasedso that when the short pulse B is applied to the axonicnanowire V exceeds the threshold creating a finite proba-bility of switching for those crosspoint devices of the com-posite synapse which were still in their OFF state (Similarschemes but with more complex somatic circuitry havebeen proposed in Refs [44ndash46])Unfortunately numerical modeling shows that this

scheme does not promise good scaling of STDP plastic-ity with growing connectivity M (Fig 9) The reason is

∆Gjk prop (Vjk)max

Vdj(t)gtVt

triggers spike

(k prime = 1hellipMndash1)

CVdj(t)

Va(tndash tk)

Gjk

Vjk(t)

Gjkprime Cf

Va(tndash tkprime)

Va(tndash tj)

inverter

t0 τ1 τ2 τ3

V1

V2

Va(t)

(a)

(b)

Fig 8 (a) The somatic circuit providing STDP and (b) the spike formused for simulations

ndash100 ndash50 0 50 100

20

21

22

23

Vm

axV

1

(tj ndash tk)τ0

M = 1024

Fig 9 Maximum synaptic voltage Vmax (which defines the STDPresponse) versus the time delay between the output (post-synaptic) spikeand the input (pre-synaptic) spike for a CrossNet with two-terminaldevices (Fig 8) for relatively high connectivity M Small black pointsraw results of 20000 numerical experiments with random spike timingred squares values of Vmax averaged within 25 0mdashwide time bins Otherparameters f0 = 001 0 = 10 = 20 = 10 (3 minus 20 = 01V2V1 = 2

(a)

(b)

from soma kprime

from soma k

Vgjprime Vdjprime Vgj Vdj

Vak

Vakprime

synapsejk

additionalgate wires

(one per cell)

∆Gjk

prop (Vjk)max

Vdj(t)gtVt

triggers spike

(kprime = 1hellipMndash1)

C

Vgj(t)

Gjk

Vjk(t)

Gjkprime

Vdj(t)

Va(tndash tk)

Va(tndash tkprime)

Va(tndash tj)

timesα

scalinginverter

from tosoma jprime

from tosoma jprime

Fig 10 The simplest Flash CrossNet (a) a 2times2 fragment of the synap-tic field and (b) the somatic circuit providing STDP adaptation

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EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Table I Approximate bias conditions for crosspoint synapses based onstandard NAND flash memory cells

Electrode potentials(versus the p-well) Vak Vdk Vgj Vakprime Vdj prime Vgj prime

Spike propagation 0 V float 0 V +5 V float +5 Vwith STDP +spikes k minusspikes j +spikes kprime minusspikes j prime

Block reset 0 V 0 V minus15 V 0 V 0 V minus15 V(all Gjk larrGmax

Particular weight 0 V float +15 V +7 V Float 0 Vimport (Gjk larr 0)

that at the bio-plausible average rate f of spikes generatedby each cell may be as high as sim01 where is thespike duration so that the product Mf may be muchhigher than 1 meaning that at the input of each somamany spikes may overlap As a result the STDP responsebecomes noisy and its average deviates from the desiredantisymmetric function of the spike delayWays toward better scaling still have to explored here

let me only mention that these complications may benaturally avoided in ldquoFlash CrossNetsrdquomdashmodel circuitsusing flash memory cells working in the analog modemdashseeFigure 10 and Table I (Earlier suggestions of using flashtechnology in neuromorphic networks47ndash49 were based onmore complex cells)Figure 11 shows a typical result of theoretical analysis

of such flash synapses with the simple somatic feedbackcircuit shown in Figure 10(b) using both Monte Carlomodeling and an approximate quasi-analytical single-spike approximation (exact in the limit Mf rarr 0) Theresults indicate very good scaling of the STDP responseeven at Mf 1 limited only by the biologically-plausible condition f 1 due to a natural separationof the adjustment feedback signals Vg from feedforwarddendritic signals VdOf course the flash memory technology is essentially a

twist of CMOS so that it requires patterning with accurate

ndash15 ndash10 ndash5 0 502

03

04

05

a = 04τ1τ2 = 2Tτ2 = 10

ττ2 = 20

α = 08

Fig 11 Maximum source-to-gate voltage Vmax in a Flash CrossNet(Fig 10) versus the spike delay Small points simulation results fromsim2400 numerical experiments squaresmdashresults given by the single-spike approximation

layer alignment and cannot be scaled down as much asnanowire crossbars However in Flash CrossNets one flashcell may provide the synaptic weight accuracy compara-ble to that of a multi-latching-switch array (Figs 6 7)at a comparable network density (Suggestions50 to usecontinuously-adjusted memristive crosspoint devices forproviding analog synaptic weights would probably requiremuch lower device-to-device variability than the onedemonstrated experimentally)

5 APPLICATION EXAMPLES

The results presented in this section have been obtained byCrossNet simulation using their realistic models They givesome idea about possible performance of such networks

51 Hopfield Networks Pattern Recognition

Possibly the simplest type of an artificial neural net isthe recurrent firing-rate network with symmetric synap-tic weights wjk = wkj (Such networks had been exploredby several researchers51 before they were made famousby Hopfield52) Properly trained the Hopfield networkmay work as an associative memory using a part of apre-written patterns to restore (ldquorecognizerdquo) the wholepatternSince the capacity of such memory is very weakly

affected by synaptic weight discreteness a CrossNet withjust one latching switch per synapse may operate very wellin this mode its main difference from the generic Hop-field net is the quasi-local (rather than global) connectiv-ity M limiting its capacity to sim045 M at 99 restorationfidelity53

Figure 12 shows an example of such an operation thefinal image is completely error free However the mostremarkable feature of the pattern restoration is its speed(sim 5 RC) taking into account that in realistic CrossNetsthe RC time constant may be below 1 s (See Section 3above)

t RC = 0

Fig 12 Dynamics of recognition of one of three trained black-and-white images by an InBar-type CrossNet with 256times256 neural cellsand connectivity parameter M = 64 The initial image (left panel) wasobtained from the trained image (identical to the one shown in the rightpanel) by flipping as many as 40 of pixels at random RC is theeffective time constant of intercell interaction Reprinted with permissionfrom [53] Ouml Tuumlrel and K K Likharev Possible nanoelectronic imple-mentation of neuromorphic networks Proc IJCNNrsquo03 (2003) pp 365ndash370 copy 2003 IEEE

328 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733

REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

52 Multilayer Perceptrons Pattern Classification

A much more important but also more demandingfunction of neuromorphic networks is the pattern clas-sification which may be achieved for example inlayered perceptrons after their supervised training by errorbackpropagationmdashsee eg Refs [36ndash38] Two major con-cerns about using CrossNets in this mode have been(i) the necessary accuracy of synaptic weights and(ii) defect tolerance

Figure 13 shows typical results of study32 which useda very common benchmarkmdashthe MNIST database oftypewritten characters54 It shows that for exampleL= 33 synaptic levels (available from two 4times4 compos-ite synapses shown in Fig 6) are sufficient for gettingvirtually the same fidelity (sim98) as for exact (contin-uous) synaptic weights and that a very substantial num-ber of stuck-at-closed defects cause only a slow fidelitydegradationThese results pertain to weights imported from a pre-

cursor network this training method is quite sufficient forexample for a known face recognition in a large crowdbecause it may be based on using multiple copies of thedesired pattern with a TV-raster-type search (Fig 14)Estimates have shown55 that such a CrossNet chip witharea below 1 cm2 may identify a face on a 8-Mpixel imagein approximately 100 s the number to be compared withsim103 s for the same algorithm run on a general-purposemicroprocessor

53 Global Reinforcement and TD Learning

Some cognitive tasks require unsupervised learning inparticular global reinforcement with either instant or

00 01 02 03 04 05 06001

01

Cla

ssifi

catio

n er

ror

frac

tion

Defect fraction q

L = 73D

L = 51D

L = 33DL = 73C

L = 51CL = 33CC Continuous-weight precursor

D Discrete-weight precursor

Fig 13 The MNIST set classification error of CrossNets with weightsimported from a discrete-weight precursor network as a function of thefraction of bad nanodevices in comparison with that for the continuous-weight precursor results L is the number of discrete weight levelsReprinted with permission from [32] J H Lee and K K Likharev IntJ Circuit Theory App 35 239 (2007) copy 2007 John Wiley amp Sons Ltd

w

h

ImagePanel k

Input ofnetwork

processingpanel k

Fig 14 Scan mapping of the input image on CrossNet inputs Red linesshow the possible time sequence of image pixels sent to a certain inputof the network processing image from the upper-left panel of the pattern

Fig 15 Dynamics of learning to balance the cart-pole system (seeinset) using three synaptic weight adaptation rules (All results wereaveraged over 20 independent experiments) Reprinted with permissionfrom [33] X Ma and K K Likharev IEEE Trans on Neural Networks18 573 (2007) copy 2007 IEEE

delayed reward36ndash3856 A study of this mode of CrossNetoperation33 has shown that these networks are quite suit-able for the most popular global-reinforcement algorithmssuch as Ari

56 Moreover they may use similar algorithms(which have been called A1 and A1 based on synap-tic rather than somatic randomness which are more natu-ral for nanodevice implementation of synapses Figure 15shows that these new algorithms provide just a slightlylower learning speed than Ari for the cart-and-pole balanc-ing taskmdasha popular benchmark for global reinforcementwith delayed reward

6 PROSPECTS CHALLENGESAND OPTIONS

Though studies of possible CrossNet applications are inthe very beginning it looks like that these networks maybe used for performing virtually any cognitive task whichhad been demonstrated using software-implemented neu-ral nets at very high speed (with manageable power

Sci Adv Mater 3 322ndash331 2011 329

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Crossbar layer

Via translation layer

CMOS layer

Fig 16 Possible 3D hybrid circuit with area-distributed interface

consumption) This may enable at least two areas of Cross-Net applications(i) Relatively simple networks performing well-understood tasks (such as face recognition) at a very highspeedmdashsee Section 52 above(ii) Experimental networks used for high-performancestudies of novel neuromorphic algorithmsmdashboth for mod-eling certain cortical functions and for the implementationof more complex practical cognitive tasks such as datamining or autonomous robotic operation in complex andhostile environments

Moreover it is possible (though by no means guar-anteed) that in future CrossNet circuits will becomethe first hardware capable of challenging the mammal(human) cerebral cortex This opportunity may be evenmore enhanced by the recent suggestion of several quasi-3D40 and genuinely-3D41 versions of CMOL circuitsmdashseeeg Figure 16However in order for that to happen numerous issues

have to be resolved First of all the existing methodsof fabrication of crosspoint devices with latching-switchfunctionality have to be improved to increase their yieldand reduce device-to-device variability It may happen thatthe solution of this problem will require latching switcheswith a completely different physics of their operationmdashforexample based on single-electron tunneling in molecularself-assembled monolayers57

Second integration of hybrid circuits has to be demon-strated at much larger scale than it has been done so farwhich in turn may require facing several technologicalchallenges (such as fabrication of nanometer-sharp inter-connect pins at temperatures allowable at the back end ofCMOS stack)Last but not least new CrossNet architectures capa-

ble of performing more complex cognitive tasks have to

be suggested and exploredmdashpossibly assisted by modelingwith simpler CrossNet circuits

Acknowledgments Useful discussions with L AbbottP Adams R Douglass R Granger D HammerstromP Hasler G Hinton E Izhikevich J KrichmarC Lebiere Y LeCun J H Lee X Ma A MayrR Miikkulainen R OrsquoReilly T Sejnowski N SimonianG Snider N Srinivasa D Strukov Ouml Tuumlrel and R SWilliams as well as technical help by T S Singh aregratefully acknowledged

References and Notes

1 K Likharev A Mayr I Muckra and Ouml Tuumlrel Ann NY Acad Sci1006 146 (2003)

2 K K Likharev Interface 14 43 (2005)3 K K Likharev and D B Strukov CMOL Devices circuits and

architectures edited by G Cuniberti G Fagas and K Richter Intro-ducing Molecular Electronics Springer Berlin (2005) pp 447ndash477

4 K K Likharev J Nanoel Optoel 3 203 (2008)5 L O Chua IEEE Trans on Circuit Theory 18 507 (1971)6 G F Cerofolini and E Romano Appl Phys A 91 181 (2008)7 Q F Xia W Robinett M W Cumbie N Banerjee T J Cardinali

J J Yang W Wu X M Li W M Tong D B Strukov G SSnider G Medeiros-Ribeiro and R S Williams Nano Lett 9 3640(2009)

8 K K Likharev J Vac Sci Technol B 25 2531 (2007)9 L J Guo J Phys D 37 R123 (2004)10 D J Wagner and A H Jayatissa Proc SPIE 6002 136

(2005)11 M Bender A Fuchs U Plachetka and H Kurz Microel Eng

83 827 (2006)12 H H Solak J Phys DmdashAppl Phys 39 R171 (2006)13 B Q Wua and A Kumar J Vac Sci Technol B 25 1743

(2007)14 V Auzelyte C Dais P Farquet D Gruzmacher L J Heyderman

F Luo S Olliges C Padeste P K Sahoo T ThomsonA Turchanin C David and H H Solak J MicroNanolith MEMSMOEMS 8 3640 (2009)

15 I W Hamley Nanotechnology 14 R39 (2003)16 D Bratton D Yang J Y Dai and C K Ober Polymers for

Advanced Technologies 17 94 (2006)17 M N Kozicki IEEE Trans on Nanotechnology 4 331 (2005)18 R Waser and M Aono Nat Mater 6 833 (2007)19 I G Baek et al Multi-layer cross-point binary oxide resistive mem-

ory (OxRRAM) for post-NAND storage applications Tech DigestIEDMrsquo05 pp 750ndash753

20 S H Jo and W Lu Nano Lett 8 392 (2008)21 T W Kim H Choi S H Oh M Jo G Wang B Cho D Y Kim

H Hwang and T Lee Nanotechnology 20 art 025201 (2009)22 J Borghetti G S Snider P J Kuekes J J Yang D R Stewart

and R S Williams Nature 464 873 (2010)23 K K Likharev and D B Strukov Prospects for the development of

digital CMOL circuits Proc NanoArchrsquo07 pp 109ndash11624 D B Strukov and K K Likharev J Nanosci Nanotechnol 7 151

(2007)25 D B Strukov and K K Likharev Nanotechnology 16 888

(2005)26 D B Strukov and K K Likharev A reconfigurable architecture for

hybrid CMOSnanodevice circuits Proc FPGArsquo06 pp 131ndash14027 S Foumllling Ouml Tuumlrel and K Likharev Single-electron latching

switches as nanoscale synapses Proc IJCNNrsquo01 pp 216ndash221

330 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

4 SYNAPTIC WEIGHTSETTINGADAPTATIONPLASTICITY

In neurocomputing the role of programming is playedby setting synaptic weights to their desired valuesmdasheitherbefore the calculation or in runtime (Weight adaptation inthe latter mode is frequently referred to as network ldquoplas-ticityrdquo) What follows is the list of procedures which havealready been developed and demonstrated (on adequatecomputer models of CrossNets) for this purpose

41 Weight Import

If the set of synaptic weights for a particular task has beendetermined using an external digital computer (a ldquoprecur-sorrdquo) these weights may be imported into a CrossNetThis task is not so trivial Indeed setting a certain setwjk of synaptic weights in a CrossNet with bistable cross-point devices requires switching each device into its properstate either ON and OFF For that voltages applied totwo nanowires leading to each device have to be manipu-lated in a way which ensures the desirable switching eventin the selected device while not perturbing the states ofother (ldquosemi-selectedrdquo) devices connected to each of thewires Moreover the import procedure should be paral-lelized as much as possible to ensure practicable weightimport timesNevertheless such import procedures with a number

of time steps scaling as M (rather than the total numberof crosspoint devices in the network) have been devel-oped both for InBars and FlossBars both with binary29

and multi-level2932 synaptic weights There is a feelingthat these solutions may be extended to virtually any futureCrossNet topology

42 In-Situ Adaptation Firing-Rate Models

If the task of synaptic weight calculation is too large for adigital precursor it has to be performed within the Cross-Net itself Of several adaptation algorithms the Hebb ruleand its variations36ndash38 are believed to be most importantFigure 7 shows the method (based on the well-known ldquosta-tistical multiplicationrdquo approach) of providing the Hebb-type plasticity in firing-rate CrossNets30

In this method each synapse consists of four arrays ofntimesn elementary latching switches fed by bipolar (dual-rail) voltages so that in the signal propagation mode thesynaptic weight may take any of the L = 4n2 + 1 quan-tized equidistant values within the zero-centered range[minuswmax +wmax] In the weight adaptation mode voltagesV1t and V2t are developed by comparators C12 withbinary outputs The comparators are fed by(i) the analog signals x12 (supplied by somatic cells) withmagnitudes limited to a certain range [0 xmax] and thesigns changed in time to perform 4-stage time divisionmultiplexing (see the table inset in Fig 7) and

+V1

ndashV1

ndashV2+V2

plusmnx1

plusmnx2

RND1

RND2

C2

C1

S(t)

S(t)

S(t)

S(t)

Stage 1 2 3 4

Sign of x1 + ndash + ndash

Sign of x2 ndash + + ndash

Sign of S + + ndash ndash

Fig 7 Stochastic multiplication scheme for quasi-Hebbian weightadaptation Each green circle is the latching switch the compositesynapse consists of four groups of ntimes n switches (The figure is forn= 3) RND12 are random (quasi-)analog signals while C12 are the sig-nal comparators with binary outputs The inset table shows the 4-stagetime division multiplexing sequence (The order of stages is arbitrary buttheir time duration should be similar)

(ii) reference signals REF12 from two independentpseudo-random signal generators with the uniform prob-ability within the same range [0 xmax]

In this arrangement the probability of each compara-tor to apply the voltage of proper polarity to each outputwire is proportional to the input analog signal A straight-forward analysis30 shows that as a result the averagesynaptic weight change during a time-division multiplex-ing cycle is

w = x1x2timeswmaxminusw for x1x2 gt 0

wmax+w for x1x2 lt 0(3)

where is a constant depending on the bistable deviceparameters and the comparator output voltage This is justthe standard x1x2 form of the Hebb rule but with addi-tional saturation (which is unavoidable at hardware imple-mentation of synaptic weights)An important feature of this adaptation method is that all

necessary circuitry (including the comparator and pseudo-random number generator) serving one axonic or dendriticline may be shared by all M synapses of that line As aresult the overhead of CMOS hardware necessary for theirimplementation does not affect density of CrossNets withbiologically-plausible values of connectivity M

43 In-Situ Adaptation STDP

In spiking neuromorphic networks which explicitly modelneural pulses in biological systems the most popular wayof the Hebb rule implementation is the so-called spike-time-dependent plasticity STDP4243 The STDP requires

326 Sci Adv Mater 3 322ndash331 2011

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IP 1294956157Sat 02 Jul 2011 132733

REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

to increase the probability of OFFrarr ON switching if thepre-synaptic and post-synaptic spikes are within a certaintime window (the latter spike follows the former one) andsuppress the probability in the opposite caseFigure 8 shows an simple example of how this can be

achieved in spiking CrossNets6 Each spike consists of twovoltage pulses a longer pulse A and a shorter but higherpulse B with the amplitude approaching (but somewhatbelow) the switching threshold Vt Applied to a compositesynapse (Fig 6) the former pulse creates a current pulsewhich causes a gradual RC-increase of the dendritic volt-age Vd (The contribution of pulse B to the recharging issmall due to its short duration)If the dendritic voltage was well below the spiking

threshold of the post-synaptic cell the dendritic wirerecharging decreases the net voltage V = VandashVd applied tothe crosspoint switches and hence creates a certain (small)probability of ON rarr OFF switching of those deviceswhich were in their ON state However if Vd was closeenough to the threshold the recharging triggers a sim-ilar spike in the post-synaptic neuron The somatic cir-cuitry sends this pulse not only to that somarsquos output(V prime

a but also back to the dendrite with the appropriate(negative) polarity Now the net voltage V is increasedso that when the short pulse B is applied to the axonicnanowire V exceeds the threshold creating a finite proba-bility of switching for those crosspoint devices of the com-posite synapse which were still in their OFF state (Similarschemes but with more complex somatic circuitry havebeen proposed in Refs [44ndash46])Unfortunately numerical modeling shows that this

scheme does not promise good scaling of STDP plastic-ity with growing connectivity M (Fig 9) The reason is

∆Gjk prop (Vjk)max

Vdj(t)gtVt

triggers spike

(k prime = 1hellipMndash1)

CVdj(t)

Va(tndash tk)

Gjk

Vjk(t)

Gjkprime Cf

Va(tndash tkprime)

Va(tndash tj)

inverter

t0 τ1 τ2 τ3

V1

V2

Va(t)

(a)

(b)

Fig 8 (a) The somatic circuit providing STDP and (b) the spike formused for simulations

ndash100 ndash50 0 50 100

20

21

22

23

Vm

axV

1

(tj ndash tk)τ0

M = 1024

Fig 9 Maximum synaptic voltage Vmax (which defines the STDPresponse) versus the time delay between the output (post-synaptic) spikeand the input (pre-synaptic) spike for a CrossNet with two-terminaldevices (Fig 8) for relatively high connectivity M Small black pointsraw results of 20000 numerical experiments with random spike timingred squares values of Vmax averaged within 25 0mdashwide time bins Otherparameters f0 = 001 0 = 10 = 20 = 10 (3 minus 20 = 01V2V1 = 2

(a)

(b)

from soma kprime

from soma k

Vgjprime Vdjprime Vgj Vdj

Vak

Vakprime

synapsejk

additionalgate wires

(one per cell)

∆Gjk

prop (Vjk)max

Vdj(t)gtVt

triggers spike

(kprime = 1hellipMndash1)

C

Vgj(t)

Gjk

Vjk(t)

Gjkprime

Vdj(t)

Va(tndash tk)

Va(tndash tkprime)

Va(tndash tj)

timesα

scalinginverter

from tosoma jprime

from tosoma jprime

Fig 10 The simplest Flash CrossNet (a) a 2times2 fragment of the synap-tic field and (b) the somatic circuit providing STDP adaptation

Sci Adv Mater 3 322ndash331 2011 327

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IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Table I Approximate bias conditions for crosspoint synapses based onstandard NAND flash memory cells

Electrode potentials(versus the p-well) Vak Vdk Vgj Vakprime Vdj prime Vgj prime

Spike propagation 0 V float 0 V +5 V float +5 Vwith STDP +spikes k minusspikes j +spikes kprime minusspikes j prime

Block reset 0 V 0 V minus15 V 0 V 0 V minus15 V(all Gjk larrGmax

Particular weight 0 V float +15 V +7 V Float 0 Vimport (Gjk larr 0)

that at the bio-plausible average rate f of spikes generatedby each cell may be as high as sim01 where is thespike duration so that the product Mf may be muchhigher than 1 meaning that at the input of each somamany spikes may overlap As a result the STDP responsebecomes noisy and its average deviates from the desiredantisymmetric function of the spike delayWays toward better scaling still have to explored here

let me only mention that these complications may benaturally avoided in ldquoFlash CrossNetsrdquomdashmodel circuitsusing flash memory cells working in the analog modemdashseeFigure 10 and Table I (Earlier suggestions of using flashtechnology in neuromorphic networks47ndash49 were based onmore complex cells)Figure 11 shows a typical result of theoretical analysis

of such flash synapses with the simple somatic feedbackcircuit shown in Figure 10(b) using both Monte Carlomodeling and an approximate quasi-analytical single-spike approximation (exact in the limit Mf rarr 0) Theresults indicate very good scaling of the STDP responseeven at Mf 1 limited only by the biologically-plausible condition f 1 due to a natural separationof the adjustment feedback signals Vg from feedforwarddendritic signals VdOf course the flash memory technology is essentially a

twist of CMOS so that it requires patterning with accurate

ndash15 ndash10 ndash5 0 502

03

04

05

a = 04τ1τ2 = 2Tτ2 = 10

ττ2 = 20

α = 08

Fig 11 Maximum source-to-gate voltage Vmax in a Flash CrossNet(Fig 10) versus the spike delay Small points simulation results fromsim2400 numerical experiments squaresmdashresults given by the single-spike approximation

layer alignment and cannot be scaled down as much asnanowire crossbars However in Flash CrossNets one flashcell may provide the synaptic weight accuracy compara-ble to that of a multi-latching-switch array (Figs 6 7)at a comparable network density (Suggestions50 to usecontinuously-adjusted memristive crosspoint devices forproviding analog synaptic weights would probably requiremuch lower device-to-device variability than the onedemonstrated experimentally)

5 APPLICATION EXAMPLES

The results presented in this section have been obtained byCrossNet simulation using their realistic models They givesome idea about possible performance of such networks

51 Hopfield Networks Pattern Recognition

Possibly the simplest type of an artificial neural net isthe recurrent firing-rate network with symmetric synap-tic weights wjk = wkj (Such networks had been exploredby several researchers51 before they were made famousby Hopfield52) Properly trained the Hopfield networkmay work as an associative memory using a part of apre-written patterns to restore (ldquorecognizerdquo) the wholepatternSince the capacity of such memory is very weakly

affected by synaptic weight discreteness a CrossNet withjust one latching switch per synapse may operate very wellin this mode its main difference from the generic Hop-field net is the quasi-local (rather than global) connectiv-ity M limiting its capacity to sim045 M at 99 restorationfidelity53

Figure 12 shows an example of such an operation thefinal image is completely error free However the mostremarkable feature of the pattern restoration is its speed(sim 5 RC) taking into account that in realistic CrossNetsthe RC time constant may be below 1 s (See Section 3above)

t RC = 0

Fig 12 Dynamics of recognition of one of three trained black-and-white images by an InBar-type CrossNet with 256times256 neural cellsand connectivity parameter M = 64 The initial image (left panel) wasobtained from the trained image (identical to the one shown in the rightpanel) by flipping as many as 40 of pixels at random RC is theeffective time constant of intercell interaction Reprinted with permissionfrom [53] Ouml Tuumlrel and K K Likharev Possible nanoelectronic imple-mentation of neuromorphic networks Proc IJCNNrsquo03 (2003) pp 365ndash370 copy 2003 IEEE

328 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

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REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

52 Multilayer Perceptrons Pattern Classification

A much more important but also more demandingfunction of neuromorphic networks is the pattern clas-sification which may be achieved for example inlayered perceptrons after their supervised training by errorbackpropagationmdashsee eg Refs [36ndash38] Two major con-cerns about using CrossNets in this mode have been(i) the necessary accuracy of synaptic weights and(ii) defect tolerance

Figure 13 shows typical results of study32 which useda very common benchmarkmdashthe MNIST database oftypewritten characters54 It shows that for exampleL= 33 synaptic levels (available from two 4times4 compos-ite synapses shown in Fig 6) are sufficient for gettingvirtually the same fidelity (sim98) as for exact (contin-uous) synaptic weights and that a very substantial num-ber of stuck-at-closed defects cause only a slow fidelitydegradationThese results pertain to weights imported from a pre-

cursor network this training method is quite sufficient forexample for a known face recognition in a large crowdbecause it may be based on using multiple copies of thedesired pattern with a TV-raster-type search (Fig 14)Estimates have shown55 that such a CrossNet chip witharea below 1 cm2 may identify a face on a 8-Mpixel imagein approximately 100 s the number to be compared withsim103 s for the same algorithm run on a general-purposemicroprocessor

53 Global Reinforcement and TD Learning

Some cognitive tasks require unsupervised learning inparticular global reinforcement with either instant or

00 01 02 03 04 05 06001

01

Cla

ssifi

catio

n er

ror

frac

tion

Defect fraction q

L = 73D

L = 51D

L = 33DL = 73C

L = 51CL = 33CC Continuous-weight precursor

D Discrete-weight precursor

Fig 13 The MNIST set classification error of CrossNets with weightsimported from a discrete-weight precursor network as a function of thefraction of bad nanodevices in comparison with that for the continuous-weight precursor results L is the number of discrete weight levelsReprinted with permission from [32] J H Lee and K K Likharev IntJ Circuit Theory App 35 239 (2007) copy 2007 John Wiley amp Sons Ltd

w

h

ImagePanel k

Input ofnetwork

processingpanel k

Fig 14 Scan mapping of the input image on CrossNet inputs Red linesshow the possible time sequence of image pixels sent to a certain inputof the network processing image from the upper-left panel of the pattern

Fig 15 Dynamics of learning to balance the cart-pole system (seeinset) using three synaptic weight adaptation rules (All results wereaveraged over 20 independent experiments) Reprinted with permissionfrom [33] X Ma and K K Likharev IEEE Trans on Neural Networks18 573 (2007) copy 2007 IEEE

delayed reward36ndash3856 A study of this mode of CrossNetoperation33 has shown that these networks are quite suit-able for the most popular global-reinforcement algorithmssuch as Ari

56 Moreover they may use similar algorithms(which have been called A1 and A1 based on synap-tic rather than somatic randomness which are more natu-ral for nanodevice implementation of synapses Figure 15shows that these new algorithms provide just a slightlylower learning speed than Ari for the cart-and-pole balanc-ing taskmdasha popular benchmark for global reinforcementwith delayed reward

6 PROSPECTS CHALLENGESAND OPTIONS

Though studies of possible CrossNet applications are inthe very beginning it looks like that these networks maybe used for performing virtually any cognitive task whichhad been demonstrated using software-implemented neu-ral nets at very high speed (with manageable power

Sci Adv Mater 3 322ndash331 2011 329

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IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Crossbar layer

Via translation layer

CMOS layer

Fig 16 Possible 3D hybrid circuit with area-distributed interface

consumption) This may enable at least two areas of Cross-Net applications(i) Relatively simple networks performing well-understood tasks (such as face recognition) at a very highspeedmdashsee Section 52 above(ii) Experimental networks used for high-performancestudies of novel neuromorphic algorithmsmdashboth for mod-eling certain cortical functions and for the implementationof more complex practical cognitive tasks such as datamining or autonomous robotic operation in complex andhostile environments

Moreover it is possible (though by no means guar-anteed) that in future CrossNet circuits will becomethe first hardware capable of challenging the mammal(human) cerebral cortex This opportunity may be evenmore enhanced by the recent suggestion of several quasi-3D40 and genuinely-3D41 versions of CMOL circuitsmdashseeeg Figure 16However in order for that to happen numerous issues

have to be resolved First of all the existing methodsof fabrication of crosspoint devices with latching-switchfunctionality have to be improved to increase their yieldand reduce device-to-device variability It may happen thatthe solution of this problem will require latching switcheswith a completely different physics of their operationmdashforexample based on single-electron tunneling in molecularself-assembled monolayers57

Second integration of hybrid circuits has to be demon-strated at much larger scale than it has been done so farwhich in turn may require facing several technologicalchallenges (such as fabrication of nanometer-sharp inter-connect pins at temperatures allowable at the back end ofCMOS stack)Last but not least new CrossNet architectures capa-

ble of performing more complex cognitive tasks have to

be suggested and exploredmdashpossibly assisted by modelingwith simpler CrossNet circuits

Acknowledgments Useful discussions with L AbbottP Adams R Douglass R Granger D HammerstromP Hasler G Hinton E Izhikevich J KrichmarC Lebiere Y LeCun J H Lee X Ma A MayrR Miikkulainen R OrsquoReilly T Sejnowski N SimonianG Snider N Srinivasa D Strukov Ouml Tuumlrel and R SWilliams as well as technical help by T S Singh aregratefully acknowledged

References and Notes

1 K Likharev A Mayr I Muckra and Ouml Tuumlrel Ann NY Acad Sci1006 146 (2003)

2 K K Likharev Interface 14 43 (2005)3 K K Likharev and D B Strukov CMOL Devices circuits and

architectures edited by G Cuniberti G Fagas and K Richter Intro-ducing Molecular Electronics Springer Berlin (2005) pp 447ndash477

4 K K Likharev J Nanoel Optoel 3 203 (2008)5 L O Chua IEEE Trans on Circuit Theory 18 507 (1971)6 G F Cerofolini and E Romano Appl Phys A 91 181 (2008)7 Q F Xia W Robinett M W Cumbie N Banerjee T J Cardinali

J J Yang W Wu X M Li W M Tong D B Strukov G SSnider G Medeiros-Ribeiro and R S Williams Nano Lett 9 3640(2009)

8 K K Likharev J Vac Sci Technol B 25 2531 (2007)9 L J Guo J Phys D 37 R123 (2004)10 D J Wagner and A H Jayatissa Proc SPIE 6002 136

(2005)11 M Bender A Fuchs U Plachetka and H Kurz Microel Eng

83 827 (2006)12 H H Solak J Phys DmdashAppl Phys 39 R171 (2006)13 B Q Wua and A Kumar J Vac Sci Technol B 25 1743

(2007)14 V Auzelyte C Dais P Farquet D Gruzmacher L J Heyderman

F Luo S Olliges C Padeste P K Sahoo T ThomsonA Turchanin C David and H H Solak J MicroNanolith MEMSMOEMS 8 3640 (2009)

15 I W Hamley Nanotechnology 14 R39 (2003)16 D Bratton D Yang J Y Dai and C K Ober Polymers for

Advanced Technologies 17 94 (2006)17 M N Kozicki IEEE Trans on Nanotechnology 4 331 (2005)18 R Waser and M Aono Nat Mater 6 833 (2007)19 I G Baek et al Multi-layer cross-point binary oxide resistive mem-

ory (OxRRAM) for post-NAND storage applications Tech DigestIEDMrsquo05 pp 750ndash753

20 S H Jo and W Lu Nano Lett 8 392 (2008)21 T W Kim H Choi S H Oh M Jo G Wang B Cho D Y Kim

H Hwang and T Lee Nanotechnology 20 art 025201 (2009)22 J Borghetti G S Snider P J Kuekes J J Yang D R Stewart

and R S Williams Nature 464 873 (2010)23 K K Likharev and D B Strukov Prospects for the development of

digital CMOL circuits Proc NanoArchrsquo07 pp 109ndash11624 D B Strukov and K K Likharev J Nanosci Nanotechnol 7 151

(2007)25 D B Strukov and K K Likharev Nanotechnology 16 888

(2005)26 D B Strukov and K K Likharev A reconfigurable architecture for

hybrid CMOSnanodevice circuits Proc FPGArsquo06 pp 131ndash14027 S Foumllling Ouml Tuumlrel and K Likharev Single-electron latching

switches as nanoscale synapses Proc IJCNNrsquo01 pp 216ndash221

330 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733

REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

to increase the probability of OFFrarr ON switching if thepre-synaptic and post-synaptic spikes are within a certaintime window (the latter spike follows the former one) andsuppress the probability in the opposite caseFigure 8 shows an simple example of how this can be

achieved in spiking CrossNets6 Each spike consists of twovoltage pulses a longer pulse A and a shorter but higherpulse B with the amplitude approaching (but somewhatbelow) the switching threshold Vt Applied to a compositesynapse (Fig 6) the former pulse creates a current pulsewhich causes a gradual RC-increase of the dendritic volt-age Vd (The contribution of pulse B to the recharging issmall due to its short duration)If the dendritic voltage was well below the spiking

threshold of the post-synaptic cell the dendritic wirerecharging decreases the net voltage V = VandashVd applied tothe crosspoint switches and hence creates a certain (small)probability of ON rarr OFF switching of those deviceswhich were in their ON state However if Vd was closeenough to the threshold the recharging triggers a sim-ilar spike in the post-synaptic neuron The somatic cir-cuitry sends this pulse not only to that somarsquos output(V prime

a but also back to the dendrite with the appropriate(negative) polarity Now the net voltage V is increasedso that when the short pulse B is applied to the axonicnanowire V exceeds the threshold creating a finite proba-bility of switching for those crosspoint devices of the com-posite synapse which were still in their OFF state (Similarschemes but with more complex somatic circuitry havebeen proposed in Refs [44ndash46])Unfortunately numerical modeling shows that this

scheme does not promise good scaling of STDP plastic-ity with growing connectivity M (Fig 9) The reason is

∆Gjk prop (Vjk)max

Vdj(t)gtVt

triggers spike

(k prime = 1hellipMndash1)

CVdj(t)

Va(tndash tk)

Gjk

Vjk(t)

Gjkprime Cf

Va(tndash tkprime)

Va(tndash tj)

inverter

t0 τ1 τ2 τ3

V1

V2

Va(t)

(a)

(b)

Fig 8 (a) The somatic circuit providing STDP and (b) the spike formused for simulations

ndash100 ndash50 0 50 100

20

21

22

23

Vm

axV

1

(tj ndash tk)τ0

M = 1024

Fig 9 Maximum synaptic voltage Vmax (which defines the STDPresponse) versus the time delay between the output (post-synaptic) spikeand the input (pre-synaptic) spike for a CrossNet with two-terminaldevices (Fig 8) for relatively high connectivity M Small black pointsraw results of 20000 numerical experiments with random spike timingred squares values of Vmax averaged within 25 0mdashwide time bins Otherparameters f0 = 001 0 = 10 = 20 = 10 (3 minus 20 = 01V2V1 = 2

(a)

(b)

from soma kprime

from soma k

Vgjprime Vdjprime Vgj Vdj

Vak

Vakprime

synapsejk

additionalgate wires

(one per cell)

∆Gjk

prop (Vjk)max

Vdj(t)gtVt

triggers spike

(kprime = 1hellipMndash1)

C

Vgj(t)

Gjk

Vjk(t)

Gjkprime

Vdj(t)

Va(tndash tk)

Va(tndash tkprime)

Va(tndash tj)

timesα

scalinginverter

from tosoma jprime

from tosoma jprime

Fig 10 The simplest Flash CrossNet (a) a 2times2 fragment of the synap-tic field and (b) the somatic circuit providing STDP adaptation

Sci Adv Mater 3 322ndash331 2011 327

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Table I Approximate bias conditions for crosspoint synapses based onstandard NAND flash memory cells

Electrode potentials(versus the p-well) Vak Vdk Vgj Vakprime Vdj prime Vgj prime

Spike propagation 0 V float 0 V +5 V float +5 Vwith STDP +spikes k minusspikes j +spikes kprime minusspikes j prime

Block reset 0 V 0 V minus15 V 0 V 0 V minus15 V(all Gjk larrGmax

Particular weight 0 V float +15 V +7 V Float 0 Vimport (Gjk larr 0)

that at the bio-plausible average rate f of spikes generatedby each cell may be as high as sim01 where is thespike duration so that the product Mf may be muchhigher than 1 meaning that at the input of each somamany spikes may overlap As a result the STDP responsebecomes noisy and its average deviates from the desiredantisymmetric function of the spike delayWays toward better scaling still have to explored here

let me only mention that these complications may benaturally avoided in ldquoFlash CrossNetsrdquomdashmodel circuitsusing flash memory cells working in the analog modemdashseeFigure 10 and Table I (Earlier suggestions of using flashtechnology in neuromorphic networks47ndash49 were based onmore complex cells)Figure 11 shows a typical result of theoretical analysis

of such flash synapses with the simple somatic feedbackcircuit shown in Figure 10(b) using both Monte Carlomodeling and an approximate quasi-analytical single-spike approximation (exact in the limit Mf rarr 0) Theresults indicate very good scaling of the STDP responseeven at Mf 1 limited only by the biologically-plausible condition f 1 due to a natural separationof the adjustment feedback signals Vg from feedforwarddendritic signals VdOf course the flash memory technology is essentially a

twist of CMOS so that it requires patterning with accurate

ndash15 ndash10 ndash5 0 502

03

04

05

a = 04τ1τ2 = 2Tτ2 = 10

ττ2 = 20

α = 08

Fig 11 Maximum source-to-gate voltage Vmax in a Flash CrossNet(Fig 10) versus the spike delay Small points simulation results fromsim2400 numerical experiments squaresmdashresults given by the single-spike approximation

layer alignment and cannot be scaled down as much asnanowire crossbars However in Flash CrossNets one flashcell may provide the synaptic weight accuracy compara-ble to that of a multi-latching-switch array (Figs 6 7)at a comparable network density (Suggestions50 to usecontinuously-adjusted memristive crosspoint devices forproviding analog synaptic weights would probably requiremuch lower device-to-device variability than the onedemonstrated experimentally)

5 APPLICATION EXAMPLES

The results presented in this section have been obtained byCrossNet simulation using their realistic models They givesome idea about possible performance of such networks

51 Hopfield Networks Pattern Recognition

Possibly the simplest type of an artificial neural net isthe recurrent firing-rate network with symmetric synap-tic weights wjk = wkj (Such networks had been exploredby several researchers51 before they were made famousby Hopfield52) Properly trained the Hopfield networkmay work as an associative memory using a part of apre-written patterns to restore (ldquorecognizerdquo) the wholepatternSince the capacity of such memory is very weakly

affected by synaptic weight discreteness a CrossNet withjust one latching switch per synapse may operate very wellin this mode its main difference from the generic Hop-field net is the quasi-local (rather than global) connectiv-ity M limiting its capacity to sim045 M at 99 restorationfidelity53

Figure 12 shows an example of such an operation thefinal image is completely error free However the mostremarkable feature of the pattern restoration is its speed(sim 5 RC) taking into account that in realistic CrossNetsthe RC time constant may be below 1 s (See Section 3above)

t RC = 0

Fig 12 Dynamics of recognition of one of three trained black-and-white images by an InBar-type CrossNet with 256times256 neural cellsand connectivity parameter M = 64 The initial image (left panel) wasobtained from the trained image (identical to the one shown in the rightpanel) by flipping as many as 40 of pixels at random RC is theeffective time constant of intercell interaction Reprinted with permissionfrom [53] Ouml Tuumlrel and K K Likharev Possible nanoelectronic imple-mentation of neuromorphic networks Proc IJCNNrsquo03 (2003) pp 365ndash370 copy 2003 IEEE

328 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733

REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

52 Multilayer Perceptrons Pattern Classification

A much more important but also more demandingfunction of neuromorphic networks is the pattern clas-sification which may be achieved for example inlayered perceptrons after their supervised training by errorbackpropagationmdashsee eg Refs [36ndash38] Two major con-cerns about using CrossNets in this mode have been(i) the necessary accuracy of synaptic weights and(ii) defect tolerance

Figure 13 shows typical results of study32 which useda very common benchmarkmdashthe MNIST database oftypewritten characters54 It shows that for exampleL= 33 synaptic levels (available from two 4times4 compos-ite synapses shown in Fig 6) are sufficient for gettingvirtually the same fidelity (sim98) as for exact (contin-uous) synaptic weights and that a very substantial num-ber of stuck-at-closed defects cause only a slow fidelitydegradationThese results pertain to weights imported from a pre-

cursor network this training method is quite sufficient forexample for a known face recognition in a large crowdbecause it may be based on using multiple copies of thedesired pattern with a TV-raster-type search (Fig 14)Estimates have shown55 that such a CrossNet chip witharea below 1 cm2 may identify a face on a 8-Mpixel imagein approximately 100 s the number to be compared withsim103 s for the same algorithm run on a general-purposemicroprocessor

53 Global Reinforcement and TD Learning

Some cognitive tasks require unsupervised learning inparticular global reinforcement with either instant or

00 01 02 03 04 05 06001

01

Cla

ssifi

catio

n er

ror

frac

tion

Defect fraction q

L = 73D

L = 51D

L = 33DL = 73C

L = 51CL = 33CC Continuous-weight precursor

D Discrete-weight precursor

Fig 13 The MNIST set classification error of CrossNets with weightsimported from a discrete-weight precursor network as a function of thefraction of bad nanodevices in comparison with that for the continuous-weight precursor results L is the number of discrete weight levelsReprinted with permission from [32] J H Lee and K K Likharev IntJ Circuit Theory App 35 239 (2007) copy 2007 John Wiley amp Sons Ltd

w

h

ImagePanel k

Input ofnetwork

processingpanel k

Fig 14 Scan mapping of the input image on CrossNet inputs Red linesshow the possible time sequence of image pixels sent to a certain inputof the network processing image from the upper-left panel of the pattern

Fig 15 Dynamics of learning to balance the cart-pole system (seeinset) using three synaptic weight adaptation rules (All results wereaveraged over 20 independent experiments) Reprinted with permissionfrom [33] X Ma and K K Likharev IEEE Trans on Neural Networks18 573 (2007) copy 2007 IEEE

delayed reward36ndash3856 A study of this mode of CrossNetoperation33 has shown that these networks are quite suit-able for the most popular global-reinforcement algorithmssuch as Ari

56 Moreover they may use similar algorithms(which have been called A1 and A1 based on synap-tic rather than somatic randomness which are more natu-ral for nanodevice implementation of synapses Figure 15shows that these new algorithms provide just a slightlylower learning speed than Ari for the cart-and-pole balanc-ing taskmdasha popular benchmark for global reinforcementwith delayed reward

6 PROSPECTS CHALLENGESAND OPTIONS

Though studies of possible CrossNet applications are inthe very beginning it looks like that these networks maybe used for performing virtually any cognitive task whichhad been demonstrated using software-implemented neu-ral nets at very high speed (with manageable power

Sci Adv Mater 3 322ndash331 2011 329

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Crossbar layer

Via translation layer

CMOS layer

Fig 16 Possible 3D hybrid circuit with area-distributed interface

consumption) This may enable at least two areas of Cross-Net applications(i) Relatively simple networks performing well-understood tasks (such as face recognition) at a very highspeedmdashsee Section 52 above(ii) Experimental networks used for high-performancestudies of novel neuromorphic algorithmsmdashboth for mod-eling certain cortical functions and for the implementationof more complex practical cognitive tasks such as datamining or autonomous robotic operation in complex andhostile environments

Moreover it is possible (though by no means guar-anteed) that in future CrossNet circuits will becomethe first hardware capable of challenging the mammal(human) cerebral cortex This opportunity may be evenmore enhanced by the recent suggestion of several quasi-3D40 and genuinely-3D41 versions of CMOL circuitsmdashseeeg Figure 16However in order for that to happen numerous issues

have to be resolved First of all the existing methodsof fabrication of crosspoint devices with latching-switchfunctionality have to be improved to increase their yieldand reduce device-to-device variability It may happen thatthe solution of this problem will require latching switcheswith a completely different physics of their operationmdashforexample based on single-electron tunneling in molecularself-assembled monolayers57

Second integration of hybrid circuits has to be demon-strated at much larger scale than it has been done so farwhich in turn may require facing several technologicalchallenges (such as fabrication of nanometer-sharp inter-connect pins at temperatures allowable at the back end ofCMOS stack)Last but not least new CrossNet architectures capa-

ble of performing more complex cognitive tasks have to

be suggested and exploredmdashpossibly assisted by modelingwith simpler CrossNet circuits

Acknowledgments Useful discussions with L AbbottP Adams R Douglass R Granger D HammerstromP Hasler G Hinton E Izhikevich J KrichmarC Lebiere Y LeCun J H Lee X Ma A MayrR Miikkulainen R OrsquoReilly T Sejnowski N SimonianG Snider N Srinivasa D Strukov Ouml Tuumlrel and R SWilliams as well as technical help by T S Singh aregratefully acknowledged

References and Notes

1 K Likharev A Mayr I Muckra and Ouml Tuumlrel Ann NY Acad Sci1006 146 (2003)

2 K K Likharev Interface 14 43 (2005)3 K K Likharev and D B Strukov CMOL Devices circuits and

architectures edited by G Cuniberti G Fagas and K Richter Intro-ducing Molecular Electronics Springer Berlin (2005) pp 447ndash477

4 K K Likharev J Nanoel Optoel 3 203 (2008)5 L O Chua IEEE Trans on Circuit Theory 18 507 (1971)6 G F Cerofolini and E Romano Appl Phys A 91 181 (2008)7 Q F Xia W Robinett M W Cumbie N Banerjee T J Cardinali

J J Yang W Wu X M Li W M Tong D B Strukov G SSnider G Medeiros-Ribeiro and R S Williams Nano Lett 9 3640(2009)

8 K K Likharev J Vac Sci Technol B 25 2531 (2007)9 L J Guo J Phys D 37 R123 (2004)10 D J Wagner and A H Jayatissa Proc SPIE 6002 136

(2005)11 M Bender A Fuchs U Plachetka and H Kurz Microel Eng

83 827 (2006)12 H H Solak J Phys DmdashAppl Phys 39 R171 (2006)13 B Q Wua and A Kumar J Vac Sci Technol B 25 1743

(2007)14 V Auzelyte C Dais P Farquet D Gruzmacher L J Heyderman

F Luo S Olliges C Padeste P K Sahoo T ThomsonA Turchanin C David and H H Solak J MicroNanolith MEMSMOEMS 8 3640 (2009)

15 I W Hamley Nanotechnology 14 R39 (2003)16 D Bratton D Yang J Y Dai and C K Ober Polymers for

Advanced Technologies 17 94 (2006)17 M N Kozicki IEEE Trans on Nanotechnology 4 331 (2005)18 R Waser and M Aono Nat Mater 6 833 (2007)19 I G Baek et al Multi-layer cross-point binary oxide resistive mem-

ory (OxRRAM) for post-NAND storage applications Tech DigestIEDMrsquo05 pp 750ndash753

20 S H Jo and W Lu Nano Lett 8 392 (2008)21 T W Kim H Choi S H Oh M Jo G Wang B Cho D Y Kim

H Hwang and T Lee Nanotechnology 20 art 025201 (2009)22 J Borghetti G S Snider P J Kuekes J J Yang D R Stewart

and R S Williams Nature 464 873 (2010)23 K K Likharev and D B Strukov Prospects for the development of

digital CMOL circuits Proc NanoArchrsquo07 pp 109ndash11624 D B Strukov and K K Likharev J Nanosci Nanotechnol 7 151

(2007)25 D B Strukov and K K Likharev Nanotechnology 16 888

(2005)26 D B Strukov and K K Likharev A reconfigurable architecture for

hybrid CMOSnanodevice circuits Proc FPGArsquo06 pp 131ndash14027 S Foumllling Ouml Tuumlrel and K Likharev Single-electron latching

switches as nanoscale synapses Proc IJCNNrsquo01 pp 216ndash221

330 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Table I Approximate bias conditions for crosspoint synapses based onstandard NAND flash memory cells

Electrode potentials(versus the p-well) Vak Vdk Vgj Vakprime Vdj prime Vgj prime

Spike propagation 0 V float 0 V +5 V float +5 Vwith STDP +spikes k minusspikes j +spikes kprime minusspikes j prime

Block reset 0 V 0 V minus15 V 0 V 0 V minus15 V(all Gjk larrGmax

Particular weight 0 V float +15 V +7 V Float 0 Vimport (Gjk larr 0)

that at the bio-plausible average rate f of spikes generatedby each cell may be as high as sim01 where is thespike duration so that the product Mf may be muchhigher than 1 meaning that at the input of each somamany spikes may overlap As a result the STDP responsebecomes noisy and its average deviates from the desiredantisymmetric function of the spike delayWays toward better scaling still have to explored here

let me only mention that these complications may benaturally avoided in ldquoFlash CrossNetsrdquomdashmodel circuitsusing flash memory cells working in the analog modemdashseeFigure 10 and Table I (Earlier suggestions of using flashtechnology in neuromorphic networks47ndash49 were based onmore complex cells)Figure 11 shows a typical result of theoretical analysis

of such flash synapses with the simple somatic feedbackcircuit shown in Figure 10(b) using both Monte Carlomodeling and an approximate quasi-analytical single-spike approximation (exact in the limit Mf rarr 0) Theresults indicate very good scaling of the STDP responseeven at Mf 1 limited only by the biologically-plausible condition f 1 due to a natural separationof the adjustment feedback signals Vg from feedforwarddendritic signals VdOf course the flash memory technology is essentially a

twist of CMOS so that it requires patterning with accurate

ndash15 ndash10 ndash5 0 502

03

04

05

a = 04τ1τ2 = 2Tτ2 = 10

ττ2 = 20

α = 08

Fig 11 Maximum source-to-gate voltage Vmax in a Flash CrossNet(Fig 10) versus the spike delay Small points simulation results fromsim2400 numerical experiments squaresmdashresults given by the single-spike approximation

layer alignment and cannot be scaled down as much asnanowire crossbars However in Flash CrossNets one flashcell may provide the synaptic weight accuracy compara-ble to that of a multi-latching-switch array (Figs 6 7)at a comparable network density (Suggestions50 to usecontinuously-adjusted memristive crosspoint devices forproviding analog synaptic weights would probably requiremuch lower device-to-device variability than the onedemonstrated experimentally)

5 APPLICATION EXAMPLES

The results presented in this section have been obtained byCrossNet simulation using their realistic models They givesome idea about possible performance of such networks

51 Hopfield Networks Pattern Recognition

Possibly the simplest type of an artificial neural net isthe recurrent firing-rate network with symmetric synap-tic weights wjk = wkj (Such networks had been exploredby several researchers51 before they were made famousby Hopfield52) Properly trained the Hopfield networkmay work as an associative memory using a part of apre-written patterns to restore (ldquorecognizerdquo) the wholepatternSince the capacity of such memory is very weakly

affected by synaptic weight discreteness a CrossNet withjust one latching switch per synapse may operate very wellin this mode its main difference from the generic Hop-field net is the quasi-local (rather than global) connectiv-ity M limiting its capacity to sim045 M at 99 restorationfidelity53

Figure 12 shows an example of such an operation thefinal image is completely error free However the mostremarkable feature of the pattern restoration is its speed(sim 5 RC) taking into account that in realistic CrossNetsthe RC time constant may be below 1 s (See Section 3above)

t RC = 0

Fig 12 Dynamics of recognition of one of three trained black-and-white images by an InBar-type CrossNet with 256times256 neural cellsand connectivity parameter M = 64 The initial image (left panel) wasobtained from the trained image (identical to the one shown in the rightpanel) by flipping as many as 40 of pixels at random RC is theeffective time constant of intercell interaction Reprinted with permissionfrom [53] Ouml Tuumlrel and K K Likharev Possible nanoelectronic imple-mentation of neuromorphic networks Proc IJCNNrsquo03 (2003) pp 365ndash370 copy 2003 IEEE

328 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733

REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

52 Multilayer Perceptrons Pattern Classification

A much more important but also more demandingfunction of neuromorphic networks is the pattern clas-sification which may be achieved for example inlayered perceptrons after their supervised training by errorbackpropagationmdashsee eg Refs [36ndash38] Two major con-cerns about using CrossNets in this mode have been(i) the necessary accuracy of synaptic weights and(ii) defect tolerance

Figure 13 shows typical results of study32 which useda very common benchmarkmdashthe MNIST database oftypewritten characters54 It shows that for exampleL= 33 synaptic levels (available from two 4times4 compos-ite synapses shown in Fig 6) are sufficient for gettingvirtually the same fidelity (sim98) as for exact (contin-uous) synaptic weights and that a very substantial num-ber of stuck-at-closed defects cause only a slow fidelitydegradationThese results pertain to weights imported from a pre-

cursor network this training method is quite sufficient forexample for a known face recognition in a large crowdbecause it may be based on using multiple copies of thedesired pattern with a TV-raster-type search (Fig 14)Estimates have shown55 that such a CrossNet chip witharea below 1 cm2 may identify a face on a 8-Mpixel imagein approximately 100 s the number to be compared withsim103 s for the same algorithm run on a general-purposemicroprocessor

53 Global Reinforcement and TD Learning

Some cognitive tasks require unsupervised learning inparticular global reinforcement with either instant or

00 01 02 03 04 05 06001

01

Cla

ssifi

catio

n er

ror

frac

tion

Defect fraction q

L = 73D

L = 51D

L = 33DL = 73C

L = 51CL = 33CC Continuous-weight precursor

D Discrete-weight precursor

Fig 13 The MNIST set classification error of CrossNets with weightsimported from a discrete-weight precursor network as a function of thefraction of bad nanodevices in comparison with that for the continuous-weight precursor results L is the number of discrete weight levelsReprinted with permission from [32] J H Lee and K K Likharev IntJ Circuit Theory App 35 239 (2007) copy 2007 John Wiley amp Sons Ltd

w

h

ImagePanel k

Input ofnetwork

processingpanel k

Fig 14 Scan mapping of the input image on CrossNet inputs Red linesshow the possible time sequence of image pixels sent to a certain inputof the network processing image from the upper-left panel of the pattern

Fig 15 Dynamics of learning to balance the cart-pole system (seeinset) using three synaptic weight adaptation rules (All results wereaveraged over 20 independent experiments) Reprinted with permissionfrom [33] X Ma and K K Likharev IEEE Trans on Neural Networks18 573 (2007) copy 2007 IEEE

delayed reward36ndash3856 A study of this mode of CrossNetoperation33 has shown that these networks are quite suit-able for the most popular global-reinforcement algorithmssuch as Ari

56 Moreover they may use similar algorithms(which have been called A1 and A1 based on synap-tic rather than somatic randomness which are more natu-ral for nanodevice implementation of synapses Figure 15shows that these new algorithms provide just a slightlylower learning speed than Ari for the cart-and-pole balanc-ing taskmdasha popular benchmark for global reinforcementwith delayed reward

6 PROSPECTS CHALLENGESAND OPTIONS

Though studies of possible CrossNet applications are inthe very beginning it looks like that these networks maybe used for performing virtually any cognitive task whichhad been demonstrated using software-implemented neu-ral nets at very high speed (with manageable power

Sci Adv Mater 3 322ndash331 2011 329

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Crossbar layer

Via translation layer

CMOS layer

Fig 16 Possible 3D hybrid circuit with area-distributed interface

consumption) This may enable at least two areas of Cross-Net applications(i) Relatively simple networks performing well-understood tasks (such as face recognition) at a very highspeedmdashsee Section 52 above(ii) Experimental networks used for high-performancestudies of novel neuromorphic algorithmsmdashboth for mod-eling certain cortical functions and for the implementationof more complex practical cognitive tasks such as datamining or autonomous robotic operation in complex andhostile environments

Moreover it is possible (though by no means guar-anteed) that in future CrossNet circuits will becomethe first hardware capable of challenging the mammal(human) cerebral cortex This opportunity may be evenmore enhanced by the recent suggestion of several quasi-3D40 and genuinely-3D41 versions of CMOL circuitsmdashseeeg Figure 16However in order for that to happen numerous issues

have to be resolved First of all the existing methodsof fabrication of crosspoint devices with latching-switchfunctionality have to be improved to increase their yieldand reduce device-to-device variability It may happen thatthe solution of this problem will require latching switcheswith a completely different physics of their operationmdashforexample based on single-electron tunneling in molecularself-assembled monolayers57

Second integration of hybrid circuits has to be demon-strated at much larger scale than it has been done so farwhich in turn may require facing several technologicalchallenges (such as fabrication of nanometer-sharp inter-connect pins at temperatures allowable at the back end ofCMOS stack)Last but not least new CrossNet architectures capa-

ble of performing more complex cognitive tasks have to

be suggested and exploredmdashpossibly assisted by modelingwith simpler CrossNet circuits

Acknowledgments Useful discussions with L AbbottP Adams R Douglass R Granger D HammerstromP Hasler G Hinton E Izhikevich J KrichmarC Lebiere Y LeCun J H Lee X Ma A MayrR Miikkulainen R OrsquoReilly T Sejnowski N SimonianG Snider N Srinivasa D Strukov Ouml Tuumlrel and R SWilliams as well as technical help by T S Singh aregratefully acknowledged

References and Notes

1 K Likharev A Mayr I Muckra and Ouml Tuumlrel Ann NY Acad Sci1006 146 (2003)

2 K K Likharev Interface 14 43 (2005)3 K K Likharev and D B Strukov CMOL Devices circuits and

architectures edited by G Cuniberti G Fagas and K Richter Intro-ducing Molecular Electronics Springer Berlin (2005) pp 447ndash477

4 K K Likharev J Nanoel Optoel 3 203 (2008)5 L O Chua IEEE Trans on Circuit Theory 18 507 (1971)6 G F Cerofolini and E Romano Appl Phys A 91 181 (2008)7 Q F Xia W Robinett M W Cumbie N Banerjee T J Cardinali

J J Yang W Wu X M Li W M Tong D B Strukov G SSnider G Medeiros-Ribeiro and R S Williams Nano Lett 9 3640(2009)

8 K K Likharev J Vac Sci Technol B 25 2531 (2007)9 L J Guo J Phys D 37 R123 (2004)10 D J Wagner and A H Jayatissa Proc SPIE 6002 136

(2005)11 M Bender A Fuchs U Plachetka and H Kurz Microel Eng

83 827 (2006)12 H H Solak J Phys DmdashAppl Phys 39 R171 (2006)13 B Q Wua and A Kumar J Vac Sci Technol B 25 1743

(2007)14 V Auzelyte C Dais P Farquet D Gruzmacher L J Heyderman

F Luo S Olliges C Padeste P K Sahoo T ThomsonA Turchanin C David and H H Solak J MicroNanolith MEMSMOEMS 8 3640 (2009)

15 I W Hamley Nanotechnology 14 R39 (2003)16 D Bratton D Yang J Y Dai and C K Ober Polymers for

Advanced Technologies 17 94 (2006)17 M N Kozicki IEEE Trans on Nanotechnology 4 331 (2005)18 R Waser and M Aono Nat Mater 6 833 (2007)19 I G Baek et al Multi-layer cross-point binary oxide resistive mem-

ory (OxRRAM) for post-NAND storage applications Tech DigestIEDMrsquo05 pp 750ndash753

20 S H Jo and W Lu Nano Lett 8 392 (2008)21 T W Kim H Choi S H Oh M Jo G Wang B Cho D Y Kim

H Hwang and T Lee Nanotechnology 20 art 025201 (2009)22 J Borghetti G S Snider P J Kuekes J J Yang D R Stewart

and R S Williams Nature 464 873 (2010)23 K K Likharev and D B Strukov Prospects for the development of

digital CMOL circuits Proc NanoArchrsquo07 pp 109ndash11624 D B Strukov and K K Likharev J Nanosci Nanotechnol 7 151

(2007)25 D B Strukov and K K Likharev Nanotechnology 16 888

(2005)26 D B Strukov and K K Likharev A reconfigurable architecture for

hybrid CMOSnanodevice circuits Proc FPGArsquo06 pp 131ndash14027 S Foumllling Ouml Tuumlrel and K Likharev Single-electron latching

switches as nanoscale synapses Proc IJCNNrsquo01 pp 216ndash221

330 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733

REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

52 Multilayer Perceptrons Pattern Classification

A much more important but also more demandingfunction of neuromorphic networks is the pattern clas-sification which may be achieved for example inlayered perceptrons after their supervised training by errorbackpropagationmdashsee eg Refs [36ndash38] Two major con-cerns about using CrossNets in this mode have been(i) the necessary accuracy of synaptic weights and(ii) defect tolerance

Figure 13 shows typical results of study32 which useda very common benchmarkmdashthe MNIST database oftypewritten characters54 It shows that for exampleL= 33 synaptic levels (available from two 4times4 compos-ite synapses shown in Fig 6) are sufficient for gettingvirtually the same fidelity (sim98) as for exact (contin-uous) synaptic weights and that a very substantial num-ber of stuck-at-closed defects cause only a slow fidelitydegradationThese results pertain to weights imported from a pre-

cursor network this training method is quite sufficient forexample for a known face recognition in a large crowdbecause it may be based on using multiple copies of thedesired pattern with a TV-raster-type search (Fig 14)Estimates have shown55 that such a CrossNet chip witharea below 1 cm2 may identify a face on a 8-Mpixel imagein approximately 100 s the number to be compared withsim103 s for the same algorithm run on a general-purposemicroprocessor

53 Global Reinforcement and TD Learning

Some cognitive tasks require unsupervised learning inparticular global reinforcement with either instant or

00 01 02 03 04 05 06001

01

Cla

ssifi

catio

n er

ror

frac

tion

Defect fraction q

L = 73D

L = 51D

L = 33DL = 73C

L = 51CL = 33CC Continuous-weight precursor

D Discrete-weight precursor

Fig 13 The MNIST set classification error of CrossNets with weightsimported from a discrete-weight precursor network as a function of thefraction of bad nanodevices in comparison with that for the continuous-weight precursor results L is the number of discrete weight levelsReprinted with permission from [32] J H Lee and K K Likharev IntJ Circuit Theory App 35 239 (2007) copy 2007 John Wiley amp Sons Ltd

w

h

ImagePanel k

Input ofnetwork

processingpanel k

Fig 14 Scan mapping of the input image on CrossNet inputs Red linesshow the possible time sequence of image pixels sent to a certain inputof the network processing image from the upper-left panel of the pattern

Fig 15 Dynamics of learning to balance the cart-pole system (seeinset) using three synaptic weight adaptation rules (All results wereaveraged over 20 independent experiments) Reprinted with permissionfrom [33] X Ma and K K Likharev IEEE Trans on Neural Networks18 573 (2007) copy 2007 IEEE

delayed reward36ndash3856 A study of this mode of CrossNetoperation33 has shown that these networks are quite suit-able for the most popular global-reinforcement algorithmssuch as Ari

56 Moreover they may use similar algorithms(which have been called A1 and A1 based on synap-tic rather than somatic randomness which are more natu-ral for nanodevice implementation of synapses Figure 15shows that these new algorithms provide just a slightlylower learning speed than Ari for the cart-and-pole balanc-ing taskmdasha popular benchmark for global reinforcementwith delayed reward

6 PROSPECTS CHALLENGESAND OPTIONS

Though studies of possible CrossNet applications are inthe very beginning it looks like that these networks maybe used for performing virtually any cognitive task whichhad been demonstrated using software-implemented neu-ral nets at very high speed (with manageable power

Sci Adv Mater 3 322ndash331 2011 329

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Crossbar layer

Via translation layer

CMOS layer

Fig 16 Possible 3D hybrid circuit with area-distributed interface

consumption) This may enable at least two areas of Cross-Net applications(i) Relatively simple networks performing well-understood tasks (such as face recognition) at a very highspeedmdashsee Section 52 above(ii) Experimental networks used for high-performancestudies of novel neuromorphic algorithmsmdashboth for mod-eling certain cortical functions and for the implementationof more complex practical cognitive tasks such as datamining or autonomous robotic operation in complex andhostile environments

Moreover it is possible (though by no means guar-anteed) that in future CrossNet circuits will becomethe first hardware capable of challenging the mammal(human) cerebral cortex This opportunity may be evenmore enhanced by the recent suggestion of several quasi-3D40 and genuinely-3D41 versions of CMOL circuitsmdashseeeg Figure 16However in order for that to happen numerous issues

have to be resolved First of all the existing methodsof fabrication of crosspoint devices with latching-switchfunctionality have to be improved to increase their yieldand reduce device-to-device variability It may happen thatthe solution of this problem will require latching switcheswith a completely different physics of their operationmdashforexample based on single-electron tunneling in molecularself-assembled monolayers57

Second integration of hybrid circuits has to be demon-strated at much larger scale than it has been done so farwhich in turn may require facing several technologicalchallenges (such as fabrication of nanometer-sharp inter-connect pins at temperatures allowable at the back end ofCMOS stack)Last but not least new CrossNet architectures capa-

ble of performing more complex cognitive tasks have to

be suggested and exploredmdashpossibly assisted by modelingwith simpler CrossNet circuits

Acknowledgments Useful discussions with L AbbottP Adams R Douglass R Granger D HammerstromP Hasler G Hinton E Izhikevich J KrichmarC Lebiere Y LeCun J H Lee X Ma A MayrR Miikkulainen R OrsquoReilly T Sejnowski N SimonianG Snider N Srinivasa D Strukov Ouml Tuumlrel and R SWilliams as well as technical help by T S Singh aregratefully acknowledged

References and Notes

1 K Likharev A Mayr I Muckra and Ouml Tuumlrel Ann NY Acad Sci1006 146 (2003)

2 K K Likharev Interface 14 43 (2005)3 K K Likharev and D B Strukov CMOL Devices circuits and

architectures edited by G Cuniberti G Fagas and K Richter Intro-ducing Molecular Electronics Springer Berlin (2005) pp 447ndash477

4 K K Likharev J Nanoel Optoel 3 203 (2008)5 L O Chua IEEE Trans on Circuit Theory 18 507 (1971)6 G F Cerofolini and E Romano Appl Phys A 91 181 (2008)7 Q F Xia W Robinett M W Cumbie N Banerjee T J Cardinali

J J Yang W Wu X M Li W M Tong D B Strukov G SSnider G Medeiros-Ribeiro and R S Williams Nano Lett 9 3640(2009)

8 K K Likharev J Vac Sci Technol B 25 2531 (2007)9 L J Guo J Phys D 37 R123 (2004)10 D J Wagner and A H Jayatissa Proc SPIE 6002 136

(2005)11 M Bender A Fuchs U Plachetka and H Kurz Microel Eng

83 827 (2006)12 H H Solak J Phys DmdashAppl Phys 39 R171 (2006)13 B Q Wua and A Kumar J Vac Sci Technol B 25 1743

(2007)14 V Auzelyte C Dais P Farquet D Gruzmacher L J Heyderman

F Luo S Olliges C Padeste P K Sahoo T ThomsonA Turchanin C David and H H Solak J MicroNanolith MEMSMOEMS 8 3640 (2009)

15 I W Hamley Nanotechnology 14 R39 (2003)16 D Bratton D Yang J Y Dai and C K Ober Polymers for

Advanced Technologies 17 94 (2006)17 M N Kozicki IEEE Trans on Nanotechnology 4 331 (2005)18 R Waser and M Aono Nat Mater 6 833 (2007)19 I G Baek et al Multi-layer cross-point binary oxide resistive mem-

ory (OxRRAM) for post-NAND storage applications Tech DigestIEDMrsquo05 pp 750ndash753

20 S H Jo and W Lu Nano Lett 8 392 (2008)21 T W Kim H Choi S H Oh M Jo G Wang B Cho D Y Kim

H Hwang and T Lee Nanotechnology 20 art 025201 (2009)22 J Borghetti G S Snider P J Kuekes J J Yang D R Stewart

and R S Williams Nature 464 873 (2010)23 K K Likharev and D B Strukov Prospects for the development of

digital CMOL circuits Proc NanoArchrsquo07 pp 109ndash11624 D B Strukov and K K Likharev J Nanosci Nanotechnol 7 151

(2007)25 D B Strukov and K K Likharev Nanotechnology 16 888

(2005)26 D B Strukov and K K Likharev A reconfigurable architecture for

hybrid CMOSnanodevice circuits Proc FPGArsquo06 pp 131ndash14027 S Foumllling Ouml Tuumlrel and K Likharev Single-electron latching

switches as nanoscale synapses Proc IJCNNrsquo01 pp 216ndash221

330 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733R

EVIEW

CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks Likharev

Crossbar layer

Via translation layer

CMOS layer

Fig 16 Possible 3D hybrid circuit with area-distributed interface

consumption) This may enable at least two areas of Cross-Net applications(i) Relatively simple networks performing well-understood tasks (such as face recognition) at a very highspeedmdashsee Section 52 above(ii) Experimental networks used for high-performancestudies of novel neuromorphic algorithmsmdashboth for mod-eling certain cortical functions and for the implementationof more complex practical cognitive tasks such as datamining or autonomous robotic operation in complex andhostile environments

Moreover it is possible (though by no means guar-anteed) that in future CrossNet circuits will becomethe first hardware capable of challenging the mammal(human) cerebral cortex This opportunity may be evenmore enhanced by the recent suggestion of several quasi-3D40 and genuinely-3D41 versions of CMOL circuitsmdashseeeg Figure 16However in order for that to happen numerous issues

have to be resolved First of all the existing methodsof fabrication of crosspoint devices with latching-switchfunctionality have to be improved to increase their yieldand reduce device-to-device variability It may happen thatthe solution of this problem will require latching switcheswith a completely different physics of their operationmdashforexample based on single-electron tunneling in molecularself-assembled monolayers57

Second integration of hybrid circuits has to be demon-strated at much larger scale than it has been done so farwhich in turn may require facing several technologicalchallenges (such as fabrication of nanometer-sharp inter-connect pins at temperatures allowable at the back end ofCMOS stack)Last but not least new CrossNet architectures capa-

ble of performing more complex cognitive tasks have to

be suggested and exploredmdashpossibly assisted by modelingwith simpler CrossNet circuits

Acknowledgments Useful discussions with L AbbottP Adams R Douglass R Granger D HammerstromP Hasler G Hinton E Izhikevich J KrichmarC Lebiere Y LeCun J H Lee X Ma A MayrR Miikkulainen R OrsquoReilly T Sejnowski N SimonianG Snider N Srinivasa D Strukov Ouml Tuumlrel and R SWilliams as well as technical help by T S Singh aregratefully acknowledged

References and Notes

1 K Likharev A Mayr I Muckra and Ouml Tuumlrel Ann NY Acad Sci1006 146 (2003)

2 K K Likharev Interface 14 43 (2005)3 K K Likharev and D B Strukov CMOL Devices circuits and

architectures edited by G Cuniberti G Fagas and K Richter Intro-ducing Molecular Electronics Springer Berlin (2005) pp 447ndash477

4 K K Likharev J Nanoel Optoel 3 203 (2008)5 L O Chua IEEE Trans on Circuit Theory 18 507 (1971)6 G F Cerofolini and E Romano Appl Phys A 91 181 (2008)7 Q F Xia W Robinett M W Cumbie N Banerjee T J Cardinali

J J Yang W Wu X M Li W M Tong D B Strukov G SSnider G Medeiros-Ribeiro and R S Williams Nano Lett 9 3640(2009)

8 K K Likharev J Vac Sci Technol B 25 2531 (2007)9 L J Guo J Phys D 37 R123 (2004)10 D J Wagner and A H Jayatissa Proc SPIE 6002 136

(2005)11 M Bender A Fuchs U Plachetka and H Kurz Microel Eng

83 827 (2006)12 H H Solak J Phys DmdashAppl Phys 39 R171 (2006)13 B Q Wua and A Kumar J Vac Sci Technol B 25 1743

(2007)14 V Auzelyte C Dais P Farquet D Gruzmacher L J Heyderman

F Luo S Olliges C Padeste P K Sahoo T ThomsonA Turchanin C David and H H Solak J MicroNanolith MEMSMOEMS 8 3640 (2009)

15 I W Hamley Nanotechnology 14 R39 (2003)16 D Bratton D Yang J Y Dai and C K Ober Polymers for

Advanced Technologies 17 94 (2006)17 M N Kozicki IEEE Trans on Nanotechnology 4 331 (2005)18 R Waser and M Aono Nat Mater 6 833 (2007)19 I G Baek et al Multi-layer cross-point binary oxide resistive mem-

ory (OxRRAM) for post-NAND storage applications Tech DigestIEDMrsquo05 pp 750ndash753

20 S H Jo and W Lu Nano Lett 8 392 (2008)21 T W Kim H Choi S H Oh M Jo G Wang B Cho D Y Kim

H Hwang and T Lee Nanotechnology 20 art 025201 (2009)22 J Borghetti G S Snider P J Kuekes J J Yang D R Stewart

and R S Williams Nature 464 873 (2010)23 K K Likharev and D B Strukov Prospects for the development of

digital CMOL circuits Proc NanoArchrsquo07 pp 109ndash11624 D B Strukov and K K Likharev J Nanosci Nanotechnol 7 151

(2007)25 D B Strukov and K K Likharev Nanotechnology 16 888

(2005)26 D B Strukov and K K Likharev A reconfigurable architecture for

hybrid CMOSnanodevice circuits Proc FPGArsquo06 pp 131ndash14027 S Foumllling Ouml Tuumlrel and K Likharev Single-electron latching

switches as nanoscale synapses Proc IJCNNrsquo01 pp 216ndash221

330 Sci Adv Mater 3 322ndash331 2011

Delivered by Ingenta toSUNY at Stony Brook Main Library

IP 1294956157Sat 02 Jul 2011 132733

REVIEW

Likharev CrossNets Neuromorphic Hybrid CMOSNanoelectronic Networks

28 Ouml Tuumlrel and K K Likharev Int J of Circuit Theory Appl 31 34(2003)

29 Ouml Tuumlrel J H Lee X L Ma and K K Likharev Int J CircTheory App 32 277 (2004)

30 J H Lee and K K Likharev In situ training of CMOL CrossNetsProc WCCIIJCNNrsquo06 pp 5026ndash5034

31 J H Lee X Ma and K K Likharev CMOL CrossNets Possibleneuromorphic nanoelectronic circuits Advances in Neural Informa-tion Processing Systems 18 edited by Y Weiss B Scholkopf andJ Platt MIT Press Cambridge MA (2006) pp 755ndash762

32 J H Lee and K K Likharev Int J Circuit Theory App 35 239(2007)

33 X Ma and K K Likharev IEEE Trans on Neural Networks 18 573(2007)

34 C J Gao and D Hammerstrom IEEE Trans on Circuits and Sys-tems 54 2502 (2007)

35 M S Zaveri and D Hammerstrom IEEE Trans on Nanotechnology9 194 (2010)

36 J Hertz A Krogh and R G Palmer Introduction to the Theory ofNeural Computation Perseus Cambridge MA (1991)

37 S Haykin Neural Networks 2nd edn Upper Saddle River Prentice-Hall NJ (1999)

38 P Dayan and L F Abbott Theoretical Neuroscience MIT PressCambridge MA (2001)

39 V B Mountcastle The Cerebral Cortex Harvard U PressCambridge MA (1998)

40 D Tu M Liu W Wang and S Haruehanroengra Micro amp NanoLett 2 40 (2007)

41 D B Strukov and R S Willams Proc Nat Acad Sci 106 20155(2009)

42 H Markram J Lubke M Frotscher and B Sakmann Science275 213 (1997)

43 R J Williams Mach Learn 8 229 (1992)44 G S Snider Spike-timing-dependent learning in memristive nano-

devices Proc NanoArchrsquo08 (2008) pp 85ndash9245 B Linares-Barranco and T Serrano-Gotarredona Nature Precedings

(2009)46 A Afifi A Ayatollahi and R Rassi IEICE Electronics Express

6 148 (2009)47 J Alspector and R B Allen Neuromorphic VLSI learning system

Proc 1987 Stanford Conf on Adv Res in VLSI (1987) pp 313ndash34948 M Holler S Tam H Castro and R Benson An electrically train-

able artificial neural network (ETANN) with 10240 lsquofloating gatersquosynapses Proc IJCNNrsquo89 pp 191ndash196

49 S Ramakrishnan P Hasler and C Gordon Floating gate synapseswith spike time dependent plasticity Proc of 2010 IEE Int Sympon Circ Syst pp 369ndash372

50 G S Snider Nanotechnology 18 art 365202 (2007)51 J J Hopfield Proc Nath Acad Sci 79 2554 (1982)52 J D Cowan and D H Sharp Quart Rev Biophysics 21 365 (1988)53 Ouml Tuumlrel and K K Likharev Possible nanoelectronic implementation

of neuromorphic networks Proc IJCNNrsquo03 (2003) pp 365ndash37054 Y LeCun and C Cortes The MNIST Database of Handwritten Dig-

its available httpyannlecuncomexdbmnist55 J H Lee and K K Likharev Lect Notes on Comp Sci 3512 446

(2005)56 R S Sutton and A G Barto Reinforcement Learning MIT Press

Cambridge MA (1998)57 N Simonian and K K Likharev Design and simulation of molecular

single-ectron latching switches Paper in preparation

Received 29 December 2010 Accepted 14 January 2011

Sci Adv Mater 3 322ndash331 2011 331